Thank you for the responses!
@JColvin, I am applying from 0-1V to the A0 pin, the signal is just a DC voltage.
@jpeyron, currently I am only trying to use one channel in. If I use a 5V Vcc and use two resistors to drop D0 (or SDATA) down to ~3.1V, the Verilog code I have works to read in the values. My issue is when 3.3V is applied, the device doesn't behave as expected.
I have attached three images, where the white trace is SCLK, the yellow trace is CS, and the green trace is SDATA. One is using the 5V Vdd, which shows it behaving as expected as I adjust the input voltage. The other two images are with a 3.3V Vdd, where they are at two different input voltages.
I do notice that when 3.3V is supplied, sdata is sometimes a 1 during the first couple cycles when it should only be zeros, which is odd to me.