• Content Count

  • Joined

  • Last visited

1 Follower

About libswig

  • Rank

Recent Profile Visitors

The recent visitors block is disabled and is not being shown to other users.

  1. Hi, Almost there - except the sound. I have done all down to programming the device. However the sweet output sound still evades me. I suspect many things can go wrong. Can you suggest how to debug the solution? I have used leds to indicate clock and rx data handling. I also hope that attached schematics can help you spot the issue. I attach v files as well. Please note that I disabled multiplier in volume controller to make sure I run at "full throttle". Thank you for the guidance. Libor top.v axis_i2s2.v axis_volume_controller.v zcu104_Rev1.0_U1_01302018.xdc
  2. Hi, My design sources structure is as follows: top.v - m_clk : clkwiz_0 - m_i2s2 : axis_i2s2 - m_vc : axis_volume_controllertop.v Clock uses differential clock source represented by clk_n and clk_p wires. Synth message (30x, for all ports): [Vivado 12-584] No ports matched 'CLK_300_N'. ["C:/Users/h326709/Downloads/zcu104_Rev1.0_U1_01302018.xdc":589] Best Regards, Libor axis_i2s2.v axis_volume_controller.v
  3. Hi Jon, I have set up the vivado project as instructed, included constraints zcu104 XDC file. however, I receive 'set_property expects at least one object' for each port I use, running synthesis. See example for G8 pin: set_property PACKAGE_PIN G8 [get_ports "PMOD0_0"] ; set_property IOSTANDARD LVCMOS33 [get_ports "PMOD0_0"] ; set_property -dict { PACKAGE_PIN G8 IOSTANDARD LVCMOS33 } [get_ports { tx_mclk }]; Thank you for your help, Libor zcu104_Rev1.0_U1_01302018.xdc
  4. Hi Jon, You've come a long way to help me, but I am afraid you have to treat me like a total dummy 🙂. Let me share my progress: Vivado, Add Sources, axis_i2s2.v, axis_volume_controller.v, top.v Add Constraints, Cora-Z7-10-Master.xdc Default Part, Boards, ZCU104 In Project Manager, Design sources, m_clk item is decorated by question mark icon - how to treat it? Clocking Wizard pictures, why and how? As you can see, I need step-by-step coaching, if you are willing to help further, I will be happy. Libor
  5. Hi Jon, My appreciation for your prompt reply. Actually I noted this post but I must admit I was unable to apply it because I was not sure about proposed actions and some abbreviations. Please clarify or be more specific about the steps. This is what I did: Download Pmod-I2S2 Volume Control Demo from link on Vivado, Open a project, readme file states: This project is only supported in the 2017.4 version of Vivado - am I safe with Vivado 2018.3 ? Available boards are: Arty A7-35, Arty A7-100, Arty S7-25, Arty S7-50,Cora Z7-07S,Cora Z7-10,Cmod S7-25 Does it matter which one to select? Vivado, Create project, RTL Project, I get empty project for Artix-7 product family I follow readme, TCL console, CD into arty-a7-35, "source ./create_project.tcl" - ERROR: [Common 17-55] 'get_property' expects at least one object. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. Is this message to be expected? How to execute next step "add the IP to a BD, then edit in IP packager" instruction? As you can see, this is a bumpy ride and I am afraid I would be thrown in the ditch Thanks for help, Libor
  6. Hi, I was recommended Pmod audio adapter as a solution for audio capture with Xilinx ZCU104 because this board does not have audio connectors of its own. There is an I2S2 product guide for audio receiver / transmitter provided by Xilinx, but describes it only in general terms. Diligent, on the other hand, covers only its own boards in combination with the audio adapter. I need some fool proof guidance on the issue. Can you help, please? Thanks, Libor