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  1. OvidiuD

    Ethernet on Genesys 2 board

    Hello, @asmi Having looked into it, it seems that there is indeed a problem with the Vivado project in Vivado 2019.1. While we are looking into it, one possible alternative is for you to use Vivado 2015.4. I've just tested the project on it and it works as described in the guide.
  2. Hi @aadgl! Here you can find the fixed release. Indeed there was a problem with the release you tried which were solved, but not released yet. The documentation has been updated, too. Hope this fixes your issues. OvidiuD
  3. Hello, @Victor! At a first glance, it seems that your warnings are cause by the fact that you have an undeclared or unpinned clock in your design. Don't forget that constraints are case sensitive. Let me know if you find the error or not, so I can help give you further assistance if needed. Good luck!
  4. Hello, @Antonio Fasano! A discussion that might help you is this one. Also, you can find examples of projects with the HDMI in and HDMI out on our GitHub. Also, you can find a more complex project that includes more complex things, HDMI processing included here. Good luck!
  5. Hi there, @Arty7_Lover! It seems that your issue is very similar to this one: Try checking this out and see if you have any luck.
  6. Hello, @SmashedTransistors! I'm very glad you're looking forward to your project and I have to admit it actually seems very interesting! Don't hesitate to ask questions on our forum whenever you have a question, I'm sure someone will always do their best to help you and eventually succeed by working with you. Best regards, Ovidiu
  7. Hi there, wimtormans To get the answer for this question you should ask directly on the NI forum: https://forums.ni.com/ Best regards, Ovidiu
  8. OvidiuD

    register clear on raed

    Hello, kamal! Basically you have to make the register have only 0's when you give it a signal. I'd say something like this: begin if rising_edge(CLOCK) then if ClearTheRegister = '1' then MyRegister<= ( others => '0'); elsif WriteInRegister = '1' then MyRegister <= SomeNewData; end if; end if; end process; Best regards, Ovidiu
  9. OvidiuD

    Sine Wave from Pmod DA3

    Hi there, lwew96! Have you tried using a higher order Low Pass Filter? That might solve your issue. Let me know if it worked, please. Best regards, Ovidiu
  10. OvidiuD

    Partial reconfiguration

    Sadly, I believe the Xilinx support team would be of more help. I am attaching a link for you in order to either find the documentation you need or support. https://www.xilinx.com/products/intellectual-property/axi_hwicap.html#documentation Best regards, Ovidiu
  11. OvidiuD

    Partial reconfiguration

    What kind of FPGA are you using?
  12. OvidiuD

    Partial reconfiguration

    Hello, savmil! Could you please give me a more in depth explanation of your issue? What kind of strange behavior do you see? Best regards, Ovidiu
  13. Hello, @hearos! In order to help you with your request, I need some details. First of all, how is your board listed in the Device Manager(you can access Device Manager from the Control Panel)? Second of all, right click on the listing and click properties. In that new window, go to the details tab and search for "Hardware Ids" in the property combo box. Please tell us what you see listed after selecting the "Hardware Ids" property. Best regards, Ovidiu