dfergenson

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  1. My company uses a CMOD A7 to drive a set of SPI-based peripherals, a few interlocks and some slow-moving analog controls. The 0.1" headers are plenty fast for SPI interfacing and make field repairs and upgrades simple. Speaking only for our application, I would not chose a higher pin density if one were available. I will, however, probably need an upgrade path at some point either to an Artix7 105T or a Zynq Z7-20. -David
  2. Thank you. Will instructions for how to make an exchange be posted to this thread? -David
  3. Thanks. Got it. I'm going to attempt to implement the fix and will report back when I've been able to reproduce it. Do you know if this will be addressed in future revisions to the Cmod A7 product line? -David
  4. Vicentiu, Thanks for doing this. I'm having a bit of trouble identifying the pads since some of the features are covered by components. Can you possibly post a photograph so that I can attempt to perform this modification? Thanks again for looking into this problem. -David P.S. I also found that using a USB 3.0 hub made my connection much more stable.
  5. I've stumbled upon what seems to be a complete solution to this problem. First, I switched cables, which did help but I still couldn't run the ILA through the new cable. In order to get ILA working, I lowered the connection speed. To do this: 1. In the lower left corner of Vivado, right click on "Open Hardware Manager" and press the menu that pops up to close it. This is poorly labeled but what it actually does is disconnects the Cmod. 2. Regular click on "Open Target" and select "Open Hardware Target..." A window will pop up in the middle of the screen. 3. Click "next". Make sure that Local Server is selected in the popup before clicking "next" again. 4. In the next window, you'll have the option to select the connection speed. Select a slower speed and click to connect. In my case, I'm routing my USB circuitry through a PCB because I need to be able to select between bus power and PCB power. That made my connection unstable so to get things up and running I just directly connected (at the default 15000000 Hz) with a new cable. But I couldn't run ILA successfully. So I had to connect at slower speeds to use ILA (6000000) but when I did that it made the JTAG connection more stable as well, even through the PCB. I went to an extreme and the system was stable at 125000 Hz but at this speed it begins to hurt my personal productivity. I'm going to do a binary search to see what I can get away with. Can anyone else confirm that this works for them? Would anyone else care to post their successful connection speeds? If this is a complete solution, then it would seem to obviate the need for a redesign of the Cmod USB/JTAG circuitry.
  6. Please forgive a nitpicky post but if I had trouble with these issues then so will others. I looked through the Cmod A7 Reference Manual and a few pieces of critical information seem to be just plain missing. 1. The addresses for the PCB pins aren't listed. They are for the pmod but not for the pins that actually set into a socket. 2. The clock speed and address aren't listed. I've been able to figure out these values from other forum posts and from the .XDC file but can someone please put them in the manual itself? If they're already there and I somehow just missed them then I apologize and will, forthwith, get myself fitted for reading glasses. -David
  7. I just checked my Cmod A7 mating to two Sullins Connector PPPC062LFBN-RC (DigiKey p/n S7109-ND) and they fit. Because each connector is independent of the other, you'd have to solder the connectors into a PCB with the Cmod connected to make sure that they don't rock out of alignment with each other.
  8. Thank you. I will follow the Pmod specification. -David
  9. I'm preparing to embed a Cmod A7 on a PCB and I want to provide similar circuit protection for some of its pins to those found on a Pmod output. I looked at the schematics for the Basys3 and found a 200 Ohm series resistor on each output pin and a zener diode directly from pin to ground. I have two concrete questions: 1. Just to confirm, the Zener voltage should be 3.4V, right? 2. What power does Digilent recommend for the 200 Ohm resistor? Thanks. -David
  10. I think that part of the problem is that the locations of these files are inconsistent between different resource centers. I was looking for the STEP file for the Cmod A7 and I found it in the Design Resources section of the table but not in the Additional Resources area. Can you have someone look into documentation consistency among similar products? It's not the most pressing of concerns but it's also a pretty easy fix. Thanks. -David
  11. I had been referring to the Basys3 but looking at the resource page I found it. It was under the Additional Resources area. Thanks. -David
  12. The .STEP files that were attached to jpeyron's post were hugely helpful. I didn't see them among the resources on the product pages myself. If I didn't just miss them somehow, can you request that they be added? Thanks.
  13. @freakuency, I had the same problem with the HDMI example as you did and ran into the same stumbling block. Here's how I resolved the issue with @jpeyron's help. The IP report window is confusing. When you click on the Upgrade IP link, it just reminds you of the importance of checking the log and then upgrading the IP. Not helpful... But at the bottom of the screen (and this is sometimes obscured on different sized windows) is a button to upgrade the IP. If you check the box next to the out of date IP, (in the case of the HDMI Zybo Z7-20 demo, its DVI2RGB) you can update it. The outdated IP creates a downstream problem because it prevents an HDL wrapper from being created around the block diagram which you now need to do by right clicking on the .bd in the source code browser. If you do this, you can generate a bitstream. I'm still stumbling over actually getting the SDK to work. I ran into the same problem that you did and so far haven't gotten past it. @jpeyron, although it didn't help @freakuencycan you tell me where to find the .meta file to delete?
  14. I don't know if I missed it earlier or if it was just added today but the flash memory part number is absolutely mentioned in the Zybo Z7 specifications. It is a Spansion S25FL128S. Either thank you very much or else sorry to have bothered you.
  15. Thanks, Jon. I was able to synthesize and generate a bitstream and memory configuration file. I would like to note that the model of the memory is not explicitly described in the specifications and there are three models of Spansion memory that seem to fit that general description. Can the specifications be updated to reflect the actual memory module for configuration file generation? I also think that I've determined the root cause of the problem. In the -10 version of the example code, I think that all of the IP was already up to date. In the -20 version, the DVI2RGB version was 1.7 when the current version was 1.8. This hung up a critical step in the TCL script. I read through the logs and found the following error had been thrown: So the out of date IP interfered with the creation of the top level wrapper (which you instructed me to create once I had updated the IP). That wrapper was created automatically in -10. What I had done instead was specify design1.bd as the top level file for synthesis. Vivado lets you do that if you type in the name but I now realize that, while permissible, it's not a good practice because it caused those ports not to be recognized when Vivado encountered them in the .XDC file. So, if whoever maintains the Git could update that IP, that would permanently solve the problem. Thanks again for your guidance. Adding the wrapper HDL was, indeed, the missing link. -David