Thanks so much for the detailed explanation !!
I've been trying working on it and seems I *kind of* got what I expected from behavioral simulation (According to datasheet, the 12 bits of digital data are sent to the system board in 16 clock cycles with the first four bits as leading zeroes and the remaining 12 bits representing the 12 bits of data, my top module reads sample in every other 16 clock cycles to allow time to transfer). My simulation result shows:
Then I tried it on board, I tried sending the data to PC through UART, and used Realterm to read the data received, however it either gives me all 0 or something obviously not correct (since each sample is supposed to start with four leading zeros, which doesn't agree with the data I received from Realterm).
I attached my code here, I'm completely new to FPGA and verilog coding, and this is my first project. I've been stuck for quite a while and I'm just wondering if I'm on the correct direction at all. Could you help take a look at my code please? I just want to make sure what I'm trying here is not totally insane... 😢 I'm using Digilent Basys 3 and Vivado 2018.3.
Thank you very much !!