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Everything posted by andre19

  1. Hi @Ana-Maria Balas Thank you for boot file. I copied it, writed to SD card, insert to ettus e310 board, set my terminal port - don't saw any reaction, any text on terminal program. It don't work(((
  2. Dear @Ana-Maria Balas 1) I look properties of IP Zynq, when created project for Arty Z7 : properties are default: (i create boot, write to SD, insert SD and it work, by UART0 it send "Hello world). For Arty Z all Ok. : 2) I send screen of properties of Zynq IP for ettus e310 (chip clg484 chip same type, such for zedboad digilent): a) In IP Zynq by default "Memory Interfaces" Quad SPI flash are selected. For ettus i deselected MIO 1-6 (i look schematic for ettus e310 bank500 ). b) For SD0 card i selected CD (MIO_0), i decided that for ettus it must be selected
  3. Hi @Ana-Maria Balas. I look configuration of Zynq for Arty Z, then generate NEW project for Ettus chip. Properties of IP "Zynq" in both projects are same (first project for arty z chip clg400, second project for ettus chip clg484) "Or did you make a new project for Ettus E310, and generated a new boot.bin for it ?" - yes. Create boot for ettus, write to SD and insert SD to Ettus - don't work. What do you phink? Best regards.
  4. Hi @Ana-Maria Balas 1) For easily start with ettus e310 i bought Arty Z7-20 (open, programmed and supported). Made project in Vivado HLS and SDK , tested result on Arty Z7 , then in analogy created project for e310. Arty Z7 (clg400) chip and E310 (clg484 ) chip. 2) For Arty I clicked in HLS "+" IP Zynq , then open properties of Zynq. Default properties of Zynq: i created wrapper, launch SDK and wrote "Hello world" to terminal program via system debugger; and next via SD card (created BOOT file = fsbl+system wrapper+my code). All works! 3) When i probed "2)" for e310 (i use S
  5. Hi @Dareamol This is actual for me too. Could you send for me tupical project of "Hello world" ? uart from procesor MIO or EMIO you receive? I wank to look your xdc file and Zynq core settings. Best regards
  6. Hi @jpeyron Could you send for me tupical project only Zynq (without Microblaze) based of "Hello world" ? uart from procesor. I wank to look your xdc file and Zynq core settings. Best regards
  7. Hi @jpeyron That idea of Tom Taylor is good, but quality of images in article is bad, i could not to see what connector be connected( I wrote a letter to him few days ago, but don,t get any answer yet(( Best regards
  8. And what about true definition in XDC of external CLOCK and RESET, because my bitstream fall down in this two moments?
  9. Hi @jpeyron I have a reason - a next i will probe to connect Microblaze+Zynq core fore more efectivity in work. Now, i probe to started Microblaze only. And another confuse with Vivado, after generating bitstream vivado don't propouse to show "message" only "log" . And i could not to see errors(( In google i don't see how to shange this bug in report window (few hours ago i have two options, now only "View Log" P.S. You do not say any about " For external clock i write next: set_property -dict { PACKAGE_PIN F7 IOSTANDARD LVCMOS33 } [get_ports { clk_in1_0 }
  10. Hi @jpeyron It is my IP blocks: For external clock i write next: set_property -dict { PACKAGE_PIN F7 IOSTANDARD LVCMOS33 } [get_ports { clk_in1_0 }]; create_clock -period 30.303 [get_ports { clk_in1_0 }];#set Clock connected to clocking withard IP
  11. Plus How to corectly in XDC file connect CLOCK and RESET? Microblaze need clock, i have external clock and manualy in XDC write : set_property -dict { PACKAGE_PIN F7 IOSTANDARD LVCMOS33 } [get_ports { clk_in1_0 }] [DRC NSTD-1] Unspecified I/O Standard: 2 out of 53 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which i
  12. Hi @jpeyron Some questions about true/not true my understandings. In Arty A7-35 in "Block design - board"i clicked on "DDR3" and DDR3 connector will avtomaticaly conected to MIG_7 IP. In Zedboard i work with another chip wy, i manualy in XDC file wrote adresses for all DDR3 conector Some remark In Z7020 chip in IP design i added MIG_7 but IP was without out for DDR3 like in project for Arty-A7 board. Than i changed properties (double click on IP) and change type of memory and then i seen output for DDR3 (like are in screan above). What do you
  13. It is interesting article.
  14. Hi! Hi @jpeyron Nowadays i have get Zedboard) and decided to try on it soft core MicroBlaze. I created project and add IP cores in analogy with my experiment with Arty A7-35. In Arty DDR3 has been added avtomation, in Zedboard i written adreses manual in XDC for each pins : It is in .XDC file: #MEMORY DDR # ddr3_dq_0 set_property -dict { PACKAGE_PIN T21 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[0] }]; set_property -dict { PACKAGE_PIN U21 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[1] }]; set_property -dict { PACKAGE_PIN T22 IOSTANDARD LV
  15. andre19


    Change chapter...
  16. Hi everybody! Hi @jpeyron ! 1. I have board Ettus E310 With Zynq core on it. and JTAG In Vivado i have created simple project for GPIO (J12 -pin8 for board C18 for FPGA), i have changed in XDC file to GPIO output IM_1 + IM_3 2. Then lauch SDK and write my simple code (GPIO turn ON/OFF). Just i have read this example :
  17. Hi @jpeyron I have get JTAG programer Connected to board and saw next: Data cable show ARM and FPGA - maybe normal. Then, clicked "program device" and get error (( What do you think, why it do not programed FPGA via JTAG ??? - it is from Data cabel display. "[Labtoolstcl 44-513] HW Target shutdown. Closing target:" ????????? Best regards.
  18. Hi @jpeyron I will work with your information. Thanks!
  19. Hi @jpeyron I have written for Ettus - them work with GNU Radio and don't work vith Vivado. They doesn't gave me any normal consultation about work Zynq with Vivado I started to program Zynq chip via Vivado - ( i have digilent Arty A7 board and now start to work with more power core) - there are different topics about programing Zynq via Vivado in your forum. I hope, somebody from forum explain for me how to corect edit blocks in Vivado for getting data from ADC I have find schematic of conection ADC to Zynq
  20. Hi @jpeyron I start to do my next step - i want to connect Zynq to ADC via LVDS (???). About this i created new topic Best regards.
  21. Hi! In previous topic i have asked about first start with Zynq core (i have Ettus E310 board) Now it is time for connecting ADC that is on board AD9361 . I want to get some signal and receive it via ADC - i do not understand how to connect ADC (how to edit Zynq for getting data via RF board connector (via LVDS??) I have read manual (p.34) about that ADC I hope, somebody help me to edit blocks or code in Vivado and get digitalized data from A
  22. Hi @jpeyron I have used your information - it has some helped me. Thanks!) 1) I have connected .XDC file (to constarints) 2) i have Created blocks like in youtube example ( and Generate succesful bitstream. Then opened SDK and get problem in downloading code to fpga (clicked PROGRAM FPGA in SDK) - i show image. SDK don't see FPGA ((( (I give rar of my project HLS + SDK What do you phink about connec
  23. Dear @jpeyron Could you help me and create simple project for transmit to PC from chip "Hello world" (i will downloaded them and probe to program my chip . . .)? It will be my first point of teaching to program Zynq. I looked at information about pins, but confused with working with them(( Best regards.
  24. Hi @jpeyron I have ettus e310 board. I decided do not use the USRP, GNU Radio and start to program FPGA on board via Vivado - this decision is better for me. When i start to work with board, i could not create true file for write inside the chip(( 1) Block design of board 2) 3)