andre19

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  1. Hi @Dareamol This is actual for me too. Could you send for me tupical project of "Hello world" ? uart from procesor MIO or EMIO you receive? I wank to look your xdc file and Zynq core settings. Best regards
  2. Hi @jpeyron Could you send for me tupical project only Zynq (without Microblaze) based of "Hello world" ? uart from procesor. I wank to look your xdc file and Zynq core settings. Best regards
  3. Hi @jpeyron That idea of Tom Taylor is good, but quality of images in article is bad, i could not to see what connector be connected( I wrote a letter to him few days ago, but don,t get any answer yet(( Best regards
  4. And what about true definition in XDC of external CLOCK and RESET, because my bitstream fall down in this two moments?
  5. Hi @jpeyron I have a reason - a next i will probe to connect Microblaze+Zynq core fore more efectivity in work. Now, i probe to started Microblaze only. And another confuse with Vivado, after generating bitstream vivado don't propouse to show "message" only "log" . And i could not to see errors(( In google i don't see how to shange this bug in report window (few hours ago i have two options, now only "View Log" P.S. You do not say any about " For external clock i write next: set_property -dict { PACKAGE_PIN F7 IOSTANDARD LVCMOS33 } [get_ports { clk_in1_0 }]; create_clock -period 30.303 [get_ports { clk_in1_0 }];#set " Best regards
  6. Hi @jpeyron It is my IP blocks: For external clock i write next: set_property -dict { PACKAGE_PIN F7 IOSTANDARD LVCMOS33 } [get_ports { clk_in1_0 }]; create_clock -period 30.303 [get_ports { clk_in1_0 }];#set Clock connected to clocking withard IP
  7. Plus How to corectly in XDC file connect CLOCK and RESET? Microblaze need clock, i have external clock and manualy in XDC write : set_property -dict { PACKAGE_PIN F7 IOSTANDARD LVCMOS33 } [get_ports { clk_in1_0 }] [DRC NSTD-1] Unspecified I/O Standard: 2 out of 53 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: sys_rst_0, and clk_in1_0. Best regards
  8. Hi @jpeyron Some questions about true/not true my understandings. In Arty A7-35 in "Block design - board"i clicked on "DDR3" and DDR3 connector will avtomaticaly conected to MIG_7 IP. In Zedboard i work with another chip wy, i manualy in XDC file wrote adresses for all DDR3 conector Some remark In Z7020 chip in IP design i added MIG_7 but IP was without out for DDR3 like in project for Arty-A7 board. Than i changed properties (double click on IP) and change type of memory and then i seen output for DDR3 (like are in screan above). What do you phink? Best regards.
  9. It is interesting article.
  10. Hi! Hi @jpeyron Nowadays i have get Zedboard) and decided to try on it soft core MicroBlaze. I created project and add IP cores in analogy with my experiment with Arty A7-35. In Arty DDR3 has been added avtomation, in Zedboard i written adreses manual in XDC for each pins : It is in .XDC file: #MEMORY DDR # ddr3_dq_0 set_property -dict { PACKAGE_PIN T21 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[0] }]; set_property -dict { PACKAGE_PIN U21 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[1] }]; set_property -dict { PACKAGE_PIN T22 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[2] }]; set_property -dict { PACKAGE_PIN U22 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[3] }]; set_property -dict { PACKAGE_PIN W20 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[4] }]; set_property -dict { PACKAGE_PIN W21 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[5] }]; set_property -dict { PACKAGE_PIN U20 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[6] }]; set_property -dict { PACKAGE_PIN V20 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[7] }]; set_property -dict { PACKAGE_PIN AA22 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[8] }]; set_property -dict { PACKAGE_PIN AB22 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[9] }]; set_property -dict { PACKAGE_PIN AA21 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[10] }]; set_property -dict { PACKAGE_PIN AB21 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[11] }]; set_property -dict { PACKAGE_PIN AB19 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[12] }]; set_property -dict { PACKAGE_PIN AB20 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[13] }]; set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[14] }]; set_property -dict { PACKAGE_PIN AA19 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[15] }]; set_property -dict { PACKAGE_PIN V22 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dqs_p_0[0] }]; set_property -dict { PACKAGE_PIN Y20 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dqs_p_0[1] }]; set_property -dict { PACKAGE_PIN W22 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dqs_n_0[0] }]; set_property -dict { PACKAGE_PIN Y21 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dqs_n_0[1] }]; #ddr3_addr_0 set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[0] }]; set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[1] }]; set_property -dict { PACKAGE_PIN AB16 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[2] }]; set_property -dict { PACKAGE_PIN AA16 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[3] }]; set_property -dict { PACKAGE_PIN AB17 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[4] }]; set_property -dict { PACKAGE_PIN AA17 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[5] }]; set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[6] }]; set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[7] }]; set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[8] }]; set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[9] }]; set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[10] }]; set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[11] }]; set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[12] }]; set_property -dict { PACKAGE_PIN W17 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[13] }]; set_property -dict { PACKAGE_PIN AB15 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[14] }]; #ddr3_ba_0 set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 } [get_ports { ddr3_ba_0[0] }]; set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { ddr3_ba_0[1] }]; set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { ddr3_ba_0[2] }]; #ddr3_ras_n_0 set_property -dict { PACKAGE_PIN AA14 IOSTANDARD LVCMOS33 } [get_ports { ddr3_ras_n_0 }]; set_property -dict { PACKAGE_PIN Y13 IOSTANDARD LVCMOS33 } [get_ports { ddr3_cas_n_0 }]; #ddr3_we_n_0 set_property -dict { PACKAGE_PIN AA13 IOSTANDARD LVCMOS33 } [get_ports { ddr3_we_n_0 }]; #ddr3_reset_n_0 set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports { ddr3_reset_n_0 }]; set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports { ddr3_ck_p_0[0] }]; set_property -dict { PACKAGE_PIN Y15 IOSTANDARD LVCMOS33 } [get_ports { ddr3_ck_n_0[0] }]; set_property -dict { PACKAGE_PIN AB14 IOSTANDARD LVCMOS33 } [get_ports { ddr3_cke_0[0] }]; set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dm_0[0] }]; set_property -dict { PACKAGE_PIN AA18 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dm_0[1] }]; #ddr3_odt_0 set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { ddr3_odt_0[0] }]; # DDR3 STOP 1) After start generating Bitstream i get ERROR: [DRC MDRV-1] Multiple Driver Nets: Net system_i/mig_7series_0/u_system_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/write_buffer.wr_buf_out_data_reg[112]_0[0] has multiple drivers: system_i/mig_7series_0/u_system_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/mem_reg_0_15_0_5_i_4/O, and system_i/mig_7series_0/u_system_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/mem_reg_0_15_0_5_i_5/O. DRC report in Syntesys are next: and 2) Next problem place: InOutTerm #1 IO Standard LVCMOS33 does not support IN_TERM, but I/O port ddr3_dq_0[0] has IN_TERM set to UNTUNED_SPLIT_50. What is mean @IO Standard LVCMOS33 does not support IN_TERM@ ??? How to fix "1)" and "2)" ??? Best regards.
  11. andre19

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  12. Hi everybody! Hi @jpeyron ! 1. I have board Ettus E310 https://kb.ettus.com/E310/E312 With Zynq core on it. and JTAG https://www.xilinx.com/products/boards-and-kits/smartlynq-data-cable.html?_ga=2.211956244.1491345133.1565455411-227237821.1553275560 In Vivado i have created simple project for GPIO (J12 -pin8 for board https://files.ettus.com/schematics/e310/e310.pdf C18 for FPGA), i have changed in XDC file to GPIO output IM_1 + IM_3 2. Then lauch SDK and write my simple code (GPIO turn ON/OFF). Just i have read this example : https://forums.xilinx.com/t5/Embedded-Processor-System-Design/axi-gpio-output-rate/m-p/877948#M41051 #include <stdio.h> #include "platform.h" #include "xil_printf.h" #include "Xscugic.h" #include "Xil_exception.h" #include "xttcps.h" #include "xgpio.h" #include "time.h" #include "sleep.h" #include"xparameters.h" XScuGic Intc; XTtcPs_Config *Config; XTtcPs Timer; TmrCntrSetup *TimerSetup; static void SetupInterruptSystem(XScuGic *GicInstancePtr, XTtcPs *TtcPsInt); static void TickHandler(void *CallBackRef); int main() { XGpio Gpio0, output; unsigned int sl_time=1000; init_platform(); // My GPIO C18 Pin8 J12 XGpio_Initialize(&output, XPAR_AXI_GPIO_0_DEVICE_ID); XGpio_SetDataDirection(&output, 1, 0x00000000); while(1) { usleep(sl_time); XGpio_DiscreteWrite(&output, 1, 1); usleep(sl_time); XGpio_DiscreteWrite(&output, 1, 0); print("Hello World\n\r"); xil_printf("\n data writing to GPIO"); } } 3. I want to power ON at the board, and get run my application. "your application will run". Just i read this: https://reference.digilentinc.com/learn/programmable-logic/tutorials/zedboard-programming-guide/start a) I created FSBL bootloader project (boot_my) + b) created my Hello_world project added GPIO ON/OFF code to it (Zynq_C_code) IM_4 c) Then i steped by step start to do recomendation from "3" 3.1 I decided to tested text and program FLASH IM_3.1 "4. Programming the using Quad SPI" but get ERROR: ****** Xilinx Program Flash ****** Program Flash v2019.1 (64-bit) **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. Connected to hw_server @ TCP:10.0.0.2:3121 Available targets and devices: Target 0 : jsn-XSC0-Mv//////0 Device 0: jsn-XSC0-Mv//////0-4ba00477-0 Retrieving Flash info... Initialization done, programming the memory ===== mrd->addr=0xF800025C, data=0x00000005 ===== BOOT_MODE REG = 0x00000005 WARNING: [Xicom 50-100] The current boot mode is SD. If flash programming fails, configure device for JTAG boot mode and try again. Downloading FSBL... ===== mrd->addr=0xF8000110, data=0x00177EA0 ===== READ: ARM_PLL_CFG (0xF8000110) = 0x00177EA0 ===== mrd->addr=0xF8000100, data=0x0001A008 ===== READ: ARM_PLL_CTRL (0xF8000100) = 0x0001A008 ===== mrd->addr=0xF8000120, data=0x1F000400 ===== READ: ARM_CLK_CTRL (0xF8000120) = 0x1F000400 ===== mrd->addr=0xF8000118, data=0x00177EA0 ===== READ: IO_PLL_CFG (0xF8000118) = 0x00177EA0 ===== mrd->addr=0xF8000108, data=0x0001A008 ===== READ: IO_PLL_CTRL (0xF8000108) = 0x0001A008 Problem in Initializing Hardware Flash programming initialization failed. ERROR: Flash Operation Failed FROM ERROR I SAW "The current boot mode is SD." 3.2 Such as Ettus E310 has SD card, i decided to tested text and program "3. Programming the using an SD card startup" a) I added for bootload file .elf from Debug (boot_my) + b) I added .bit file + c) I added .elf file with my code from (Zynq_C_code) IM_5 + IM_6 file When i "3.4) Place your boot image file onto a fat32 formatted SD card " i use this program https://software.intel.com/en-us/get-started-galileo-windows-step1 After all this step i don't saw GPIO ON/OFF and don't saw message in terminal.(((( Could anybody help me and explain my mistakes???? Best regards.
  13. Hi @jpeyron I have get JTAG programer https://www.xilinx.com/products/boards-and-kits/smartlynq-data-cable.html Connected to board and saw next: Data cable show ARM and FPGA - maybe normal. Then, clicked "program device" and get error (( What do you think, why it do not programed FPGA via JTAG ??? 10.0.0.2 - it is from Data cabel display. "[Labtoolstcl 44-513] HW Target shutdown. Closing target:" ????????? Best regards.
  14. Hi @jpeyron I will work with your information. Thanks!
  15. Hi @jpeyron I have written for Ettus - them work with GNU Radio and don't work vith Vivado. They doesn't gave me any normal consultation about work Zynq with Vivado I started to program Zynq chip via Vivado - ( i have digilent Arty A7 board and now start to work with more power core) - there are different topics about programing Zynq via Vivado in your forum. I hope, somebody from forum explain for me how to corect edit blocks in Vivado for getting data from ADC I have find schematic of conection ADC to Zynq https://www.analog.com/media/en/technical-documentation/data-sheets/AD9361.pdf (http://files.ettus.com/schematics/e310/e310_db.pdf - i need SPI and P0 for receive data manual p.1) But i don't understand how true configure Zynq pins in VIVADO for receivered data (I don't worked with analogy types of getting data. I have experiment with STM32 - i writed adrres and read data from ADC - simple) I do not understand what to configure inside the kernel to receive information from the ADC - my problem it is low knowledge in configuration Zynq for receive data(( So far I can not understand in what sequence and what levels to put on the pins to start receiving data from the ADC. Best regards
  16. Hi @jpeyron I start to do my next step - i want to connect Zynq to ADC via LVDS (???). About this i created new topic https://forum.digilentinc.com/topic/18363-zynq-ettus-e310-adc-ad9361-via-lvds/ Best regards.
  17. Hi! In previous topic i have asked about first start with Zynq core (i have Ettus E310 board) Now it is time for connecting ADC that is on board AD9361 . I want to get some signal and receive it via ADC - i do not understand how to connect ADC (how to edit Zynq for getting data via RF board connector (via LVDS??) https://files.ettus.com/schematics/e310/e310.pdf) I have read manual (p.34) about that ADC https://www.analog.com/media/en/technical-documentation/data-sheets/AD9361.pdf I hope, somebody help me to edit blocks or code in Vivado and get digitalized data from ADC. Best regards.
  18. Hi @jpeyron I have used your information - it has some helped me. Thanks!) 1) I have connected .XDC file (to constarints) https://github.com/OrionInnov/uhd-fpga/blob/master/usrp3/top/e300/e310.xdc?_ga=2.195350511.234626281.1558874700-227237821.1553275560 2) i have Created blocks like in youtube example ( and Generate succesful bitstream. Then opened SDK and get problem in downloading code to fpga (clicked PROGRAM FPGA in SDK) - i show image. SDK don't see FPGA ((( (I give rar of my project HLS + SDK https://m.mega.dp.ua/kMWSx) What do you phink about connecting to FPGA? Best regards
  19. Dear @jpeyron Could you help me and create simple project for transmit to PC from chip "Hello world" (i will downloaded them and probe to program my chip . . .)? It will be my first point of teaching to program Zynq. I looked at information about pins, but confused with working with them(( Best regards.
  20. Hi @jpeyron I have ettus e310 board. I decided do not use the USRP, GNU Radio and start to program FPGA on board via Vivado - this decision is better for me. When i start to work with board, i could not create true file for write inside the chip(( 1) Block design of board 2) http://files.ettus.com/manual/page_usrp_e3xx.html 3) https://kb.ettus.com/E310/E312
  21. Hi @jpeyron Early i have worked with arty A7 board and programmed it via Vivado. Now i have get another board with Zynq 7020 and i start to write code in vivado - it is not Digilent board (its is very bad(( and hard to start for me ) . I choose my chip in vivado and combinated IP blocks. I want at first step to make transmitting "Hello world" to PC. But, after generating bitstream i have get errors, i don't understand hove to fix tham(( Best regards
  22. Hello! @jpeyron Dir "jpeyron" there is a picture in your answer of block design for Zynq ("hello world" generate example). But you wrote, that you used vivado 2018.3. I use vivado 2017.4, when i connect block like in your picture and start "implementation" - all be ok. When start "generate bit stream" - i get error. Could you give more pictures that explain how to edit properties of each blocks of that (Zynq core, AXI interconnect, GPIO, proc reset) ???