andre19

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  1. Hi @jpeyron I have written for Ettus - them work with GNU Radio and don't work vith Vivado. They doesn't gave me any normal consultation about work Zynq with Vivado I started to program Zynq chip via Vivado - ( i have digilent Arty A7 board and now start to work with more power core) - there are different topics about programing Zynq via Vivado in your forum. I hope, somebody from forum explain for me how to corect edit blocks in Vivado for getting data from ADC I have find schematic of conection ADC to Zynq https://www.analog.com/media/en/technical-documentation/data-sheets/AD9361.pdf (http://files.ettus.com/schematics/e310/e310_db.pdf - i need SPI and P0 for receive data manual p.1) But i don't understand how true configure Zynq pins in VIVADO for receivered data (I don't worked with analogy types of getting data. I have experiment with STM32 - i writed adrres and read data from ADC - simple) I do not understand what to configure inside the kernel to receive information from the ADC - my problem it is low knowledge in configuration Zynq for receive data(( So far I can not understand in what sequence and what levels to put on the pins to start receiving data from the ADC. Best regards
  2. Hi @jpeyron I start to do my next step - i want to connect Zynq to ADC via LVDS (???). About this i created new topic https://forum.digilentinc.com/topic/18363-zynq-ettus-e310-adc-ad9361-via-lvds/ Best regards.
  3. Hi! In previous topic i have asked about first start with Zynq core (i have Ettus E310 board) Now it is time for connecting ADC that is on board AD9361 . I want to get some signal and receive it via ADC - i do not understand how to connect ADC (how to edit Zynq for getting data via RF board connector (via LVDS??) https://files.ettus.com/schematics/e310/e310.pdf) I have read manual (p.34) about that ADC https://www.analog.com/media/en/technical-documentation/data-sheets/AD9361.pdf I hope, somebody help me to edit blocks or code in Vivado and get digitalized data from ADC. Best regards.
  4. Hi @jpeyron I have used your information - it has some helped me. Thanks!) 1) I have connected .XDC file (to constarints) https://github.com/OrionInnov/uhd-fpga/blob/master/usrp3/top/e300/e310.xdc?_ga=2.195350511.234626281.1558874700-227237821.1553275560 2) i have Created blocks like in youtube example ( and Generate succesful bitstream. Then opened SDK and get problem in downloading code to fpga (clicked PROGRAM FPGA in SDK) - i show image. SDK don't see FPGA ((( (I give rar of my project HLS + SDK https://m.mega.dp.ua/kMWSx) What do you phink about connecting to FPGA? Best regards
  5. Dear @jpeyron Could you help me and create simple project for transmit to PC from chip "Hello world" (i will downloaded them and probe to program my chip . . .)? It will be my first point of teaching to program Zynq. I looked at information about pins, but confused with working with them(( Best regards.
  6. Hi @jpeyron I have ettus e310 board. I decided do not use the USRP, GNU Radio and start to program FPGA on board via Vivado - this decision is better for me. When i start to work with board, i could not create true file for write inside the chip(( 1) Block design of board 2) http://files.ettus.com/manual/page_usrp_e3xx.html 3) https://kb.ettus.com/E310/E312
  7. Hi @jpeyron Early i have worked with arty A7 board and programmed it via Vivado. Now i have get another board with Zynq 7020 and i start to write code in vivado - it is not Digilent board (its is very bad(( and hard to start for me ) . I choose my chip in vivado and combinated IP blocks. I want at first step to make transmitting "Hello world" to PC. But, after generating bitstream i have get errors, i don't understand hove to fix tham(( Best regards
  8. Hello! @jpeyron Dir "jpeyron" there is a picture in your answer of block design for Zynq ("hello world" generate example). But you wrote, that you used vivado 2018.3. I use vivado 2017.4, when i connect block like in your picture and start "implementation" - all be ok. When start "generate bit stream" - i get error. Could you give more pictures that explain how to edit properties of each blocks of that (Zynq core, AXI interconnect, GPIO, proc reset) ???