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  1. Hi @Ana-Maria Balas Thank you for boot file. I copied it, writed to SD card, insert to ettus e310 board, set my terminal port - don't saw any reaction, any text on terminal program. It don't work(((
  2. It is for Ettus e310 project:
  3. Dear @Ana-Maria Balas 1) I look properties of IP Zynq, when created project for Arty Z7 : properties are default: (i create boot, write to SD, insert SD and it work, by UART0 it send "Hello world). For Arty Z all Ok. : 2) I send screen of properties of Zynq IP for ettus e310 (chip clg484 chip same type, such for zedboad digilent): a) In IP Zynq by default "Memory Interfaces" Quad SPI flash are selected. For ettus i deselected MIO 1-6 (i look schematic for ettus e310 bank500 ). b) For SD0 card i selected CD (MIO_0), i decided that for ettus it must be selected c) I selected UART0 (MIO_14_15) 3) What do you phink? Where could be mistake ? What properties of Zynq i must to set for ettus e310? Best regards.
  4. Hi @Ana-Maria Balas. I look configuration of Zynq for Arty Z, then generate NEW project for Ettus chip. Properties of IP "Zynq" in both projects are same (first project for arty z chip clg400, second project for ettus chip clg484) "Or did you make a new project for Ettus E310, and generated a new boot.bin for it ?" - yes. Create boot for ettus, write to SD and insert SD to Ettus - don't work. What do you phink? Best regards.
  5. Hi @Ana-Maria Balas 1) For easily start with ettus e310 i bought Arty Z7-20 (open, programmed and supported). Made project in Vivado HLS and SDK , tested result on Arty Z7 , then in analogy created project for e310. Arty Z7 (clg400) chip and E310 (clg484 ) chip. 2) For Arty I clicked in HLS "+" IP Zynq , then open properties of Zynq. Default properties of Zynq: i created wrapper, launch SDK and wrote "Hello world" to terminal program via system debugger; and next via SD card (created BOOT file = fsbl+system wrapper+my code). All works! 3) When i probed "2)" for e310 (i use SD card) - e310 don't start((( 4) What do you phink i need to change in project or properties in Zynq IP ???? 5) Please, look again on schematim of e310 (bank 500 - input for SD , boot mode) Best regards
  6. Hi @Dareamol This is actual for me too. Could you send for me tupical project of "Hello world" ? uart from procesor MIO or EMIO you receive? I wank to look your xdc file and Zynq core settings. Best regards
  7. Hi @jpeyron Could you send for me tupical project only Zynq (without Microblaze) based of "Hello world" ? uart from procesor. I wank to look your xdc file and Zynq core settings. Best regards
  8. Hi @jpeyron That idea of Tom Taylor is good, but quality of images in article is bad, i could not to see what connector be connected( I wrote a letter to him few days ago, but don,t get any answer yet(( Best regards
  9. And what about true definition in XDC of external CLOCK and RESET, because my bitstream fall down in this two moments?
  10. Hi @jpeyron I have a reason - a next i will probe to connect Microblaze+Zynq core fore more efectivity in work. Now, i probe to started Microblaze only. And another confuse with Vivado, after generating bitstream vivado don't propouse to show "message" only "log" . And i could not to see errors(( In google i don't see how to shange this bug in report window (few hours ago i have two options, now only "View Log" P.S. You do not say any about " For external clock i write next: set_property -dict { PACKAGE_PIN F7 IOSTANDARD LVCMOS33 } [get_ports { clk_in1_0 }]; create_clock -period 30.303 [get_ports { clk_in1_0 }];#set " Best regards
  11. Hi @jpeyron It is my IP blocks: For external clock i write next: set_property -dict { PACKAGE_PIN F7 IOSTANDARD LVCMOS33 } [get_ports { clk_in1_0 }]; create_clock -period 30.303 [get_ports { clk_in1_0 }];#set Clock connected to clocking withard IP
  12. Plus How to corectly in XDC file connect CLOCK and RESET? Microblaze need clock, i have external clock and manualy in XDC write : set_property -dict { PACKAGE_PIN F7 IOSTANDARD LVCMOS33 } [get_ports { clk_in1_0 }] [DRC NSTD-1] Unspecified I/O Standard: 2 out of 53 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: sys_rst_0, and clk_in1_0. Best regards
  13. Hi @jpeyron Some questions about true/not true my understandings. In Arty A7-35 in "Block design - board"i clicked on "DDR3" and DDR3 connector will avtomaticaly conected to MIG_7 IP. In Zedboard i work with another chip wy, i manualy in XDC file wrote adresses for all DDR3 conector Some remark In Z7020 chip in IP design i added MIG_7 but IP was without out for DDR3 like in project for Arty-A7 board. Than i changed properties (double click on IP) and change type of memory and then i seen output for DDR3 (like are in screan above). What do you phink? Best regards.
  14. It is interesting article.
  15. Hi! Hi @jpeyron Nowadays i have get Zedboard) and decided to try on it soft core MicroBlaze. I created project and add IP cores in analogy with my experiment with Arty A7-35. In Arty DDR3 has been added avtomation, in Zedboard i written adreses manual in XDC for each pins : It is in .XDC file: #MEMORY DDR # ddr3_dq_0 set_property -dict { PACKAGE_PIN T21 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[0] }]; set_property -dict { PACKAGE_PIN U21 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[1] }]; set_property -dict { PACKAGE_PIN T22 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[2] }]; set_property -dict { PACKAGE_PIN U22 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[3] }]; set_property -dict { PACKAGE_PIN W20 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[4] }]; set_property -dict { PACKAGE_PIN W21 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[5] }]; set_property -dict { PACKAGE_PIN U20 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[6] }]; set_property -dict { PACKAGE_PIN V20 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[7] }]; set_property -dict { PACKAGE_PIN AA22 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[8] }]; set_property -dict { PACKAGE_PIN AB22 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[9] }]; set_property -dict { PACKAGE_PIN AA21 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[10] }]; set_property -dict { PACKAGE_PIN AB21 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[11] }]; set_property -dict { PACKAGE_PIN AB19 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[12] }]; set_property -dict { PACKAGE_PIN AB20 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[13] }]; set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[14] }]; set_property -dict { PACKAGE_PIN AA19 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dq_0[15] }]; set_property -dict { PACKAGE_PIN V22 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dqs_p_0[0] }]; set_property -dict { PACKAGE_PIN Y20 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dqs_p_0[1] }]; set_property -dict { PACKAGE_PIN W22 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dqs_n_0[0] }]; set_property -dict { PACKAGE_PIN Y21 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dqs_n_0[1] }]; #ddr3_addr_0 set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[0] }]; set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[1] }]; set_property -dict { PACKAGE_PIN AB16 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[2] }]; set_property -dict { PACKAGE_PIN AA16 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[3] }]; set_property -dict { PACKAGE_PIN AB17 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[4] }]; set_property -dict { PACKAGE_PIN AA17 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[5] }]; set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[6] }]; set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[7] }]; set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[8] }]; set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[9] }]; set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[10] }]; set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[11] }]; set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[12] }]; set_property -dict { PACKAGE_PIN W17 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[13] }]; set_property -dict { PACKAGE_PIN AB15 IOSTANDARD LVCMOS33 } [get_ports { ddr3_addr_0[14] }]; #ddr3_ba_0 set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 } [get_ports { ddr3_ba_0[0] }]; set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { ddr3_ba_0[1] }]; set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { ddr3_ba_0[2] }]; #ddr3_ras_n_0 set_property -dict { PACKAGE_PIN AA14 IOSTANDARD LVCMOS33 } [get_ports { ddr3_ras_n_0 }]; set_property -dict { PACKAGE_PIN Y13 IOSTANDARD LVCMOS33 } [get_ports { ddr3_cas_n_0 }]; #ddr3_we_n_0 set_property -dict { PACKAGE_PIN AA13 IOSTANDARD LVCMOS33 } [get_ports { ddr3_we_n_0 }]; #ddr3_reset_n_0 set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports { ddr3_reset_n_0 }]; set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports { ddr3_ck_p_0[0] }]; set_property -dict { PACKAGE_PIN Y15 IOSTANDARD LVCMOS33 } [get_ports { ddr3_ck_n_0[0] }]; set_property -dict { PACKAGE_PIN AB14 IOSTANDARD LVCMOS33 } [get_ports { ddr3_cke_0[0] }]; set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dm_0[0] }]; set_property -dict { PACKAGE_PIN AA18 IOSTANDARD LVCMOS33 } [get_ports { ddr3_dm_0[1] }]; #ddr3_odt_0 set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { ddr3_odt_0[0] }]; # DDR3 STOP 1) After start generating Bitstream i get ERROR: [DRC MDRV-1] Multiple Driver Nets: Net system_i/mig_7series_0/u_system_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/write_buffer.wr_buf_out_data_reg[112]_0[0] has multiple drivers: system_i/mig_7series_0/u_system_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/mem_reg_0_15_0_5_i_4/O, and system_i/mig_7series_0/u_system_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/mem_reg_0_15_0_5_i_5/O. DRC report in Syntesys are next: and 2) Next problem place: InOutTerm #1 IO Standard LVCMOS33 does not support IN_TERM, but I/O port ddr3_dq_0[0] has IN_TERM set to UNTUNED_SPLIT_50. What is mean @IO Standard LVCMOS33 does not support [email protected] ??? How to fix "1)" and "2)" ??? Best regards.