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  1. Hi @[email protected], thank you very much for your detailed answer and thank you for looking into the Nexys 4 DDR schematic. Currently I am operating the board using the USB port of my Mac. It worked with "everything" so far, so it took me a while even thinking that the problem might be tied to current. But the SDHC cards which are showing this random erroneous behaviour are kind of "smelling" like a current problem. => Now having read your post, I will go and buy myself a wall power supply, test again and report back in this forum. About the reset line controlling if mains power is
  2. Hi Jon, thank you for your feedback! I already experimented with larger drive values (I even tried switching from LVCMOS33 to LVTTL, because there, DRIVE can go as high as 24, whereas it can be only 16 as a maximum, whenusing LVCMOS33). Unfortunatelly all this did not help. Do you know by chance, if inside Nexys' SD card reader is some kind of a "driver" IC that utilizes external power - or - if the FPGA is driving the SD card directly? Best regards Mirko
  3. Hi all, I am using a Nexys 4 DDR board to interface microSD and microSDHC cards using the SPI mode. (For those interested in what the whole thing is all about, click here.) Might it be, that microSD cards are needing current in the range of 10mA (e.g. look at Transcend's 2GB SD card datasheet - link) and microSDHC (SDHC vs SD) are needing 10x of this, e.g. look here at Samsung's 32GB SDHC card: How much current is the Nexys 4 DDR SD Card slot able to supply? The first c
  4. Thank you for the hint about the looperdemo! (BTW: I already up-voted your first answer, but the system is showing this question still as "has no best answer" - no idea why)
  5. Hi Tommy, thank you very much! This indeed helps a lot as it brings my thinking on the right track. I'll immediatelly start digging through the Xilinx MIG Documentation. Mirko
  6. Hi all, I am creating a custom CPU on the Nexys 4 DDR. At 100 MHz system clock, it executes commands at about 20 MIPS on average. I used async SRAM in past, this was a piece of cake as the SRAM was always faster than my CPU. But now, being on the Nexys 4 DDR, I'd like to leverage the on board DDR RAM. Having a look at Mihaita Nagy's DDR to SRAM component (link: I was a bit surprised: On the reference page you can read, that an async. read operation of a single data word takes 210ns. Is this realistic or maybe a typo? 210ns means that the max r