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  1. Hi @[email protected], thank you very much for your detailed answer and thank you for looking into the Nexys 4 DDR schematic. Currently I am operating the board using the USB port of my Mac. It worked with "everything" so far, so it took me a while even thinking that the problem might be tied to current. But the SDHC cards which are showing this random erroneous behaviour are kind of "smelling" like a current problem. => Now having read your post, I will go and buy myself a wall power supply, test again and report back in this forum. About the reset line controlling if mains power is fed into the card: This is *very* interessting indeed! Because the card stays in the SPI mode also after asserting the RESET control. But if I "manually" power cycle the card, i.e. removing it from the reader and putting it back in again, then it is in native mode and I need to switch it back to SPI. So are you sure about this "asserting RESET is equivalent to taking power away"? (Talking about Nexys' microSD card reader.) Here is a diagram, that shows the microSD wiring: The CS (aka RESET) is connected to a line called CAT3 and VCC seems separate. Sorry, if my questions seem stupid - I am a beginner - and I am just wondering, why a lot of people (not only me in my code (LINK)) are asserting the reset line pretty regularly after sending any SPI CMD to the card. Do I mix up things here? One small other detail: If I get you right, I can change this line in my UCF file: NET "SD_MISO" LOC = C2 | IOSTANDARD = LVCMOS33 | PULLUP; to this line NET "SD_MISO" LOC = C2 | IOSTANDARD = LVCMOS33; because the Nexys 4 DDR's microSD card reader already is wired in a way that the pull-ups are there and I do not need to use the FPGA's internal pull-ups, right? Thanks again and best regards Mirko
  2. Hi Jon, thank you for your feedback! I already experimented with larger drive values (I even tried switching from LVCMOS33 to LVTTL, because there, DRIVE can go as high as 24, whereas it can be only 16 as a maximum, whenusing LVCMOS33). Unfortunatelly all this did not help. Do you know by chance, if inside Nexys' SD card reader is some kind of a "driver" IC that utilizes external power - or - if the FPGA is driving the SD card directly? Best regards Mirko
  3. Hi all, I am using a Nexys 4 DDR board to interface microSD and microSDHC cards using the SPI mode. (For those interested in what the whole thing is all about, click here.) Might it be, that microSD cards are needing current in the range of 10mA (e.g. look at Transcend's 2GB SD card datasheet - link) and microSDHC (SDHC vs SD) are needing 10x of this, e.g. look here at Samsung's 32GB SDHC card: How much current is the Nexys 4 DDR SD Card slot able to supply? The first card I wrote about above (Transcend's 2GB SD V2 card) works fine with my controller, the second card (Samsung's) is not even initializing (no response to CMD0). (Some other SDHC cards are working with my controller, see below.) Are there some settings I need to do in the UCF file, e.g. fast SLEW rate or another value for DRIVE (to supply more current)? Currently my UCF file looks like this: ##Micro SD Connector NET "SD_RESET" LOC = E2 | IOSTANDARD = LVCMOS33; NET "SD_CLK" LOC = B1 | IOSTANDARD = LVCMOS33; NET "SD_MOSI" LOC = C1 | IOSTANDARD = LVCMOS33; NET "SD_MISO" LOC = C2 | IOSTANDARD = LVCMOS33 | PULLUP; Here is the source (Link) of my controller. I tested it with ~40 cards. 20 of them are SD cards Version 1 and Version 2 (from 64 MB up to two GB): Works fine and stable with all of them. 20 of them are SDHC. When it comes to SDHC, it works with about 50% of the cards (well - works kind of: I need to reset after each read command). The other 50% are showing really strange behaviours: Some are only reporting themselves as a SDHC during the coldstart/hard reset (insert card) and from then on "claim" to be a SD V2 card, others are initializing well but when it comes to reading, they never send a R1 on READ_BLOCK, etc. While googling I found some comments in forums, that strange behaviour might be rooted in a lack of current, so this is the background of my question. Best regards Mirko
  4. Thank you for the hint about the looperdemo! (BTW: I already up-voted your first answer, but the system is showing this question still as "has no best answer" - no idea why)
  5. Hi Tommy, thank you very much! This indeed helps a lot as it brings my thinking on the right track. I'll immediatelly start digging through the Xilinx MIG Documentation. Mirko
  6. Hi all, I am creating a custom CPU on the Nexys 4 DDR. At 100 MHz system clock, it executes commands at about 20 MIPS on average. I used async SRAM in past, this was a piece of cake as the SRAM was always faster than my CPU. But now, being on the Nexys 4 DDR, I'd like to leverage the on board DDR RAM. Having a look at Mihaita Nagy's DDR to SRAM component (link: I was a bit surprised: On the reference page you can read, that an async. read operation of a single data word takes 210ns. Is this realistic or maybe a typo? 210ns means that the max read speed would be 4,76 MHz. This seems to slow to be true. So did I maybe get something wrong (I am a pretty new to DDR RAM topics therefore this might be the case). If I did not get it wrong: Just being curious: Why is it so slow? Are there faster ways to work with the DDR RAM? Thank you and best regards Mirko