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  1. Hi @mmedrano, did you ever get your SPI slave working? I'm attempting the same thing and running into some issues with the IP core. Long story short, the core sometimes does not register data from the master - bit 0 in the status register at 0x64 remains 0, indicating RX FIFO is empty - despite what looks like a good SPI transaction on the logic analyzer. Wondering if there were any tricks you used to get this working. Thanks, K