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  1. Thank for your great sample @xc6lx45, and @zygot about your sharing! I implemented the FIFO with BRAM yesterday. The attached files are what I did. Please correct me if you have time! Thank you very much! Have a nice day! Best regards, Charlie.
  2. Hi @xc6lx45, Thank for your response! Well, to be honest, I don't have hands-on experience with e.g. CMOS ICs and your advices is very useful. My understanding is I can implement on-chip FIFO for my project without any memory capacity problem? Does it mean that I can use more than 1 block RAM for 1 FIFO? (Sorry, I am not clear about your saying "...but a very expensive FIFO."). Thank you very much! Best regards, Charlie.
  3. Hi @jamey.hicks, We are going to use Kintex 7 XC7K160T and want to store 131071 samples (18 bits per sample) in FIFO. However, maximum RAM block of Kintex 7 is 36 Kb. I think we have not enough RAM capacity (Please correct me!). This is the reason why we have to use an external FIFO. Please give us suggestion! Thank you! Best regards, Charlie.
  4. Hi @xc6lx45, Thank for your response! I have read this data sheet There are a lot of listed pins. In my old design, I used an internal IP FIFO for this function and I only used some signals, for example: data_out,fifo_full, fifo_empty, fifo_threshold, fifo_overflow, fifo_underflow,clk, rst_n, wr, rd, data_in,... How can I apply my old design with the external FIFO via an interface instead the internal FIFO? Do I must use all pins of external FIFO? I followed this example (for ADC) but it is so simple. Please correct me or give me suggestion! Thanks! Charlie.
  5. Hello Community, I am a newbie and am using Xilinx Vivado 2018.1. I have a project with Kintex 7. I want to connect an external FIFO ( 72T18125L4 ) to Kintex 7 and I want to implement an interface in Kintex 7 to communicate with this FIFO. Please give me the idea! Sorry if I posted in wrong place! :( Thank you very much! Best regards, Charlie.