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  1. You guys should put in some protection to fix that on future board revs. Also I can't find any warnings about this in the on-line reference manual.
  2. If I push the SRST or POR buttons I can re-program the FPGA and then reload the code via the SDK/debugger and everything works. I'd just like to understand why the VDMA won't initialize properly following a soft-boot by the debugger.... it seems like the _ChannelInit () and _ChannelReset() should be enough to get the peripheral working properly - I wouldn't have expected a full bitstream re-load to be necessary. Probably there's something that's not being fully re-initialized by the Xilinx SDK code. I tried reversing the order of _ChannelInit() and _ChannelReset() but I still get the error on a soft-boot. A couple of other things... I notice that the board stays powered if I remove the USB connection but leave HDMI Out connected (when my external monitor is powered on). HDMI is only spec'd up to 50mA so the Arty shouldn't be running off that. Also, I needed to modify the frame-buffer declaration in display_demo.c to avoid an occasional alignment-related error: u8 frameBuf[DISPLAY_NUM_FRAMES][DEMO_MAX_FRAME] __attribute__((aligned(16))); // need to specify alignment or we sometimes get "Unaligned address 0: 12050c without DRE" error during DMA config - Jay
  3. I'm having a problem with the Arty Z7 HDMI Out demo (https://reference.digilentinc.com/learn/programmable-logic/tutorials/arty-z7-hdmi-demo/start). I can build, start and run the demo and it works just fine after a power-cycle, but if I then re-load and re-start the SDK code (via the debugger) without re-loading the FPGA bitstream I get the following error and there is no output from the HDMI port: Read channel reset failed 11000 VDMA Configuration Initialization failed 1 (error is happening in XAxiVdma_CfgInitialize(), right after XAxiVdma_ChannelInit(RdChannel); and XAxiVdma_ChannelReset(RdChannel); If I re-load the bitstream before re-launching the code things work fine, but it doesn't seem like I should have to reload the bitstream every time. Any idea what's going on? I'm using Vivado 2018.3 and version 6.3 (rev 6) of the VDMA IP.