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Everything posted by vttay03

  1. I finally got it running, I think it had to do with the way the project cache was interacting with OOC synthesis runs. In the attached screenshot under Generate Output Products, I changed "Synthesis Options" to "Global" and everything started working suddenly. I think forcing it to re-synthesize everything cleared something. Hoping to be able to revert back to "OOC per IP" to speed up the synthesis process after I get familiar with it all.
  2. I'm trying to integrate a custom IP module (AXI4 peripheral) with the Vivado IP Integrator flow on the Arty-A7 board. I've followed the tutorial outlined here: https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-creating-custom-ip-cores/start I am able to successfully generate a bitstream - my PWM signals should be wired out to the PMOD JB connector. However, nothing works once I try to launch an application from within SDK. Even something as simple as "Hello World" fails to run. The board support package, libraries, and applications all compile without issu
  3. Hi @jpeyron-- Just wanted to follow-up and let you know this all worked after rolling back to 2017.4 and using the offset you provided. Thanks for the help!
  4. Any luck? I tried a few different addresses higher than 0x00C00000 but still not working. I pulled the datasheet for the SPI flash and it looks like the 128 Mb part has addresses up to 0x00FFFFFF. Haven't had time to investigate how to calculate the bitstream size to ensure it's not overwriting the stored application once that's loaded into offset 0x0.
  5. I'm stumped and have been pouring through the posts in these forums over the last couple of days but can't quite get to a solution. I know this has sort of been beaten to death...so take it easy on me. I'm trying to get the Arty A7-100T board to boot from SPI flash on power-up. I'll try to go in the order of which I've configured things as concisely as possible...any insight or help is much appreciated. IP block in Vivado is customized as shown in image below. In addition, I've connected 'ext_spi_clk' to a 50MHz clock generated by the clocking wizard. Bitstream generates succes