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  1. Hi All, I have nine 8-bit values that I want to add using the dsp48e2 slice of ZCU104 Evaluation kit. As an example I tried this code from the Xilinx answer records(https://www.xilinx.com/support/answers/66429.html). I want to implement the second approach: "Two of the inputs are free to come from any source and one input comes from an internal DSP48 feedback signal as in a MAC." But after synthesis even the original verilog code is inferring 2 DSP slices. Am I interpreting things wrong or is there any bug in the code? I created this VHDL equivalent of the Verilog code from X
  2. Hi @BogdanVanca, Thanks, it was 9600 so changed it to 115200. I have to change it everytime I start TeraTerm. Is it possible to save the configurations? Best regards, Lrni
  3. Hi, I am trying to learn about Zynq APSoC using Zybo 7z020. I have successfully completed all steps of this tutorial :https://reference.digilentinc.com/vivado/getting-started-with-ipi/2018.2 I have a problem that Tera Term is always printing square brackets instead of the expected output as shown in this tutorial. I am using Vivado 2018.3 with SDK 2018.3 on Window 10. Below is the screen snapshot of the problem. Could anybody please help. Thank you very much Lrni