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Everything posted by RelativeHardware

  1. Hello everybody, I have a little issue with a project i'm trying. I want to test writing some data with Matlab to the DDR memory on the arty-s7. I have tried connecting the gpio via axi to the jtag to axi and that worked great. Now i put the ddr memory in the design block diagram and it's not working like i expect. The error is weird that it's not connected to mig_7series_0/ui_clk_sync_rst but gives an error that there is a mismatch between them. Does anybody see a mistake in my wiring and give me any pointers. See the attached block diagram and the error.
  2. Hello everyone. Recently I bought the Pmod i2s2: stereo Audio Input and Output module. I got this working with the example project. As part of the exercise I even translated the I2S part from Verilog to VHDL, and it’s working great by tying the output AXIS directly to the input (without the volume control part). digilent pmod i2s2 code My own vhdl equivalent What I’m a bit confused about, and this may be my limited knowledge of FPGA’s, is that everything is handled on the rising edge of the clock. For example in the digilent pmod i2s2 code in line 135 and 136 the rx_data_l and r register are written on the posedge of the axis_clk. So eventually you get the waveform as in the picture. So far I understand this principle clearly. What I don’t get is why this data on the receive side of the axi is read in on the posedge of the axis_clk. In line 83 and 85 the input data of the axis is written to tx_data_r and l. How can this happen correctly, doesn’t the data bus need some time to change the values. Now it seems that the data is written and read at exactly the same time. Now I want to extend this project by writing the samples into blockram and have the same issue. Can you write the address and data on the same clock as the blockram writes the data, or is it better to write the data on the falling edge for example.