• Content Count

  • Joined

  • Last visited

About aadgl

  • Rank

Recent Profile Visitors

The recent visitors block is disabled and is not being shown to other users.

  1. aadgl

    Vitas tutorial

    SHORT STORY FOR HELLO WORLD ON ARTY A7: (a) Install Vitis 2019.2 (includes Vivado) (b) Connect FPGA board via USB and open terminal emulator at 9600 baud (c) Vivado is used to create the HDL, BD, etc parts of project (d) Vitis replaces the SDK VIVADO (1) Create BD as usual with these adds: > MicroBlaze, from IP > sys_clock, from board > reset, from board > usb_uart, from board (2) Fix "reset": Invert resetn in clk_wiz_0, Output Clocks, Active Low, then reconnect (3) ... Create HDL Wrapper then Generate Bitstream (4) File > Export > Export Hardware, with "[x] Include Bitstream" Note this generates .XSA, needed in step (9) (5) Tools > Launch Vitis VITIS (6) Select Workspace for Vitis, [Launch] (7) Create Application Project (8) Enter a Project name "name", [Next], needed in step (14) (9) Select "Create a new platform from hardware (XSA)" tab Click the blue plus sign Select the .XSA file from step (4), [Open], [Next] (10) Domain, [Next] (11) Template, Hello World, [Finish] (12) Right click on "name" from (8) in Vitis Explorer Select "Build Project" (13) Xilinx > Program FPGA (14) Right click on "name" from (8) in Explorer Select "Run As" > "Launch on Hardware ..." (15) "Hello World" should print to terminal emulator Vitis.pdf Vivado.pdf
  2. Worked immediately with 2019.2 versions of Vivado and Vitis
  3. I am having the same problem with Cora Z7-07S (xc7z007sclg400-1) in Vivado 2019.1. (a) Create and Test an application that loops through "Hello World" (b) In same SDK project, Create FSBL Application (c) Create Boot Image for the "Hello World" application (d) Format 16GB SD Card Fat 32 with Default Allocation Size (e) Copy BOOT.bin to SD Card, then eject Card (f) Power down Cora (g) Install JP2 to short both pins (h) Insert SD Card and power-up Cora (i) Connect Putty to Cora's COM port (same that worked in (a)) (j) Wait, watch, press SRST button, no traffic from Cora to Putty, no flicker to Cora Com LED, etc I tried the BOOT.bin in the project for the other Cora FPGA, by jpeyron, above, 8/31/2018. Same results. I have tried several other SD Card, one works with another Zynq board. Any clues, other settings, would be appreciated. Thanks, Dave
  4. Hi OvidiuD, Yes, that works very well, thanks. Dave
  5. Ok, got it, will try and report back, thanks.
  6. Hi artvvb, The Nexsys board looks nice. The demo does drive a speaker, but wasn't the right starting point for my project. I have since adapted from these examples: > http://www.fpgadeveloper.com/2014/08/using-the-axi-dma-in-vivado.html > https://www.xilinx.com/support/answers/57562.html The first gets a Zynq block diagram setup and the second has the C code. The second is referenced from this page that has three other examples, including interrupts. > https://www.xilinx.com/support/answers/57550.html These examples are good to get going, need significant work (including bug fixes), but do have enough working to get started. A month later I have several Zynq versions of Stream/FIFO/SimpleDMA working, one running 250 MB/sec. I have also adapted the Zynq work to Artix. Lots of twists and turns along the way, but doable. Your "general thoughts" were helpful. Thanks, Dave
  7. Hi JColvin, Thanks, very much, for looking into it. Let me know what is found. Dave
  8. Not sure of the underlying problem ... Often the BSP folder needs to be rebuilt to get the compiler to find include files when compiling the Application (a) Right click on the bsp folder, it will open a menu (b) Left click on "Refresh" That should recompile the BSP folder. Recompiling the Application may then work. Below is a snapshot, extras at the bottom are unwanted copies, not sure how to delete them.
  9. Hi , I have a new Zybo Z7-20 that is running other vhdl/arm code well under Win10. I am trying to run this demo in Vivado 2018.2 > Zybo-Z7-20-pcam-5c-2018.2-1.zip These are results from the numbered steps in README.md: > Steps 1-3, OK, except project is out of date, continue w/o rebuild > Steps 4-17, FPGA programs OK, etc > Step 18, Fails to run - Trying to run the c program reports the executable doesn't exist - Build yields "ps7_init.h" is missing ... - Copy "ps7_init.h" and "ps7_init.c" to sdk ... src folder - Build yields "ff.h" missing error ... - Modify BSP to include "xiffs" - Build is sucessful - Cycle power, restart SDK, terminal, reprogram FPGA, etc - C program run, but visible change on Zybo or HDMI - Add "xil_printf("Hello World\r\n");" at top of main() in main.c - Cycle everything and run, prints "Hello World" and stalls > Step 18, single step in debug: - Boots from JTAG - Never returns from "FsblHandoffJtagExit();" - Stalls in assembly at the "wfe" call: FsblHandoffJtagExit: mcr 15,0,r0,cr7,cr5,0 /* Invalidate Instruction cache */ mcr 15,0,r0,cr7,cr5,6 /* Invalidate branch predictor array */ dsb isb /* make sure it completes */ ldr r4, =0 mcr 15,0,r4,cr1,cr0,0 /* disable the ICache and MMU */ isb /* make sure it completes */ Loop: wfe b Loop I was able to rebuild the project and needed to find/copy these .xdc files to build in Vivado: > Zybo-Z7-20-pcam-5c.srcs\sources_1\bd\system\ip\system_MIPI_CSI_2_RX_0_0\hdl\line_buffer\line_buffer\line_buffer.xdc > Zybo-Z7-20-pcam-5c.srcs\sources_1\bd\system\ip\system_MIPI_CSI_2_RX_0_0\hdl\cdc_fifo\cdc_fifo.xdc > Zybo-Z7-20-pcam-5c.srcs\sources_1\bd\system\ip\system_MIPI_CSI_2_RX_0_0\hdl\cdc_fifo\cdc_fifo_clocks.xdc Then needed to add the same files to SDK as described above. The new build has the same problem as the "out of date" version from the zip, stalls at "wfe". The Zybo Z7 has worked very well for other projects in Vivado 2019.1 Please advise on corrective actions, web pages I missed, etc. Thanks, Dave
  10. The version of "arty_a7_gpio_interrupt.zip" appears to have been modified and doesn't work: (A) The two commented lines at the bottom need to be uncommented: DOESN"T WORK: int Init_Interrupt(void) { . . . . //XGpio_InterruptEnable(&Gpio, 0xf); usleep(100); //XGpio_InterruptGlobalEnable(&Gpio); usleep(100); return stat; } DOES WORK: int Init_Interrupt(void) { . . . . XGpio_InterruptEnable(&Gpio, 0xf); usleep(100); XGpio_InterruptGlobalEnable(&Gpio); usleep(100); return stat; } (B) The "XGpio_InterruptClear(&Gpio, 0x0)" parameters need to be changed: DOESN"T WORK: void InterruptHandler(void *CallbackRef) { xil_printf("Received the Interrupt\n\r"); XGpio_InterruptClear(&Gpio, 0x0); XIntc_Acknowledge(&Intc, XPAR_MICROBLAZE_0_AXI_INTC_AXI_GPIO_0_IP2INTC_IRPT_INTR); } DOES WORK: void InterruptHandler(void *CallbackRef) { xil_printf("Received the Interrupt\n\r"); XGpio_InterruptClear(&Gpio, 0xF); XIntc_Acknowledge(&Intc, XPAR_MICROBLAZE_0_AXI_INTC_AXI_GPIO_0_IP2INTC_IRPT_INTR); } Not sure what was intended with the 0xF. As they are, the interrupt will be enabled for the Switches and the Buttons. To only monitor the buttons use 0x2. Also the main() program seems to be reporting Switch status, but is labeling it as Buttons.
  11. Hi artvvb, Great clues and example! I just ordered at Nexys A7 ECE from Amazon, with delivery on Friday. I will get the "Nexys-A7-100T-DMA-Audio Demo" on that board and then adapt from there. Thanks, Dave
  12. Dear Reader, I need to move data from FPGA memory to DDR memory. For other projects I have: > DDR working with MicroBlaze, thanks for the help - (https://forum.digilentinc.com/topic/17948-place-30-172-sub-optimal-placement-for-a-clock-capable-io-pin-and-pll-pair/) > Memory IP's (dualport and fifo) working from FPGA to AXI_GPIO to MicroBlaze For a new project I need the copy from FPGA memory to DDR memory to be fast (48MB/sec). I think: (a) FPGA direct to DDR may work better, but from other posts it is difficult to setup and tune? (b) If "DMA from IP memory to DDR memory" is possible: - Might it be fast enough? - Are there any example or clues? Thanks, Dave
  13. Is there an example project that interacts with the Arty A7 DDR memory directly from VHDL? I have a potential image processing project that needs 16MB of memory accessible from processing in VHDL. The incoming image rate exceeds 60MB/sec; this presents numerous challenges - a place to store intermediate images is the current concern. Although I have DDR working with MicroBlaze, the processing rate exceeds accessing the DDR through MicroBlaze. If not for the ARTY A7, I would consider shifting the project to the ZYBO Z7 or some other XILINX board, including one with sufficient SRAM. Thanks, Dave
  14. Hi Jon, File is attached and at this location in project: > Arty_A7_100\Arty_A7_100.srcs\sources_1\bd\design_1\ip\design_1_mig_7series_0_0\design_1_mig_7series_ 0_0\mig.prj It is v4.2, the v4.2c was a typo. Dave mig.prj
  15. Hi Jon, Thanks again for the example and screen shots. I haven't resolved the v4.2 vs v2.3 in mig.prj, but was able to create a usable design with E.0 board files and the information you sent: > Configure clk_wiz: - Two outputs (clk_out1 and clk_out2) - 166.667 and 200.000 MHz frequencies - Invert reset to active low (need to scroll down on that config page) > Drive mig_7series with the clk_wiz clocks (had to delete clocks Vivado added) > Configure MicroBlaze to use 83MHz clock from mig_7series Thanks, Dave