aadgl

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  1. Hi JColvin, Yes, the first link worked very well !!! Thanks, Dave
  2. Hello, I am trying to implement DDR2 with Microblaze on a Nexys A7 100T board. I have found several resources, but none are clear examples: > https://github.com/Digilent/Nexys-A7-100T-OOB/releases - has DDR2, but not in a Microblaze project > nexys4ddr_mig_prj.zip - is a good start, but doesn't work in Vivado 2018.2 - the files can be loaded, MIG doesn't enable the [Next] button > https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-4-ddr-sram-to-ddr-component/start?_ga=2.10507316.1851975201.1591529487-1868089371.1591529487 - Documentation reports the components can be inserted as precompiled or source. - I haven't found a a way to do either in Vivado 2018.2 I can get Microblaze with Hello World running. A procedure for the A7-100T board and some version of Vivado would be appreciated. Thanks, Dave
  3. Follow-up. The project works well in Vivado 2019.1 for HDMI Output. I don't need HDMI Input, but decided to test anyway. The v2019.1 does not appear to work for HDMI Input. Oh well, a good project to work from, thanks.
  4. Hi Ana-Maria, I agree the Critical Warning doesn't affect the project, - pops-up a window that needs to be cleared, explained to others, etc - easier to edit the IP and avoid the pop-up. Your question: > Point the IP to the vivado_library folder Reword - Point the project IP folder to the Demo project vivado_library folder When rebuilding the project from "design_1_bd.tcl", it needs IP from this Demo project folder: (a) <demo folder>\vivado_proj\Zybo-Z7-20-HDMI.ipdefs\repo_0\vivado-library Copy that "vivado-library" folder to a location for the new project (b) Point the new project to that IP folder, from Vivado: Tools - Settings - IP - Repository, then click "+" to select IP Repo folder location Then browse to the "vivado-library" folder from (a) The project can then be recreated from the .tcl file. When built, everything builds and runs as expected. Then other VHDL modules can be added to the recreated project, the led's work, etc. I have significant other IP now working with the recreated project, runs in FreeRTOS, etc. Thanks, Dave
  5. Hi Ana-Maria, Thanks for the reply and instructions on seeing more of Vivado's internal files. I do see the three lines and I run Validate frequently. Elsewhere I saw vague mention of the reset and generate steps, thanks for the detailed description of where to find them. I did the reset, generate, and regenerate steps - same result, must be something else sideways in my setup. Yesterday I found a work-around that appears to work (more details if anyone is interested): > Extract the design_1_bd.tcl file and vivado-library folder from the project > Create a new project > Point the IP to the vivado_library folder > Run the .TCL file That recreated the project in such a way that I can add VHDL modules to it. When I can, I will take another pass at correcting the Vivado Bug from a fresh install. Also this Critical Warning keeps appearing: > [IP_Flow 19-4965] IP ila_pixclk was packaged with board value 'digilentinc.com:nexys_video:part0:1.1'. Current project's board value is 'digilentinc.com:zybo-z7-20:part0:1.0'. Please update the project settings to match the packaged IP. I am thinking the Zybo project has a Nexys IP module, to avoid the (likely) extraneous warning I renamed the Nexys board value. Thanks again for your help, Dave
  6. Hello, I am using this project: > Zybo Z7-20 HDMI Input/Output Demo Vivado 2018.2 It installs and runs nicely from the SDK per the documentation. I have only tested the HDMI output function. I am trying to add a VHDL module to the Block Diagram, something I have done on other Vivado projects. I added the VHDL module to sources, enabled the btn, led5, led6, I/O in constraint .xdc, etc, and then added the VHDL module to the Block Diagram. Vivado built the .bit file, transferred it to the SDK, uploaded .bit, and ran C code as usual. I have used the same VHDL module in other Vivado projects and has always dropped in the Block Diagram and worked. The VHDL module should flash led5_g, but nothing happens. The Vivado messages indicate the the btn, led5, and led6 are not being used - yet they appear on the block diagram as being connected to the VHDL module. Vivado did detect the VHDL module in the block diagram and automoation connected it to the correct PS7 clock. Although the VHDL module appears to be part of the block diagram it doesn't appear to be incorporated into the .bit file. Question - How can I integrate a VHDL module into the above demo project? Thanks, Dave Added later - Below is a screenshot showing the original project with an added VHDL Module (two buttons and two leds): (a) Simple module that has two buttons drive two leds (attached_ (b) Same module in block diagram with I/O ports (c) .XDC file with I/O ports enabled (attached) (d) Vivado reporting I/O ports not used The same module, similarly embedded in a block diagram, runs as expected in a standalone Vivado 2018.2 project. Zybo-Z7-Master.xdc btnled.vhd
  7. lonel - Thanks for your response. I can work-around this for now, but will eventually need the cifs' module.
  8. Thanks, I tried that, didn't fix the problem, but did lead me here: > https://askubuntu.com/questions/946132/error-mounting-samba-network-drive-wrong-fs-type-bad-option For Intel Ubuntu Desktop18.04, I followed those instructions: $ sudo apt-get install nfs-common $ sudo apt install cifs-utils Then this command worked (after creating /mnt/drivem): $ mount //192.168.1.100/drivem /mnt/drivem -o user=beagles,rw,gid=1000,uid=1000 I did the same on a fresh PYNQ 2.5, and got the same errors as above: > mount error: cifs filesystem not supported by the system > mount error(19): No such device > Refer to the mount.cifs(8) manual page (e.g. man mount.cifs) That led me to here: > https://askubuntu.com/questions/1115171/mount-cifs-gives-me-mount-error-cifs-filesystem-not-supported-by-the-system And trying: $ modprobe cifs Then yields: > modprobe: FATAL: Module cifs not found in directory /lib/modules/4.19.0-xilinx-v2019.1 It "appears", the Xilinx build doesn't include cifs? Dave
  9. I need to access a Windows share from a PYNQ Z1. I can access PYNQ from Windows, but not Windows from PYNQ. This is the script that I have used on Ubuntu 16.04 and 18.04 boxes: $ sudo mkdir -p /mnt/drivem $ sudo mount //192.168.1.100/drivem /mnt/drivem -o user=username,rw,gid=1000,uid=1000 It asked for the Windows password, then returned this message: > mount error: cifs filesystem not supported by the system > mount error(19): No such device > Refer to the mount.cifs(8) manual page (e.g. man mount.cifs) I have tried this on PYNQ 2.1 and 2.5 with Window 8.1 and Windows 10 computers. Also various parameters on the mount command line, including -t cifs, other type of slashes, single quotes … Same results. I also tried this: $ sudo apt install -y cifs-utils It ran, installed files, but didn’t change the resulting error messages. Any clues would be appreciated, in particular will this work from PYNQ? Thanks, Dave
  10. I had the same problem, bought: - Programmable Logic IC Development Tools PYNQ-Z1+ Accessory Kit Board, cables, etc were fine - the included SD Card wouldn't boot !!! Downloaded Glasgow Release, PYNQ-Z1 V2.5 SDCard image: - Jupyter 1.13, Vivado and Petalinux 2019.1, Ubuntu 18.04 Link is here, requires Xilinx login: > https://github.com/Xilinx/PYNQ/releases Board worked right away with this image. - Dave
  11. aadgl

    Vitas tutorial

    SHORT STORY FOR HELLO WORLD ON ARTY A7: (a) Install Vitis 2019.2 (includes Vivado) (b) Connect FPGA board via USB and open terminal emulator at 9600 baud (c) Vivado is used to create the HDL, BD, etc parts of project (d) Vitis replaces the SDK VIVADO (1) Create BD as usual with these adds: > MicroBlaze, from IP > sys_clock, from board > reset, from board > usb_uart, from board (2) Fix "reset": Invert resetn in clk_wiz_0, Output Clocks, Active Low, then reconnect (3) ... Create HDL Wrapper then Generate Bitstream (4) File > Export > Export Hardware, with "[x] Include Bitstream" Note this generates .XSA, needed in step (9) (5) Tools > Launch Vitis VITIS (6) Select Workspace for Vitis, [Launch] (7) Create Application Project (8) Enter a Project name "name", [Next], needed in step (14) (9) Select "Create a new platform from hardware (XSA)" tab Click the blue plus sign Select the .XSA file from step (4), [Open], [Next] (10) Domain, [Next] (11) Template, Hello World, [Finish] (12) Right click on "name" from (8) in Vitis Explorer Select "Build Project" (13) Xilinx > Program FPGA (14) Right click on "name" from (8) in Explorer Select "Run As" > "Launch on Hardware ..." (15) "Hello World" should print to terminal emulator Vitis.pdf Vivado.pdf
  12. Worked immediately with 2019.2 versions of Vivado and Vitis
  13. I am having the same problem with Cora Z7-07S (xc7z007sclg400-1) in Vivado 2019.1. (a) Create and Test an application that loops through "Hello World" (b) In same SDK project, Create FSBL Application (c) Create Boot Image for the "Hello World" application (d) Format 16GB SD Card Fat 32 with Default Allocation Size (e) Copy BOOT.bin to SD Card, then eject Card (f) Power down Cora (g) Install JP2 to short both pins (h) Insert SD Card and power-up Cora (i) Connect Putty to Cora's COM port (same that worked in (a)) (j) Wait, watch, press SRST button, no traffic from Cora to Putty, no flicker to Cora Com LED, etc I tried the BOOT.bin in the project for the other Cora FPGA, by jpeyron, above, 8/31/2018. Same results. I have tried several other SD Card, one works with another Zynq board. Any clues, other settings, would be appreciated. Thanks, Dave
  14. Hi OvidiuD, Yes, that works very well, thanks. Dave
  15. Ok, got it, will try and report back, thanks.