flying

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  1. Hi, as I mentioned in the previous post as the Zybo-z7-20-base linux was not referenced by the Petalinux project build, so I sourced the hardware description: petalinux-config --get-hw-description=<PATH-TO-HDF-DIRECTORY> I did as well the petalinux-config and selected SD card instead of initramfs . The outcome is that there is some activity of the board afterwards the sd with boot.bin and image.ub are copied on the card and fed into the Zybo: the LED Green is blinking I tried connected to the serial terminal with screen , but no establishing of the communication is done. With dmesg -w , the Zybo device seems restarting and the peripherals listed by the dmesg are ftdi and /dev/ttyUSB0 , and it seems disconnected and the serial is enumerated afterwards on the /dev/ttyUSB1 and this restarting of the Zybo board is like continous after 5 or 10 seconds. Also the HDMI synk to the display is without effect and I can not see the "desktop" of the Petalinux. I had a post here: that only the pipeline_mode_change(vdma_driver, cam, vid, Resolution::R640_480_60_NN,OV5640_cfg::mode_t::MODE_720P_1280_720_60fps); worked when debugged on ARM the https://github.com/Digilent/Zybo-Z7-20-pcam-5c project . I would be interested if something similar - a setting of the HDMI -dvi2rgb or other display driver could be done when initializing the Programming System - ARM : something like the following snippet set video resolution (Resolution::R640_480_60) into this https://github.com/Digilent/Petalinux-Zybo-Z7-20/blob/master/Zybo-Z7-20/project-spec/hw-description/ps7_init.c file ?? Thanks and regards!
  2. Hi @JColvin, Thanks for your reply. I am trying Petalinux with Zybo-Z10 and PCam 5C. I tried reproducing the setup from here and listed my blockings if you could help. Thanks and regards!
  3. Hi, I have a Zybo Zynq-Z7-10 board with PMOD PCam-5C I tried the steps in the replies: https://forum.digilentinc.com/topic/17074-pcam-elf-on-petalinux-from-sd-card/?do=findComment&comment=42504 https://forum.digilentinc.com/topic/17074-pcam-elf-on-petalinux-from-sd-card/?do=findComment&comment=42698 I setup as well a microSD card 8G using gParted: first partition 1GB type fat16 and the second partition 6.80GB type ext4. After inserting the card in Zybo's slot and switching the jumper to SD , the effect of switching on is that the board lights on the LED red LD13 PGOOD, the connected HDMI Monitor has not signal. I have some questions: which resolution has the HDMI output in Petalinux? The bitstream file of Z7-20 Vivado project with the modifications of the diagram and PWM https://github.com/Digilent/Zybo-Z7-20-base-linux - how does it get inserted in the Petalinux binaries that get on the SD card? I guess using this command --- petalinux-package --boot --force --fsbl images/linux/zynq_fsbl.elf --fpga images/linux/system_wrapper.bit --u-boot ---- but there is no interdependency set in the previous posts. Should the project run and the HDMI display connected to the output of the Zynq must run even without the bitstream ? The microsd card was formated with gParted, is compulsory using of a dedicated tool to write the rootfs, boot.bin files ? or the commands: cp BOOT.BIN image.ub /dev/sdd1/ is enough ? https://github.com/Digilent/Petalinux-Zybo-Z7-20?_ga=2.177147622.2104787184.1555966017-216103582.1546520870#configure-sd-rootfs sudo umount /dev/sdd2 sudo dd if=images/linux/rootfs.ext4 of=/dev/sdd2 sync sudo resize2fs /dev/sdd2 sync should be enough?
  4. Hi Bogdan Vanca , Thanks a lot for your answer. Indeed , the archived project was successfully built. I still have one question: The HDMI sink - my screen does not synchronize unless I select the resolution: VGA pipeline_mode_change(vdma_driver, cam, vid, Resolution::R640_480_60_NN,OV5640_cfg::mode_t::MODE_720P_1280_720_60fps); I tried on another one and the resolution 720p pipeline_mode_change(vdma_driver, cam, vid, Resolution::R1280_720_60_PP,OV5640_cfg::mode_t::MODE_720P_1280_720_60fps); However the 1080p does not work: pipeline_mode_change(vdma_driver, cam, vid, Resolution::R1920_1080_60_PP, OV5640_cfg::mode_t::MODE_1080P_1920_1080_30fps); --- problematic. Is this related to the timing issues of the design? The screen was successfully set as a computer monitor on 1080p . How can I get rid of these timing issues? route_design Complete, Failed Timing! WNS -2.421; TNS -4.796 WHS -1.07; THS -2.098 Thanks and best regards !
  5. Hi, FinallyI succeeded exporting the HW to SDK by repeating the steps with Zybo Pcam repo and the dependency towards vivado library and took an appropriate commit (as posted in this comment But now to Program the FPGA , I have difficulties in executing the following sequence mentioned above: 5. Left click on the pcam_vdma_hdmi project. From the top icons, select Program FPGA. Then, from the top menu, select Run -> Run -> Launch on Hardware (System Debugger). Please see the screenshot attached - I do not have Run -> Run ... And another question: how should be the configuration of JP5 ? QSPI or JTAG ? When in JTAG I have only a red led LD13 PGOOD, and when configuration is QSPI I have PGOOD LD13 on, DONE LD12 on LD6 changing color, and also LD0,LD1,LD2,LD3 flickering and LD4 pulsing. Subsequently my interest would be to read the stream captured on the PL into the PS and apply some video processing onto it and output the processed video stream via HDMI. Could you point me to some data processing using Open CV - is there a guideline of how to achieve this frame streaming from PL into PS and installing OpenCV into PS? Thanks in advance, Best regards
  6. Hi Bogdan Vanca , You can find the code here: https://github.com/flyinggiorno/Zybo-Z7-20-pcam-5c-26oct Best regards, F
  7. Hi Bogdan Vanca, Thanks for the quick answer. Exporting is blocked with the exception: [Vivado 12-4452] The hardware handoff file (.sysdef) does not exist. It may not have been generated due to: 1. A bitstream might not have been generated. Generate Bitstream and export again, or do not request a bitstream to be included in export. 2. There are no block design hardware handoff files. Check the vivado log messages for more details It sems I still have some errors that are stoppers as the model is not successfully synthesized. After Reporting and upgrading again the IPs and there are still problems with MIPI_CSI_2_RX_0_0 and DVIClocking. [Synth 8-439] module 'system_MIPI_CSI_2_RX_0_0' not found [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details [Synth 8-2396] near character '0' ; 3 visible types match here ["C:/Users/admin/repo/Zybo-Z7-20-pcam-5c-26oct/src/hdl/DVIClocking.vhd":69] SyncLockedOut: entity work.RestBridge <--------Error: cannot find <restbridge> in library <xil_defaultlib>. Please ensure that the library was compiled and that a library and a use clause are present in the VHDL file. generic map ( kPolarity => '0') Firstly the report IP did not find the DviClocking and DviClocking.vhd was empty. And MIPI_CSI_2_RX was downloaded from here https://github.com/Digilent/vivado-library/tree/feature/d-phy and extracted under %project/repo\vivado-library Best regards,F
  8. Hi, After reading that PCAM 5C is supported in Zybo Z7-20 I was wondering if this is possible with Zybo Z7-10 ? I saw the repository https://github.com/Digilent/Petalinux-Zybo-Z7-20 has some commits regarding PCAM 5C while https://github.com/Digilent/Petalinux-Zybo-Z7-10 is poorer. Which device driver does Petalinux Z7-20 uses for opening and reading from camera ? is there some DPHY MIPI CSI/DSI IP in FPGA fabric or a software stack decoding MIPI signals? How would be the approach to enable PCAM 5C streaming in Petalinux Zybo Z7-10? Best regards
  9. Hi, I am trying the same setup: Zybo Z7-10 and downloaded almost the same code that @malkauns did https://github.com/Digilent/Zybo-Z7-20-pcam-5c/tree/482b7c3ebb66bc3c04706f9e5ccda8edd933bc04 dated Oct 26, 2018. Did also the same steps described here: After upgrading the IPs I get these messages Critical warnings: [PSU-1] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.073 . PS DDR interfaces might fail when entering negative DQS skew values. [PSU-2] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.034 . PS DDR interfaces might fail when entering negative DQS skew values. [PSU-3] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.03 . PS DDR interfaces might fail when entering negative DQS skew values. [PSU-4] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.082 . PS DDR interfaces might fail when entering negative DQS skew values. [Designutils 20-1280] Could not find module 'ila_sfen_rxclk'. The XDC file c:/Users/admin/repo/Zybo-Z7-20-pcam-5c-26oct/src/bd/system/ip/system_MIPI_D_PHY_RX_0_0/hdl/ila_sfen_rxclk/ila_v6_2/constraints/ila.xdc will not be read for any cell of this module. [Common 17-55] 'set_property' expects at least one object. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. [Vivado 12-4452] The hardware handoff file (.sysdef) does not exist. It may not have been generated due to: 1. A bitstream might not have been generated. Generate Bitstream and export again, or do not request a bitstream to be included in export. 2. There are no block design hardware handoff files. Check the vivado log messages for more details. Do you have some advice to counteract these issues? regards, Fino