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  1. actually - the closer I examine the waveform panel there are problems manifesting themselves even before A=0xB0 and B=0x00. It's definitely still not right and the 2 changes you've suggested don't fix the problem. Take a look at the attached waveform. I have it starting at 89,919,000 ns. If you follow along with the A, B and CIN inputs...you'll see problems even here....WAY before the problems I identified at A=0xB0 and B=0x00 Still scratching my head!
  2. yes, that is the change I was referring to; xor'ing the 2nd instantiation of the 4 bit adder/subtractor. However, to be sure I wasn't missing ANY of your changes I pasted your entire version into the design. Once I realized you had "IfDef"s surrounding your necessary changes I realized they'd do no harm in the Verilog design. However I DID have to comment out this line; `default_nettype none So I ran it again and perused the wave form panel in detail. Strangely enough the design works all the way thru a[7:0]=0xB) and b[7:0] = 0x0. Beyond that point...the addition's are correct but the subtractions are incorrect. CLOSE...but no cigar. This has been what I've been doing for the past 2 days...trying zillion's of 'ideas'/iterations to resolve the issue but I just can't seem to find one. Your solution definitely is the closest the design has come to fully working. See the attached Waveform to see the 'breakdown' point.
  3. Xor'ing the 2nd instantiation of the 4bit Adder/Subtractor does not resolve the problem. The 2nd change you suggested is a 'non change'. assign cout = cin ^ carry[4] is 100% identical to assign cout = op ^ carry[4] op is assigned the value of CIN at the onset. Neither op nor CIN are changed so the equations are equivalent. I'm assuming all the other changes in the code are necessary for you to run it thru your SymbiYosys software and are not pertinent to the actual circuit...so I did not add them in. Thanks anyhow...appreciate the effort!
  4. This is a 4 bit ripple add/subtract carry circuit. CIN = 0 for addition (the B inputs don't get inverted and the CIN value of 0 adds nothing to the circuit's final value) CIN = 1 for subtraction ( the B inputs get inverted, 1's complement, and the CIN value of 1 makes it 2's complement) From there each COUT is then wired up to the CIN of the next 1bit full adder. As I said in my original post...the 4 bit ripple carry adder/subtractor circuit is working fine. It's when I instantiate 2 of them, in the 8 bit adder/subtractor, that I'm running into my problem. If I build an 8 bit adder/subtractor out of 8 instantiated 1 bit full adders...that ALSO works fine.
  5. Attached is a screen shot showing the waveform output centered at your question; You'll see that the a[7:0] input value is 0 and the b[7:0] input value is E. When CIN = 0 (addition) s7[7:0] = E (0x0 + 0xe = 0xe) --> correct When CIN =1 (subtraction) s7[7:0] is showing 0x02 when it SHOULD be showing 0xF2 0000 0000 0x0 - 0000 1110 0xe ========== 1111 0010 0xf2 (f2 = -14)
  6. I'm designing and simulating/testing with Vivado 2018.3. The attached files are: 1. Waveform output: I have the output starting at a[7:0] input = A0. You can see the B[7:0] input increasing from 0 to 1 to 2 to 3.....etc. You can further see the CIN value changing from 0 to 1 for each of the A and B input values. When CIN = 0 (addition) the result s[7:0] is correct. For all values of A[7:0] and B[7:0]. When CIN =1 (subtraction) the results are simply dead wrong. 2. TCL console output: I have this printed output starting at a[7:0] input = A0 so you can match the various values up to the waveform output. The columns of data in the TCL output are: [TIME] [A Input]. [B Input]. [S output]. [COUT output]. [CIN input]. As you can see...when the circuit is in subtraction mode...something is going awry....and THIS is what I've been trying to resolve. Thanks for your input/guidance!
  7. When I run it thru a simulation OR actually load it onto a Basys3 board...its NOT working. Not sure how you were able to "prove" that it is working. I have physical evidence to the contrary. Thanks though!
  8. To All: I've been having trouble with this 8 bit adder/subtractor. It's "built up" from a 1 bit full adder, then a 4 bit adder/subtractor and then, finally, into a full 8 bit adder/subtracter. The 1 bit full adder works perfectly. The 4 bit adder/subtracter, built up from the 1 bit full adder, works perfectly. The final, 8 bit adder/subtractor, is where my problem lies and I have beat my head against the wall until the dents are now noticeable (in both my head AND the wall). The 'fix' has GOT to be simple but it sure hasn't popped into my head...and I've tried so many iterations to resolve it I've lost track of what I've done and haven't done! I'm pretty certain the problem lies in how the COUT and CIN values are being passed from the 1st 4 bit adder/subtractor iteration to the 2nd...but danged if I can figure out what I've done wrong! Can ANYBODY tell me what's wrong with the final 8 bit adder/subtractor? PLEASE (and thank-you!) addsub_8bit_cascade4.txt
  9. Hi All; I've created a packaged IP for a 4bit adder (Vivado 2018.3). Mostly an exercise in learning to make sure I know what I'm doing when I start packaging up truly needed IP's. The packaging of the IP from the project went fine, no issues. Using the newly created IP in a new project works fine with an exception; During the implementation run 27 critical errors pop up. Each of these errors point to an uncommented line in the constraint file. However, once the implementation is done I then build the bitstream, program the board (Basys3) and....**POOF** everything is working fine. So the 27 critical errors don't cause a 'show stopper'. I'd like to figure out WHAT is causing these errors so I can resolve the problem and not have this issue propagated thru the IP's I create for use in other projects. See the attached image. Any hints, guidance, suggestions (or answers) would be greatly appreciated. Thanks
  10. Hi All: This forum has been very helpful for me as I slowly come up to speed with Vivado. I now have a new question that I hope somebody can either answer or point me in the right direction; In the attached image I have taken my full_adder RTL module and deployed it within a new project where I am using the IP Integrator. I have successfully implemented a 2 bit adder out of my original 1 bit full_adder. What is depicted in the image, below, is working fine. HERE IS MY PROBLEM: I can't seem to connect up a vector port to the a inputs, the b inputs or the s outputs. The only way I've been able to get it to work properly is to connect up individual (make external) ports on each instantiation of the full_adder. I would prefer using a[1:0], b[1:0] and s[1:0] but I run into 2 problems: 1). when I create a vector port for input a (a[1:0]) and b (b[1:0]) it seems that Vivado is tying both a ports together. Whatever it's doing - when I use vector ports for input a and b the design doesn't work. 2) when I create a vector port for output s (s[1:0]) it will only let me "hook up" one, or the other, of the s ports...but not both. As stated above, the design as shown works...but only because I used individual input/output ports. Doing this manually when I've jumped it up to a 64 bit, 2's complement, adder is going to be problematic if I can't figure out how to use vector ports in the IP integrator. (NOTE: I've already done this, successfully, via pure Verilog code, starting with a 1/2 adder, then including that RTL design in the full adder, then including that RTL design in a 4 bit adder, then including that RTL design in a 16 bit adder...etc., etc., etc.). I'm trying to replicate this in the IP Integrator for "learning" purposes. Thanks for any help/guidance/advice in advance.
  11. "all the bother" = learning experience. I've already been able to create the full adder via Verilog and then instantiated the full adder 8 times in yet another project - to create a full 8 bit adder. That was easy, no problems. Now, as I said, I'm trying to do the same thing via a schematic (block design). If you could give me the URLS to the guides AND tutorials regarding IP and repositories...I'd appreciate that. Thanks.
  12. Hi all. I'm still fairly new to Vivado (2018.3) and having trouble trying to figure something out. I HAVE tried searching the web and forum for an answer but haven't come up with one. My Problem: I've completed a Vivado project for a full adder. It was created with a schematic design (block design?). it works great, my test bench confirms everything and it loaded and executed in my Basys3 board perfectly. So now I'm trying to figure out how to "package" this up and save it as a new schematic symbol. I want to create a cascade of this full adder in another project (as in a 4 bit adder, an 8 bit adder, etc). I can't seem to figure out how to do this. Any help/guidance would be greatly appreciated. P.S. - I KNOW there is already a 14 bit adder/subtractor in the IP library but I'm trying to get to this point on my own without using the pre-built IP. THANKS! 🙂
  13. HI xc6lx45: Well, to my surprise, when I got home and loaded the .BIT file onto the board...it works perfectly. [1:0]sw is changing the frequency the the led is blinking at properly. So this tells me that I don't quite have my testbed code done properly. I tried to attach it into this text but it kept getting reformatted so I've simply attached the actual file. If somebody could look at it and tell me what (if anything) I've done wrong I'd greatly appreciate it. THANKS! NOTE: In the actual module code, above, I had changed the CASE choices to the 0, 1st, 2nd and 3rd flip-flops in order to better see the led changing value on the wave panel. However I've changed the code back to the actual flip-flops I wanted; the 26th, 25th, 24th and 23rd flip-flops. As I said...the board is working perfectly now and the switch setting are appropriately changing the led blinking frequency. It HAS to be something wrong with the TestBench code...or me not using the simulator properly. THANKS MUCH! clock_divider.tb
  14. To All: 1st off...thank-you to everybody that's been so kind to respond and help out. This newbie greatly appreciates the assistance. That being said; I've resolved the main problem(s) and now Vivado properly processes the project. However the simulation is showing me that the frequency that the LED is blinking at is NOT changing based on the switch value [1:-0]sw changing. I've posted both the updated module, below and a screen grab of the simulation. You can see, from the simulation that as the switch value changes (from 3 to 2 to 1 to 0) the LED continues to blink at the same frequency. that's the bad news. The good news is I am WAY further along than I was this morning....especially being able to properly get a simulation going for analysis! I still haven't loaded the .BIN file onto the board...yet I KNOW there is a problem from the simulation! EUREKA! 🙂 Any idea why the led is not properly being assigned the value being determined in the case statements? Thanks again: MODULE: module clk_divider( input clk, input rst, input [1:0] sw, output led ); wire [26:0] din; wire [26:0] clkdiv; reg switched_clkdiv; dff dff_inst ( .clk(clk), .rst(rst), .D(din[0]), .Q(clkdiv[0]) ); genvar i; generate for (i = 1; i < 27; i=i+1) begin : dff_gen_label dff dff_inst ( .clk(clkdiv[i-1]), .rst(rst), .D(din), .Q(clkdiv) ); end endgenerate assign din = ~clkdiv; always @ (*) begin case(sw) 2'b00: switched_clkdiv <= clkdiv[0]; 2'b01: switched_clkdiv <= clkdiv[1]; 2'b10: switched_clkdiv <= clkdiv[2]; 2'b11: switched_clkdiv <= clkdiv[3]; default: switched_clkdiv <= clkdiv[0]; endcase end assign led = switched_clkdiv; endmodule
  15. xc6lx45: Thanks for the response/advise. Can you recommend your opinion of the 'right' textbook for Verilog? I'm all ears (and eyes) at this early juncture...... Thanks