Anusha Kodimela

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Everything posted by Anusha Kodimela

  1. Hi Jon! Is it specific to the board? My question was little different.I have the vhdl source code programmed to a bit file and I would like to automate the process of opening the Xilinx ISE Impact tool upload the bit file using python.I am using a Genesys2 Kintex7 development board.
  2. Hello Team! I wanted to program a bit file using the python program such as using APIs of the genesys2 board.Currently I am using Impact tool to program and Real Term terminal to view the transmitted data through UART. Is it possible to just use a single user interface from python and send commands for programming the file,starting and stopping the counter from the python code (instead of a slide switch of the genesys2 board) please share your thoughts
  3. But Jon, I am expecting the ascii value will be displayed on the terminal(by default) instead of the binary data on the terminal and later we need to decode that ascii code to find the exact data isn't it right?should we assign design a converter in our hdl which takes in binary 8 bit value converts it to ascii hex?
  4. The FIFO generator is the same for ISE and Vivado,its the IP core being used.It is not just specific for ISE. Are there any experts to whom this thread can be assigned for help?
  5. Hi Jon! Do you have anything to suggest regarding the FIFO generator,can I directly send the FIFO output bus data(dout) through USB UART bridge?
  6. Hi Jon! After a count value is generated and written into the FIFO,the value is then being transmitted through the UART bridge.Do you think it is possible to transmit that way as the FIFO gets appended with new value as it gets ?I am thinking this might be the reason for seeing garbage values even after setting the baud correctly (Tx and Rx end).I am using a FIFO with Block Ram with following settings(attached) in the core generator. Let me know if you have an inputs/advice. FIF0_Coregen_Screenshots.docx
  7. Hi Jon,The couter and the FIFO coregen is already been tested verified.The only thing I wanted to test was if my tera term is set at 115200(8,N,1) I wanted to modify the same in my desig as well with baud rate of 115200 and parity signal set to 0 so that the Tx(HDL) and Teraterm(Rx) have the same config.I will keep you posted if there is any update
  8. Hello Jon! I have already referred that article before building my UART controller. I have my count value given to LEDs at the same time reading those values on to the terminal,but for some reason the terminal output shows random charters list!I am unable to decode..As per the atasheet for Genesys 2 Kintex 7 I have set the baud rate as 115200(8,N,1).Attached screenshot below
  9. Hi Jon! I have two questions regarding USB-UART controller in Genesys2 Kintex7 1.If I use a negative reset input reset_n : IN STD_LOGIC:= '1'; in my design and that reset input is given to one of the button on the board would it work because all I know is the buttons are usually of value '0' and would be set to '1' only when they are pressed.In my case how would I configure(user constraints file) them If i need a negative reset? 2.The connections for USB-UART is one micro usb for JTAG(J17) to PC for programming and one micro usb for UART (J15)to PC for communication through tx pin and it requires a Teraterm terminal to view the data that is communicated? NET "tx" LOC="Y23"|IOSTANDARD="LVCMOS33"; --- this is the transmit pin being used NET "reset_n" LOC="M19"|IOSTANDARD="LVCMOS33"; -- this is the reset button Thanks Anusha
  10. I resolved the issue Jon, Its not the reset and locked I just changed the feedback to none in the wizard settings.That solved my issue.
  11. I still need to figure out how to use the reset and lock pins to get the CLKFX pin working. Kindly help if anyone has any info.
  12. Hi Jon! I figured out the issue,please find attached clocking wizard selections.The issue is using the CLKFX output .I changed the output pin of DCM to CLK2X(which is used to only double the input frequency 100Mhz) and my design works fine. But the requirement is to generate 200Mhz clock using the CLKFX pin and google suggests to use rest and locked pins in our design while using CLKFX. coming back to the clock constraints you asked for I am using the system clock 50MHZ which is NET "clk" LOC = "B8"; # Bank = 0, Pin name = IP_L13P_0/GCLK8, Type = GCLK, Sch name = GCLK0 DCM_CoreGen_Parameters_Screenshot.docx
  13. seems like the CLKFX_OUT => clk is not giving the desired output hence the board is not working
  14. I am running with another issue with DCM and created a new thread for it..Could you please have a look
  15. Board:Nexys2 Spartan 3E I have used a DCM Core gen to convert the system clock 50MHz to 200 Mhz and added the component to my design,port mapped signals as below not used locked and rest pins while generating the coregen.. CLKIN_IN => Clock, ----input 50 Mhz clock CLKFX_OUT => clk,---output 200Mhz clock CLKIN_IBUFG_OUT => open, CLK0_OUT => open the clk signal (output from dcm)is being used now in my design instead of Clock(50 Mhz.I am displaying a count value on a seven segment display which has worked before using dcm (for 50 Mhz clock).I have not seen any error or warnings after implementing the DCM .The simulation seems working as expected.But I am not seeing the output which I have to see in the board after programming it. Did I forget implementing any other step?My ucf looks like below and If I insert the first lines of the ucf I am getting a timing constraint waning for dcm constraints file.Kindly help. # Clock #NET "Clock" TNM_NET = "clk_ref"; #TIMESPEC "TS_clk" =PERIOD: "clk_ref": 20ns:PRIORITY 1; #HIGH 50 %; # 50MHz NET "Clock" LOC="B8" | IOSTANDARD="LVCMOS33";#50MHz Clock Input NET "Counter_enable" LOC="L15" | IOSTANDARD="LVCMOS33";#L15-JA1 NET "Counter_disable" LOC="K12" | IOSTANDARD="LVCMOS33";#K12-JA2 NET "Anode_Activate<0>" LOC="F17" | IOSTANDARD="LVCMOS33"; NET "Anode_Activate<1>" LOC="H17" | IOSTANDARD="LVCMOS33"; NET "Anode_Activate<2>" LOC="C18" | IOSTANDARD="LVCMOS33"; NET "Anode_Activate<3>" LOC="F15" | IOSTANDARD="LVCMOS33"; NET "LED_out<6>" LOC="L18" | IOSTANDARD="LVCMOS33"; NET "LED_out<5>" LOC="F18" | IOSTANDARD="LVCMOS33"; NET "LED_out<4>" LOC="D17" | IOSTANDARD="LVCMOS33"; NET "LED_out<3>" LOC="D16" | IOSTANDARD="LVCMOS33"; NET "LED_out<2>" LOC="G14" | IOSTANDARD="LVCMOS33"; NET "LED_out<1>" LOC="J17" | IOSTANDARD="LVCMOS33"; NET "LED_out<0>" LOC="H14" | IOSTANDARD="LVCMOS33";
  16. Hi jon! I have resolved that issue using a case statement to assign the bits instead of using the - operator.Hence I have deleted the post also immediately.where you still able to see it?
  17. Hello Jon! Thank you for giving hope in coding with what ever I am comfortable with.
  18. Hi jeypron! If I had to use my vhdl code in vivado using UART Lite IP core do I still have to use microblaze?I have experience working with IP core when I generated the FIFO Bloc ram and did the port mapping and logic based on the signals used in fifo. Can you guide me with any example which does USB_UART communication not using microblaze as I am not good at creating block design.
  19. Thanks jpeyron! I have already built my vhdl code for generating the 32 bit value and then storing it to block ram FIFO. Hence I would continue using the same for my UART USB bridge as well. But I couldn't find AXI UART Lite v2.0 LogiCORE IP .I am using Xilinx ISE 14.7 DESIGN suite.we have all valid licenses for IP cores.Do you have any idea?
  20. Thankyou jpeyron! Could you also elaborate the process for data transfer to PC using USB-UART? I have not seen any IP cores for establishing data transfer from Genesys2 to PC using USB UART .Is the block RAM fifo IP core generated in my design can be accessed from external world(PC) using the USB-UART bridge? The data sheet for Genesys2 says FTDI FT232R USB-UART bridge (attached to connector J15) that lets you use PC applications to communicate with the board using standard Windows COM port commands. Free USB-COM port drivers, available from Windows Update or www.ftdichip.com under the "Virtual Com Port" or VCP heading,convert USB packets to UART/serial port data. Serial port data is exchanged with the FPGA using a two-wire serial port (TXD/RXD) with no handshake signals. After the drivers are installed, I/O commands can be used from the PC directed to the COM port to produce serial data traffic on the Y20 and Y23 FPGA pins.
  21. Thankyou for the reply jeypron! We weren't looking for any specific number (volume of data and the date rate) but more likely aligned towards using the Ethernet since we would like to do it in faster rate compared to USB rates . My main objective is to access the Data written in the FIFO and grab it to the PC using ethernet which can be a upper level program written in matlab/python to access the data but before I do that how should I set up the Ethernet using the IP crore to allow access from the PC to my block ram FIFO. Could you please let me know from the FPGA end what all needs to be done to set up Ethernet such as which IP core has to be used,IP core settings etc. Also could you let me know for using USB UART do we need IP core? Thanks and Regards Anusha Kodimela
  22. Hello Team! I am using Genesys2 FPGA for building a module with generates 32 bit values which are to be sent to PC for further analysis and computations.right now I am storing those values in async block ram fifo. which interface would be good for my requirement to implement as the board that I am using right now Genesys2 Kintex-7 contains both USB-UART and Ethernet(attaching the data sheet) . could anyone elaborate in brief what steps are to be implemented depending on the interface being used? Thanks and Regards Anusha Kodimela genesys2_rm.pdf