Anusha Kodimela

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  1. Hi Jon! Is it specific to the board? My question was little different.I have the vhdl source code programmed to a bit file and I would like to automate the process of opening the Xilinx ISE Impact tool upload the bit file using python.I am using a Genesys2 Kintex7 development board.
  2. Hello Team! I wanted to program a bit file using the python program such as using APIs of the genesys2 board.Currently I am using Impact tool to program and Real Term terminal to view the transmitted data through UART. Is it possible to just use a single user interface from python and send commands for programming the file,starting and stopping the counter from the python code (instead of a slide switch of the genesys2 board) please share your thoughts
  3. But Jon, I am expecting the ascii value will be displayed on the terminal(by default) instead of the binary data on the terminal and later we need to decode that ascii code to find the exact data isn't it right?should we assign design a converter in our hdl which takes in binary 8 bit value converts it to ascii hex?
  4. The FIFO generator is the same for ISE and Vivado,its the IP core being used.It is not just specific for ISE. Are there any experts to whom this thread can be assigned for help?
  5. Hi Jon! Do you have anything to suggest regarding the FIFO generator,can I directly send the FIFO output bus data(dout) through USB UART bridge?
  6. Hi Jon! After a count value is generated and written into the FIFO,the value is then being transmitted through the UART bridge.Do you think it is possible to transmit that way as the FIFO gets appended with new value as it gets ?I am thinking this might be the reason for seeing garbage values even after setting the baud correctly (Tx and Rx end).I am using a FIFO with Block Ram with following settings(attached) in the core generator. Let me know if you have an inputs/advice. FIF0_Coregen_Screenshots.docx
  7. Hi Jon,The couter and the FIFO coregen is already been tested verified.The only thing I wanted to test was if my tera term is set at 115200(8,N,1) I wanted to modify the same in my desig as well with baud rate of 115200 and parity signal set to 0 so that the Tx(HDL) and Teraterm(Rx) have the same config.I will keep you posted if there is any update
  8. Hello Jon! I have already referred that article before building my UART controller. I have my count value given to LEDs at the same time reading those values on to the terminal,but for some reason the terminal output shows random charters list!I am unable to decode..As per the atasheet for Genesys 2 Kintex 7 I have set the baud rate as 115200(8,N,1).Attached screenshot below
  9. Hi Jon! I have two questions regarding USB-UART controller in Genesys2 Kintex7 1.If I use a negative reset input reset_n : IN STD_LOGIC:= '1'; in my design and that reset input is given to one of the button on the board would it work because all I know is the buttons are usually of value '0' and would be set to '1' only when they are pressed.In my case how would I configure(user constraints file) them If i need a negative reset? 2.The connections for USB-UART is one micro usb for JTAG(J17) to PC for programming and one micro usb for UART (J15)to PC for communication through tx pin and it requires a Teraterm terminal to view the data that is communicated? NET "tx" LOC="Y23"|IOSTANDARD="LVCMOS33"; --- this is the transmit pin being used NET "reset_n" LOC="M19"|IOSTANDARD="LVCMOS33"; -- this is the reset button Thanks Anusha
  10. I resolved the issue Jon, Its not the reset and locked I just changed the feedback to none in the wizard settings.That solved my issue.
  11. I still need to figure out how to use the reset and lock pins to get the CLKFX pin working. Kindly help if anyone has any info.
  12. Hi Jon! I figured out the issue,please find attached clocking wizard selections.The issue is using the CLKFX output .I changed the output pin of DCM to CLK2X(which is used to only double the input frequency 100Mhz) and my design works fine. But the requirement is to generate 200Mhz clock using the CLKFX pin and google suggests to use rest and locked pins in our design while using CLKFX. coming back to the clock constraints you asked for I am using the system clock 50MHZ which is NET "clk" LOC = "B8"; # Bank = 0, Pin name = IP_L13P_0/GCLK8, Type = GCLK, Sch name = GCLK0 DCM_CoreGen_Parameters_Screenshot.docx
  13. seems like the CLKFX_OUT => clk is not giving the desired output hence the board is not working
  14. I could find the above attached error in the design summary report.