Alonso

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  1. Thank you for your answers. Look that, i simulate the "music looper" project which you told me. And i see that the state (nstate) of SRAM to DDR component never change: And the signal calib_complete, always is X. Thank you.
  2. I dont know what happend, but i cant simulate it. Can it be simulate?? or have i to use FPGA? thank you
  3. TOP.vhd Here is my TOP module and the testbench, i think that i am assigning initial values. Thank you. TOP_TB.vhd
  4. Hello. I'm trying to simulate SRAM to DDR component from Nexys 4 DDR, I'm using Vivado 2017.2 and i want to write on DDR. I have respected timming about all entrande signals (RAM) but i never write on DDR, I always see 'ZZZZ' at ddr2_dq signal. Here is a screencapture about simulation. What am i doing wrong? Thank you.