Phil

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  1. @artvvb Arthur, thanks for the detailed reply. This is the information I needed to move forward. My HDL wrapper is Verilog, which threw me off when I got the error messages about VHDL. In the top level settings the target language is set for Verilog. I'm not aware of another setting somewhere that would affect this. From the example you provided, when the IIC port is made external and the HDL wrapper is updated to account for this, I did not realize before that the IOBUF buffers were instantiated and that the _io signals are then made available to make my pin assignment in my .xdc file. This is the information I needed and I can see how the tristate is being handled. I have tested this by assigning pins on different connectors than the ones pre-defined for I2C and PMOD in the board definition files. After adding the pullup constraints it all works fine and I can now use other available I/O pins.
  2. I have the Arty A7-100T and have successfully built and run a project using the PMOD RTCC module, which uses the I2C interface. I modified the project to use the I2C pins on connector J3 of the Arty and enabled the pullup resistors. I wired the SCL & SDA pins to the PMOD RTCC and all is good. It runs the same as if connected to the PMOD connector. So now I am trying to build my project without using the I2C defined port that is in the board definition files. I want to connect directly to the 6 control and data lines that make up the I2C port on the AXI IIC IP and I want to be able to use any of the available I/O pins on the board for SCL & SDA (I realize that I will need external pullup resistors unless the internal pullups available in the FPGA are sufficient). The problem I am having is that I get failures during synthesis that seem to not like me trying to use bi-directional tristate pins for SCL and SDA. I have a Verilog file that I am using for the bi-directional tristate control: module tristate(IO_Data, Tx_Data, Rx_Data, Tri_En); inout IO_Data; // bidirectional data line input Tx_Data; output Rx_Data; input Tri_En; assign IO_Data = Tri_En? 1'bz:Tx_Data; assign Rx_Data = IO_Data; endmodule This is what it looks like wired up: These are the constraints on the 2 pins: set_property PACKAGE_PIN L18 [get_ports scl] set_property IOSTANDARD LVCMOS33 [get_ports scl] set_property PACKAGE_PIN M18 [get_ports sda] set_property IOSTANDARD LVCMOS33 [get_ports sda] This is the type of error I get: [Designutils 20-1595] In entity system_tristate_0_1, connectivity of net IO_Data cannot be represented in VHDL. VHDL lacks syntax to connect the following inout terminals to a differently-named net: inout IO_Data Resolution: Check whether terminals really need inout direction and substitute input or output as needed. It may also be possible to rename the net to match the terminal. My questions are: 1) Should I be able to connect I2C in this manner without having the port defined in a board definition file? 2) If so, any suggestions to correct my design or how to eliminate the errors I'm seeing? 3) Is there a tristate buffer primitive or IP that I should be able to use here (I cannot find one, which is why I attempted to create my own here)? 4) The PMOD RTCC module does not have pullup resistors on SCL & SDA. When using it with the PMOD connector and the board definition files it works. Are the internal FPGA pullup resistors enabled somewhere? I could not find that anywhere in the PMOD definition files or the Arty board definition files.
  3. Phil

    Arty A7 vs Nexys A7

    OK, thanks. I had downloaded from the store page, which links to rev C. The reference page links to rev E
  4. Phil

    Arty A7 vs Nexys A7

    Where can I download the schematic for the specific version of the board I have? On the Arty A7 resource page, the schematic linked is rev C.1. The board version I have is rev E (from the silkscreen on the back side just below the bar code sticker). I noticed that some different parts are used between the two and would like to have the schematic specific to my board, if it is available. Thanks
  5. Phil

    Arty A7 vs Nexys A7

    Thanks @jpeyron for the info. I just received my board and some IO modules so I will be digging through the resources you mentioned
  6. Phil

    Arty A7 vs Nexys A7

    Thanks @JColvin for addressing my questions. This is good info. I will be ordering the Arty A7 -100T. I have a couple of more questions if you don't mind... I want to make sure this board has the JTAG interface built-in, like I think it does from the description of the board features. A while back I had ordered a Zynq kit from Avnet and it did not have JTAG built-in nor included with the kit, nor did it have any mention of needing one on whatever sales documentation we read about it before ordering. We needed the HS2, which the user manual did mention. I will be looking to use the Ethernet port on this board. Is the MAC IP core freely available in Vivado or is this a licensed IP? I will eventually need a 10/100/1000 speed MAC to go with my custom board design, if this is supported. I understand that the Arty A7 has a 10/100 PHY. Thanks
  7. Phil

    Arty A7 vs Nexys A7

    I have been looking at the Arty A7 and Nexys A7 boards and am confused about the FPGA part numbers listed for them. The Arty A7 specifies the XC7A100TCSG324-1 part number. The Nexys A7 specifies the XC7A100T-1CSG324C part number. The numbers appear to be very similar, but there must be some difference in the two parts. I have been unsuccessful finding anything that breaks down the part number for the Arty. The Xilinx document "XA Artix-7 FPGAs Data Sheet: Overview" has the breakdown in ordering information for the part Nexys part number. Are these in fact identical parts? The Nexyx A7 board appears to be a re-spin of an earlier design. When did this board come available? What about the Arty A7 board, is it a more recent design? I have searched the forum posts and did not find anything addressing this, so I decided to post my questions. Thanks