ulvarg

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ulvarg last won the day on November 21 2014

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About ulvarg

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  1. You should see the following lines somewhere in your XDC file: ## Clock signal #set_property PACKAGE_PIN W5 [get_ports clk] #set_property IOSTANDARD LVCMOS33 [get_ports clk] #create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk] Just take out the hashtags (#) in order to enable the clock pin.
  2. I just want to make sure that this happens when you try to open the project and not when you synthesize and then try to implement it. If that's not the case, did you include the XDC Constraints file in your project? It looks to me that you forgot to add the file to your project. Also, I don't know if you're running Vivado on Windows 8 or above. Vivado is currently having compatibility issues with Windows 8 and 8.1.
  3. ulvarg

    Bays3 Programming Issue

    Thank you for your answer, duskwuff. I talked to one of my professors at school, and he told me the same as you a couple of days after I made this post. I hope this answer may be of use to others as well.
  4. Digilent's webmaster is the right person to talk to. If you can't reach him easily, why not use ImageShack links in the meantime? Uploaded pictures are lightweight and have a decent resolution.
  5. And if you want to learn more about VHDL, you can visit Hamster's website. He has lots of interesting content there. http://hamsterworks.co.nz/mediawiki/index.php/Main_Page
  6. Apparently you have no previous experience coding in an HDL. It would be easier for you to create a VHDL test bench. I'm currently learning VHDL from some external websites since I could not follow the Verilog tutorials made by Digilent; the explanations related to the code are just poor. If you so want, you can follow this easy-to-understand VHDL tutorial on test benching.
  7. ulvarg

    Bays3 Programming Issue

    I apologize for the spam threads; my Internet connection is not working properly.
  8. ulvarg

    Bays3 Programming Issue

    Hi, Ever since I programmed my Basys3 board via JTAG for the first time, I noticed that the 7-segment displays would stay slightly on despite not using them in my projects. Is this type of behavior to be expected? If not, does anyone know how to overcome this issue? Thank you.
  9. I already figured out what my error was. If anyone else finds himself/herself in a situation where the bitstream file gives the errors I listed above, just enable the clock pins on the Basys 3 XDC file.
  10. Hi, I recently acquired a Basys 3 board and am currently trying to run the abacus demo on the board with a .bin file. I have been able to synthesize and implement all of the verilog files and followed all of the steps given in the demonstration video to run the project on the board , but I have not been able to generate the bitstream file. I attached a report file just in case someone wants to take a look at it. EDIT: I have found three errors but do not know what they mean. [Drc 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 1 out of 50 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: clk. [Drc 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 1 out of 50 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: clk. [Vivado 12-1345] Error(s) found during DRC. Bitgen not run. bitstream_report.txt
  11. The $10 license is device-locked, meaning that you can only run it on a single FPGA architecture as well as on one single computer at a time. When you generate a license file on the Xilinx website, you're prompted to select a device ID for your machine, e.g., a hard drive or a mac address, which means that unless you return the license to Xilinx via the License Manager, you won't be able to run Vivado with such a license on other machines.
  12. Hi all, I recently acquired a Basys3 board and read that it was designed to work exclusively with Vivado. I want to do some projects using Labview and have found that other boards, such as the Basys2 and the Nexys series are compatible with it and documentation is provided as to how to interface the boards with LV. I am just wondering if it is also possible to interface the Basys3 board with Labview. Thank you
  13. Hi all, I am a newbie into the world of FPGAs and HDLs. I am currently taking a logic design course where I am required to present a project by the end of this year. I would like to buy either a Basys3 or a Nexys4 board, but I am unsure as to how I could interface any of these boards with other external components, such as sound sensors, servos, (another development board perhaps?), and so on. Please, try not to consider Pmods, as they are somewhat expensive to my budget for now. Your help is greatly appreciated.