Ana-Maria Balas

Digilent Staff
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  1. Like
    Ana-Maria Balas got a reaction from Luke Abela in Nexys 4 DDR Ethernet Tutorial - Tera Term   
    I reproduced the problem somehow. You need to make sure that you follow the exact steps as they are described in the tutorial:
    1. Connect your PC to your Nexys 4 DDR using an Ethernet cable.
    2. Make sure you set the static TCP/IPv4 address "192.168.1.XX” for your PC, where XX is a value between 2 and 255, but not 10.
    This is important because the board and the PC has to be in the same network , so that's why you set "192.168.1" which is the Network Identifier. The XX is the Host Identifier.
    Below is a screenshot of the connection through serial port and what it displays when you run the application.

    3. Connect to Tera Term using the board IP : 192.168.1.10.
    You need to open a new connection and set 192.168.1.10, Telnet, TCP port 7.
    Cheers,
    Ana-Maria
  2. Like
    Ana-Maria Balas got a reaction from Mounir in Object Detection System Requirements   
    I think that you could use Zybo Z7 with Pcam 5C and Pmod WiFi.
    Here are some useful projects which you can modify them and adapt them to your needs :
    Zybo Z7 -20 Pcam 5C Demo :  https://github.com/Digilent/Zybo-Z7-20-pcam-5c
    Pmod Wi-FI IP and some exemples : https://github.com/Digilent/vivado-library/tree/master/ip/Pmods/PmodWIFI_v1_0
     
  3. Like
    Ana-Maria Balas got a reaction from Bryan_S in Old Spartan 3 UART code to Digilent CMOD S6 not working   
    I'm glad you worked it out!
    Best regards,
    Ana-Maria
     
  4. Like
    Ana-Maria Balas got a reaction from Bryan_S in Old Spartan 3 UART code to Digilent CMOD S6 not working   
    Hi @Bryan_S,
    We don't have the necessary resources to investigate/correct the code of your project.
    However the source code I provided to you above, is readable and you can test it with your project. Just integrate the clk_gen_50MHz.vhd and UART_RX_CTRL.vhd files to your project. I think those files are all you need.
    Cheers,
    Ana-Maria
  5. Like
    Ana-Maria Balas got a reaction from Irfan in ZYNQ UART Issue   
    Hello @Irfan,
    Which board are you using ? Also could you post a screenshot of your block design ?
    Cheers,
    Ana-Maria
  6. Like
    Ana-Maria Balas got a reaction from Bryan_S in Old Spartan 3 UART code to Digilent CMOD S6 not working   
    Hello @Bryan_S,
    Here is a demo project for Cmod S6 from https://reference.digilentinc.com/reference/programmable-logic/cmod-s6/start.
    I looked into the source files and there is clk_gen_50MHz.vhd.
    You can see in the top.vhd file how the clk_gen_50MHz is instantiated and used.
    I don't know what is the clk16x in your code, but here are some source files for serial port serialport_v3.zip The sources are for Nexys4 DDR which has a 100 MHz system clock.
    But in your case, if you use the clk_gen_50MHz, you'll have a 50 MHz clock instead of 100 MHz, 9600 baud rate, as shown in the UART_RX_CTRL.vhd file. The same for UART_TX_CTRL.vhd.
    I don't know if you'll use the sources from above, but I hope it helps.
    Best regards,
    Ana-Maria Balas
     
  7. Like
    Ana-Maria Balas got a reaction from Cristian.Fatu in Old Spartan 3 UART code to Digilent CMOD S6 not working   
    Hello @Bryan_S,
    Here is a demo project for Cmod S6 from https://reference.digilentinc.com/reference/programmable-logic/cmod-s6/start.
    I looked into the source files and there is clk_gen_50MHz.vhd.
    You can see in the top.vhd file how the clk_gen_50MHz is instantiated and used.
    I don't know what is the clk16x in your code, but here are some source files for serial port serialport_v3.zip The sources are for Nexys4 DDR which has a 100 MHz system clock.
    But in your case, if you use the clk_gen_50MHz, you'll have a 50 MHz clock instead of 100 MHz, 9600 baud rate, as shown in the UART_RX_CTRL.vhd file. The same for UART_TX_CTRL.vhd.
    I don't know if you'll use the sources from above, but I hope it helps.
    Best regards,
    Ana-Maria Balas
     
  8. Like
    Ana-Maria Balas got a reaction from Cristian.Fatu in PmodKYPD and PmodOLED for Zynq   
    Hello @justeen,
    I see that you used the Pmod IP's from the vivado-library. Each IP you added to your block design comes with a demo. In the vivado-library folder, corresponding to your Pmod IP,  you will find the example sources.
    Here are the demo sources for Pmod Oled and here are the demo sources for Pmod KYPD. You can look into the example sources for both of the Pmods and adapt them to your project.
    At step 11. Create a New Application Project in SDK from the tutorial explains how to create a project in SDK when using Digilent Pmod IPs.
    Cheers,
    Ana-Maria
  9. Like
    Ana-Maria Balas reacted to justeen in PmodKYPD and PmodOLED for Zynq   
    Dear Ana-Maria,
    Thank you so much. I already found all three links you mentioned right before you reply to me. Yes, they really help me to how to start.
    The sample codes were long, but worked. I'm trying to write a main code. I really appreciate your great help.
    You're awesome!!
    Thanks again.
  10. Like
    Ana-Maria Balas got a reaction from vicentiu in MTDS PMOD Connection issue   
    In my block design I didn't used the board flow, I made external the output pin of the IP , and then I used that name to constrain the JB Pmod pins in the Cora-Z7-07S-Master.xdc constraint file(as you can see in the picture below the bd) .
    You have two choices:
    1. You can name the Pmod's IP output anyway you want, but then you'll have to constrain the Pmod pins in the xdc file as I did in my block design 
    2. You can use the board flow as suggested in the tutorial, and you don't use the xdc file. "jb" is the name of the Pmod connector, as it is supposed to be, you cannot change it. 
    When you connect it from the board tab, it means that the output of the Pmod IP will be constrained automatically to the right pin connector( named "jb") of your board, and this way you don't have to constrain those pins manually.  
     Those warnings won't affect your project, it means that the Pmod MTDS IP was packed with a different board when it was created.
    Just add the Zynq, add the Pmod MTDS using board flow, leave the "jb" as it is, ignore the warnings related to different board value of the Pmod MTDS IP, make sure you validated your design, create HDL Wrapper and generate bitstream.
    Then follow the rest of the steps from the tutorial. 
     
    Cheers,
    Ana-Maria
     
  11. Like
    Ana-Maria Balas got a reaction from WillTx in MTDS PMOD Connection issue   
    Hello @WillTx,
    1. There is an IP for Pmod MTDS with the drivers you need to make your Pmod MTDS working. It also contains 10 demos from which you can learn a lot. You can find it here :
    https://github.com/Digilent/vivado-library/tree/master/ip/Pmods/PmodMTDS_v1_0. 
    You need to download the entire vivado-library (from here) then follow the tutorial for using Pmod IP cores in Vivado.
    2. Your block design after adding the Pmod MTDS IP:
    3. You can use the board flow to automatically connect to JB Pmod connector without a XDC constrain file (as it shows in the tutorial at step 3).  You need to install the board files first.
    If you want to use the Cora-Z7-07S-Master.xdc constraint file, below are the lines corresponding to JB Pmod connector :

    4. Please follow the REAME.txt found in drivers/PmodMTDS_v1_0/examples/
     
    Cheers,
    Ana-Maria
  12. Like
    Ana-Maria Balas got a reaction from Cristian.Fatu in MTDS PMOD Connection issue   
    Hello @WillTx,
    1. There is an IP for Pmod MTDS with the drivers you need to make your Pmod MTDS working. It also contains 10 demos from which you can learn a lot. You can find it here :
    https://github.com/Digilent/vivado-library/tree/master/ip/Pmods/PmodMTDS_v1_0. 
    You need to download the entire vivado-library (from here) then follow the tutorial for using Pmod IP cores in Vivado.
    2. Your block design after adding the Pmod MTDS IP:
    3. You can use the board flow to automatically connect to JB Pmod connector without a XDC constrain file (as it shows in the tutorial at step 3).  You need to install the board files first.
    If you want to use the Cora-Z7-07S-Master.xdc constraint file, below are the lines corresponding to JB Pmod connector :

    4. Please follow the REAME.txt found in drivers/PmodMTDS_v1_0/examples/
     
    Cheers,
    Ana-Maria
  13. Like
    Ana-Maria Balas got a reaction from vicentiu in MTDS PMOD Connection issue   
    Hello @WillTx,
    1. There is an IP for Pmod MTDS with the drivers you need to make your Pmod MTDS working. It also contains 10 demos from which you can learn a lot. You can find it here :
    https://github.com/Digilent/vivado-library/tree/master/ip/Pmods/PmodMTDS_v1_0. 
    You need to download the entire vivado-library (from here) then follow the tutorial for using Pmod IP cores in Vivado.
    2. Your block design after adding the Pmod MTDS IP:
    3. You can use the board flow to automatically connect to JB Pmod connector without a XDC constrain file (as it shows in the tutorial at step 3).  You need to install the board files first.
    If you want to use the Cora-Z7-07S-Master.xdc constraint file, below are the lines corresponding to JB Pmod connector :

    4. Please follow the REAME.txt found in drivers/PmodMTDS_v1_0/examples/
     
    Cheers,
    Ana-Maria