Ana-Maria Balas

Technical Forum Moderator
  • Content Count

    87
  • Joined

  • Last visited

  • Days Won

    8

Reputation Activity

  1. Like
    Ana-Maria Balas got a reaction from Hos Sam97 in digilent nexys artix 7 100T UCf File   
    Hello @Hos Sam97,
    Nexys A7 have the same UCF file as Nexys 4 DDR. You can download the UCF file from here.
    The UCF file contains the constrains for all the Onboard I/O.
  2. Like
    Ana-Maria Balas got a reaction from mladenik in Setting the Internal reference on PMOD DA4   
    What is the fixed version you are using?
    The clock was 100Mhz when I used it with Microblaze.
  3. Like
    Ana-Maria Balas got a reaction from mladenik in Setting the Internal reference on PMOD DA4   
    To clarify, the Microblaze clock was set to 100Mhz, and the Axi Quad SPI used the default internal frequency ratio, which I think is 16, so I got a SCLK frequency of around 6 Mhz.
    But you say that you fixed it, and I want to know which mode did you use and it's working properly with Pmod DA4? 
  4. Like
    Ana-Maria Balas got a reaction from mladenik in Setting the Internal reference on PMOD DA4   
    I will try it to see how it works.
    Thank you too. 
     
  5. Like
    Ana-Maria Balas got a reaction from nicke in cmod a7 TRX/MGTs available?   
    Yes the transceivers are not routed on Cmod A7, because you would need a high-speed connector, which would increase the cost of the board and this was not the intention for a small board.
    The only board with Artix 7 is Nexys Video, which has a FMC connector.
  6. Like
    Ana-Maria Balas got a reaction from JKing in FPGA and DAC Interface compatibility   
    Hello @JKing,
    The system boards are from Xilinx, and the adapter board and DAC boards are from Analog Devices, so maybe you would find better responses on the Xilinx forum or Analog Devices, rather from our forum.
    However, I asked one of our engineers about this issue and here is the response I got: 
    For KC705 case with AD-DAC-FMC-ADP adapter and AD9142A-M5375-EBZ board compatibility between the pins from the DAC board, through the adapter board and up to the FPGA seems OK, for both FMC connectors on the KC705 board. Logical levels: The DAC uses LVDS, on the KC705 board the logical levels LVDS_25 must be set (they are the only ones available from the HR banks, where the FMC connectors are connected).
    Maximum frequencies / maximum data rates at FPGA banks: in https://www.xilinx.com/support/documentation/data_sheets/ds182_Kintex_7_Data_Sheet.pdf on page 14, in Table 17, data rates for "DDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 14)", in the HR bank, for speed grades -2 (which is on the KC705 board), is 1250 Mb/s :
    -The DAC can support a maximum of 575MHz on the DCI clock, with the data squared on opposite fronts (I and Q respectively, on opposite fronts of the clock) => 575Mb/s maximum useful data rate required by the DAC.
    -Since we have to send the data to the DAC in quadrature, the maximum useful FPGA data rate is half of 1250 Mb/s, ie 625 Mb/s.
    - 575Mb/s <625Mb/s, so it should be OK.
    For security, you should look for a reference / example design with OSERDES for the respective board, modify it for your DAC and try to compile it with the desired frequencies, to see if the implementation passes.
    -DATA_WIDTH = 4 to 14 at OSERDES does not affect us, because we actually receive the data of a word in parallel, on different LVDS pairs.
    -If we were to use DAC in byte mode, then we would need 2 clock cycles to send 16 bits of I and 16 bits of Q. Of the 1250Mb/s that supports FPGA, we would remain with ¼, that is with 312.5 Mb/s, less than 575Mb/s, so I would not reach the maximum DAC rate.
    Timing analysis: The FPGA must send the data synchronously with each edge of the DCI clock. Fortunately, the DAC has a DLL and a delay line respectively; Depending on the working frequency, one of the two can be used to ease the timing requirements (i.e. to apply a delay between the clock and the data, so that the timing of the DAC is satisfied).
    You should analyze the rest of cases:
    KCU105 with AD9142A-M5375-EBZ;
    KC705 with AD9122-M5375-EBZ;
    KCU105 with AD9122-M5375-EBZ.
    Best regards.
    Ana-Maria Balas
     
  7. Like
    Ana-Maria Balas got a reaction from Zain Zaidi in Can't figure out physical connections for Basys3 XADC Demo   
    Hello @Zain Zaidi,
    The JAXC6 and JAXC12 provides 3.3V VCC and are not inputs.
    The ADC differential input must be with a voltage difference between 0-1V.
    The input signal for each JXADC channel of the Pmod must be between 0 - 3.3V.
    So if you connect your XA_N channels to ground, then you must apply to the XA_P channels a voltage between 0-1V.
    ex :   XA1_P= 0.5sin(wt), XA1_N = 0V   => XA1_P - XA1_N = 0.5sin(wt) differential input for ADC.
    XA1_P= 2.5sin(wt), XA1_N = 2.2sin(wt)   => XA1_P - XA1_N = 0.3sin(wt) differential input for +ADC.
    Please read ug480  pages 31-32.
    If you look into the schematic file of the Basys 3, you will see that the Vp(A12) and Vn(B13) pins are connected to XADCGND.
     
  8. Like
    Ana-Maria Balas got a reaction from Luke Abela in Nexys 4 DDR Ethernet Tutorial - Tera Term   
    I reproduced the problem somehow. You need to make sure that you follow the exact steps as they are described in the tutorial:
    1. Connect your PC to your Nexys 4 DDR using an Ethernet cable.
    2. Make sure you set the static TCP/IPv4 address "192.168.1.XX” for your PC, where XX is a value between 2 and 255, but not 10.
    This is important because the board and the PC has to be in the same network , so that's why you set "192.168.1" which is the Network Identifier. The XX is the Host Identifier.
    Below is a screenshot of the connection through serial port and what it displays when you run the application.

    3. Connect to Tera Term using the board IP : 192.168.1.10.
    You need to open a new connection and set 192.168.1.10, Telnet, TCP port 7.
    Cheers,
    Ana-Maria
  9. Like
    Ana-Maria Balas got a reaction from Mounir in Object Detection System Requirements   
    I think that you could use Zybo Z7 with Pcam 5C and Pmod WiFi.
    Here are some useful projects which you can modify them and adapt them to your needs :
    Zybo Z7 -20 Pcam 5C Demo :  https://github.com/Digilent/Zybo-Z7-20-pcam-5c
    Pmod Wi-FI IP and some exemples : https://github.com/Digilent/vivado-library/tree/master/ip/Pmods/PmodWIFI_v1_0
     
  10. Like
    Ana-Maria Balas got a reaction from Bryan_S in Old Spartan 3 UART code to Digilent CMOD S6 not working   
    I'm glad you worked it out!
    Best regards,
    Ana-Maria
     
  11. Like
    Ana-Maria Balas got a reaction from Bryan_S in Old Spartan 3 UART code to Digilent CMOD S6 not working   
    Hi @Bryan_S,
    We don't have the necessary resources to investigate/correct the code of your project.
    However the source code I provided to you above, is readable and you can test it with your project. Just integrate the clk_gen_50MHz.vhd and UART_RX_CTRL.vhd files to your project. I think those files are all you need.
    Cheers,
    Ana-Maria
  12. Like
    Ana-Maria Balas got a reaction from Irfan in ZYNQ UART Issue   
    Hello @Irfan,
    Which board are you using ? Also could you post a screenshot of your block design ?
    Cheers,
    Ana-Maria
  13. Like
    Ana-Maria Balas got a reaction from Bryan_S in Old Spartan 3 UART code to Digilent CMOD S6 not working   
    Hello @Bryan_S,
    Here is a demo project for Cmod S6 from https://reference.digilentinc.com/reference/programmable-logic/cmod-s6/start.
    I looked into the source files and there is clk_gen_50MHz.vhd.
    You can see in the top.vhd file how the clk_gen_50MHz is instantiated and used.
    I don't know what is the clk16x in your code, but here are some source files for serial port serialport_v3.zip The sources are for Nexys4 DDR which has a 100 MHz system clock.
    But in your case, if you use the clk_gen_50MHz, you'll have a 50 MHz clock instead of 100 MHz, 9600 baud rate, as shown in the UART_RX_CTRL.vhd file. The same for UART_TX_CTRL.vhd.
    I don't know if you'll use the sources from above, but I hope it helps.
    Best regards,
    Ana-Maria Balas
     
  14. Like
    Ana-Maria Balas got a reaction from Cristian.Fatu in Old Spartan 3 UART code to Digilent CMOD S6 not working   
    Hello @Bryan_S,
    Here is a demo project for Cmod S6 from https://reference.digilentinc.com/reference/programmable-logic/cmod-s6/start.
    I looked into the source files and there is clk_gen_50MHz.vhd.
    You can see in the top.vhd file how the clk_gen_50MHz is instantiated and used.
    I don't know what is the clk16x in your code, but here are some source files for serial port serialport_v3.zip The sources are for Nexys4 DDR which has a 100 MHz system clock.
    But in your case, if you use the clk_gen_50MHz, you'll have a 50 MHz clock instead of 100 MHz, 9600 baud rate, as shown in the UART_RX_CTRL.vhd file. The same for UART_TX_CTRL.vhd.
    I don't know if you'll use the sources from above, but I hope it helps.
    Best regards,
    Ana-Maria Balas
     
  15. Like
    Ana-Maria Balas got a reaction from Cristian.Fatu in PmodKYPD and PmodOLED for Zynq   
    Hello @justeen,
    I see that you used the Pmod IP's from the vivado-library. Each IP you added to your block design comes with a demo. In the vivado-library folder, corresponding to your Pmod IP,  you will find the example sources.
    Here are the demo sources for Pmod Oled and here are the demo sources for Pmod KYPD. You can look into the example sources for both of the Pmods and adapt them to your project.
    At step 11. Create a New Application Project in SDK from the tutorial explains how to create a project in SDK when using Digilent Pmod IPs.
    Cheers,
    Ana-Maria
  16. Like
    Ana-Maria Balas reacted to justeen in PmodKYPD and PmodOLED for Zynq   
    Dear Ana-Maria,
    Thank you so much. I already found all three links you mentioned right before you reply to me. Yes, they really help me to how to start.
    The sample codes were long, but worked. I'm trying to write a main code. I really appreciate your great help.
    You're awesome!!
    Thanks again.
  17. Like
    Ana-Maria Balas got a reaction from vicentiu in MTDS PMOD Connection issue   
    In my block design I didn't used the board flow, I made external the output pin of the IP , and then I used that name to constrain the JB Pmod pins in the Cora-Z7-07S-Master.xdc constraint file(as you can see in the picture below the bd) .
    You have two choices:
    1. You can name the Pmod's IP output anyway you want, but then you'll have to constrain the Pmod pins in the xdc file as I did in my block design 
    2. You can use the board flow as suggested in the tutorial, and you don't use the xdc file. "jb" is the name of the Pmod connector, as it is supposed to be, you cannot change it. 
    When you connect it from the board tab, it means that the output of the Pmod IP will be constrained automatically to the right pin connector( named "jb") of your board, and this way you don't have to constrain those pins manually.  
     Those warnings won't affect your project, it means that the Pmod MTDS IP was packed with a different board when it was created.
    Just add the Zynq, add the Pmod MTDS using board flow, leave the "jb" as it is, ignore the warnings related to different board value of the Pmod MTDS IP, make sure you validated your design, create HDL Wrapper and generate bitstream.
    Then follow the rest of the steps from the tutorial. 
     
    Cheers,
    Ana-Maria
     
  18. Like
    Ana-Maria Balas got a reaction from WillTx in MTDS PMOD Connection issue   
    Hello @WillTx,
    1. There is an IP for Pmod MTDS with the drivers you need to make your Pmod MTDS working. It also contains 10 demos from which you can learn a lot. You can find it here :
    https://github.com/Digilent/vivado-library/tree/master/ip/Pmods/PmodMTDS_v1_0. 
    You need to download the entire vivado-library (from here) then follow the tutorial for using Pmod IP cores in Vivado.
    2. Your block design after adding the Pmod MTDS IP:
    3. You can use the board flow to automatically connect to JB Pmod connector without a XDC constrain file (as it shows in the tutorial at step 3).  You need to install the board files first.
    If you want to use the Cora-Z7-07S-Master.xdc constraint file, below are the lines corresponding to JB Pmod connector :

    4. Please follow the REAME.txt found in drivers/PmodMTDS_v1_0/examples/
     
    Cheers,
    Ana-Maria
  19. Like
    Ana-Maria Balas got a reaction from Cristian.Fatu in MTDS PMOD Connection issue   
    Hello @WillTx,
    1. There is an IP for Pmod MTDS with the drivers you need to make your Pmod MTDS working. It also contains 10 demos from which you can learn a lot. You can find it here :
    https://github.com/Digilent/vivado-library/tree/master/ip/Pmods/PmodMTDS_v1_0. 
    You need to download the entire vivado-library (from here) then follow the tutorial for using Pmod IP cores in Vivado.
    2. Your block design after adding the Pmod MTDS IP:
    3. You can use the board flow to automatically connect to JB Pmod connector without a XDC constrain file (as it shows in the tutorial at step 3).  You need to install the board files first.
    If you want to use the Cora-Z7-07S-Master.xdc constraint file, below are the lines corresponding to JB Pmod connector :

    4. Please follow the REAME.txt found in drivers/PmodMTDS_v1_0/examples/
     
    Cheers,
    Ana-Maria
  20. Like
    Ana-Maria Balas got a reaction from vicentiu in MTDS PMOD Connection issue   
    Hello @WillTx,
    1. There is an IP for Pmod MTDS with the drivers you need to make your Pmod MTDS working. It also contains 10 demos from which you can learn a lot. You can find it here :
    https://github.com/Digilent/vivado-library/tree/master/ip/Pmods/PmodMTDS_v1_0. 
    You need to download the entire vivado-library (from here) then follow the tutorial for using Pmod IP cores in Vivado.
    2. Your block design after adding the Pmod MTDS IP:
    3. You can use the board flow to automatically connect to JB Pmod connector without a XDC constrain file (as it shows in the tutorial at step 3).  You need to install the board files first.
    If you want to use the Cora-Z7-07S-Master.xdc constraint file, below are the lines corresponding to JB Pmod connector :

    4. Please follow the REAME.txt found in drivers/PmodMTDS_v1_0/examples/
     
    Cheers,
    Ana-Maria