Ana-Maria Balas

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Everything posted by Ana-Maria Balas

  1. Hello @Kyle_Jackson, We are looking into this issue. As soon as we discover something, we'll let you know. Thank you, Ana-Maria
  2. How do you see the clock? Later edit: I saw that you are measuring it through dio. I didn't see the answer that the clock works with pullup constrains.It's good that the clock works now. See this forum thread The problem lays elsewhere. Are you using the right usb port? Are you sure the keyboard is recognized properly by PIC? The keyboard should have current consumption of 100 mA or lower. When the keyboard is connected to USB port, first it sends "AA" to host and this way you can find out if the boar
  3. Could you put pullup constrains to both clk and data pins, because in the reference manual it says: Try to modify like this: NET "USB2_CLK" LOC=K17 | IOSTANDARD=LVCMOS33 | PULLUP; #Bank = 1, pin name = IO_L40N_GCLK10_M1A6_1, Sch name = USBH2-CLK NET "USB2_DATA" LOC=L17 | IOSTANDARD=LVCMOS33 | PULLUP; #Bank = 1, pin name = IO_L40P_GCLK11_M1A5_1, Sch name = USBH2-DATA
  4. Why are you using NET USB2_CLK LOC=A12; NET USB2_DATA LOC=k17; You should use NET "USB2_CLK" LOC=K17 | IOSTANDARD=LVCMOS33; #Bank = 1, pin name = IO_L40N_GCLK10_M1A6_1, Sch name = USBH2-CLK NET "USB2_DATA" LOC=L17 | IOSTANDARD=LVCMOS33; #Bank = 1, pin name = IO_L40P_GCLK11_M1A5_1, Sch name = USBH2-DATA The correct ucf file for Anvyl is Anvyl_Master.ucf
  5. Did you try to simulate the code and see what happens? This is very important because it offers you a way to debug and see how it works and this way you can make adjustments. You should try it. Here is a tutorial
  6. Hello @Pier, Did you checked the DDS Compiler IP Guide? I see at pages 13-17 that if you use the Standard Mode of Operation then:
  7. Hello @CPerez10, Are you sure the keyboard you have is working properly with the board? You could try this project first to see how it's working and to inspire from it, and then you can create your own driver:
  8. Did you check the source code from the bottom of the page?
  9. Hi @[email protected], I attached the project for 2018.2 version with errors The errors were related to repository sources that weren't added to SDK project. The repo_0 folder inside ZedBoard-FMC-Pcam-Adapter-DEMO.ipdefs contains the driver sources for Digilent custom IPs from the hardware project. Please run the application and tell us if it's working properly.
  10. Hello @[email protected], Please download the release and when you open the project in SDK, right -click on project name -> C/C++ Build Settings then Arm v7 g++ compiler -> Directories and make sure the path is: "${workspace_loc:/${ProjName}/src}" Clean the project ( Project -> Clean) That should solve the errors regarding include files ( Fatal error: no such file or directory). After that the build should be successful. Run the application and tell us if is working. Pl
  11. Hi @Antonio Fasano, I found some project demonstration for Pmod I2S2 which I wasn't aware of it's existence before. Please check out:
  12. Hello @mukunda, Did you manage to find out the problem?
  13. Yes, I've already give him the link with some Reference projects which contains also pdf files with documentation for each project, and it explains very well the Uart component which is used with the PmodRS232 (in Interface Reference Component from the Reference projects). The info is there...
  14. No, I've looked and there isn't an IP for PMOD RS232. But there are some example projects which you can use to create one.
  15. Hello @ESJ, That IP is created by Digilent. You can modify it with the Vivado IP Packger, you can find the IP here There is also some documentation for the IP which you can read.
  16. Hello @SamuelCroteau, Did you checked the chapter for creating custom characters? you can use it to create the Tetris blocks. You can found the source code for the Unit 3 course at the bottom of the page Also you can find some info here: You also have some libraries here which I found them useful:
  17. Hello @stefan5578, The board has a Zynq SoC and can be programmed with applications created in SDK (or Vitis) based on C/ C++ languages. Also you can use it with Petalinux. You can make hardware projects in Vivado Design Suite as with any other FPGA board created by Digilent.
  18. Hello @Antonio Fasano, We currently don't have an IP for Pmod I2S2. You'll have to create one yourself based on the I2S protocol. This pdf file explains very well the I2S bus specification
  19. Hello @farzan, 1. The first critical messages doesn't affect your project. It means that the IP was tested with a project that was created with a different board than yours,but this doesn't have any impact on your project, because it is a generic IP that can be used with all Digilent boards. 2. Because you have errors, then the SDK project cannot be build and therefore you cannot program the FPGA. You have to solve the errors first. The error say that the project you created overflowed the maximum capacity of your allocated BRAM memory with 92408 bytes. This means that you didn'
  20. Yes, I think the memory test interfere with the fact that all the data and code section of the project runs from SRAM. It's good that you commented that part of code, if the project runs, then it means there is no problem with SRAM memory. Also if you want to see how the memory test behaves, just change in the linker script to use microblaze internal bram and you can uncomment that part of the test.
  21. Hello @PaulJX, I tried to reproduce the errors and I installed Vivado 2016.4 but when I try to generate the bit-\stream, no matter what project I create, the synthesis remains blocked in "queued" mode and I cannot go further with generating the bitstream. None of the solutions I found online fixed the problem, so I don't think you or me should proceed with Vivado 2016.4 version. I don't know why this is happening, I encountered bugs with this version of Vivado before and I don't use it at all. I recommend Vivado 2018.2 because I personally think is the most stable, free of bugs versi
  22. The message error is clear, those signals rgb_led_tri_o[2:0], led_2bits_tri_o[1:0] are not constrained correctly in the xdc file. There are 2 ways to verify those types of errors: 1. Verify that the names of those signals exist at the desired pins and that are spelled correctly, as they are named in the top file of the project in the Cmod_A7.xdc constrain file. 2. The GPIO, memory, and others are directly constrained when adding and IP (AXI GPIO, AXI EMC and other) from Board flow because the signal names are specified in a file from VIVADO BOARDS ( that file is this https://github.c
  23. It's okay. You can get back with the response whenever you want. I'm here!
  24. To test the external 512 SRAM with a project that is working for sure, could you try the OOB Demo for Cmod A7-35 T please? Here are the release sources for Vivado 2016.4: Here is the tutorial: Download, extract it, and follow instructions found in the tutorial above. I wanted to add that the linker script is configured to use microblaze_0_local_memory, but you can change it to use axi_emc to test that proje