Ana-Maria Balas

Digilent Staff
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Everything posted by Ana-Maria Balas

  1. Something like this : set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 PULLUP TRUE} [get_ports { scl }]; #IO_L11P_T1_SRCC_34 Sch=ck_io[0] set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 PULLUP TRUE} [get_ports { sda }]; #IO_L3N_T0_DQS_34 Sch=ck_io[1]
  2. Hello @pricejj3, The project you are using is made for Vivado 2018.2 version. Use the recommended version of Vivado. Cheers, Ana-Maria
  3. You are using Vivado HLS. Open just the Vivado 2018.3 which is Vivado HL Design. "The Vivado High-Level Synthesis compiler enables C, C++ and SystemC programs to be directly targeted into Xilinx devices without the need to manually create RTL." Also The registers and instructions are different for each flash memory, so no, they are not similar.
  4. You can see the schematic of the board on the resource center. I2C pins are right beside IO42, so i think it is convenient for your project... EDIT: @emma9513 I just remembered that you can add pull-up resistors internally from FPGA and constrain those pins in xdc.
  5. If you don't use a shield which comes equipped with pull-up resistors pre-installed, then yes, you will have to add the pull-up resistors externally. But since the I2C pins on the Shield Connector are so close to IO, why bother ?
  6. Hello @AN_newbie, The MX25L3233 is not supported by Vivado 2016.4. You need to use a more recent version. I verified in Vivado 2019.1 and is supported. Even if the tutorial uses Vivado 2016.4, the steps are the same in any version. "it looked totally foreign" - The interface for Vivado 2019.1 is not so different from Vivado 2016.4 just some design changes. I will put here some steps, maybe it will ease your effort. 1.Link the jumper JP1 to QSPI. 2.Add xdc constraint file Basys-3-Master.xdc 3.Open Implemented Design, then Settings 4.Then check bin_file box in Bistream tab 5.Configure additional bistream settings. 6.General -> Enable bitstream compresion->TRUE 7.Configuration -> Bus width - > 4 8.Ok -> Apply -> Ok -> Save 9.If you will look into xdc constraint, at the end of the file should appear those lines of code, one with COMPRESS TRUE and another with SPI_BUSWIDTH 4 10.Generate Bistream Below are the steps for programing from Vivado Hardware Manager. 11.Open Hardware Manager -> Open Target -> Auto connect 12. Add your memory. For this, right click on device (xc7a35t_0) -> Add Configuration Memory Device -> write on Search "MX25L3233" -> select the part with mx25l3233f-spi-x1_x2_x4. 13.Right click on the flash memory (mx25l3233f-spi-x1_x2_x4) -> Program Config´╗┐uration Memory Device -> add configuration file (<project_name>.bin file found in runs/impl folder) -> click OK Below are the steps for programing the flash from Vivado SDK. 11. In SDK, after you created you application and verified that it's working, go to Xilinx ->Program FPGA and beside microblaze_0 select <yourapplicationname>.elf instead of bootloop 12. Go to Xilinx -> Program Flash, then select the download.bit located inside of your hardware platform folder and leave the Offset box empty, then choose the right flah memory type. (part number is MX25L3233F ) Cheers, Ana-Maria
  7. Hello @emma9513, The Shield Connector have SPI and I2C dedicated pins. However there is no issue if you want to use the General Purpose I/O pins. You can use the EMIO for SPI, I2C and UART1 from Zynq PS then constrain them to the desired IO pins. Also you can use AXI Quad SPI IP, AXI IIC IP and AXI Uartlite then constrain them to the desired IO pins. I recommend using the first way if you want one interface per communication protocol and also you won't fill the PL with unnecessary logic if you have a big project. Let me know if you have problems. Cheers, Ana-Maria
  8. Hello @TY Fan, Did you follow the Getting Started with Digilent Pmod IPs tutorial ? I see that you are using Pmod Connector JE but the PmodWiFi IP's output is "Pmod_out_0". I think it should be "je". Also I read the README file of the example projects and there is no need for an SD card. https://github.com/Digilent/vivado-library/tree/master/ip/Pmods/PmodWIFI_v1_0
  9. I think that you could use Zybo Z7 with Pcam 5C and Pmod WiFi. Here are some useful projects which you can modify them and adapt them to your needs : Zybo Z7 -20 Pcam 5C Demo : https://github.com/Digilent/Zybo-Z7-20-pcam-5c Pmod Wi-FI IP and some exemples : https://github.com/Digilent/vivado-library/tree/master/ip/Pmods/PmodWIFI_v1_0
  10. Do you want a Linux based system or bare-metal?
  11. Hello @Mounir, What do you mean with "IoT features" ? Could you please be more specific with what are you planning to do?
  12. Hello @TeslaCrytpo, Cmod S7 doesn't have DDR and because of that you won't have an application to store in the DDR. Through the offset address the boot-loader knows from which address to load the application from DDR. Some steps should be skipped from the tutorial.I think it would be easier to write for you all the steps here: 1. When your design is ready to be generated into a bitstream select Open Implemented Design, then Settings 2.Then check bin_file box in Bistream tab 3.Configure additional bistream settings. 4.General -> Enable bitstream compresion- TRUE 5.Configuration -> Bus width - > 4 6.Ok -> Apply 7.If you will look into the xdc constraint file, at the end of the file it should appear 2 lines of code, one with COMPRESS TRUE and another with SPI_BUSWIDTH 4 8. In SDK, after you created you application and verified that it's working, go to Program FPGA and beside microblaze_0 select <yourapplicationname>.elf instead of bootloop 9. Go to Xilinx -> Program Flash, then select the download.bit located inside of your hardware platform folder and leave the Offset box empty, then choose the right flah memory type. (part number is MX25L3233F ) The flash has now been programmed and you can test it.
  13. I think you should ask for support from Ettus company. I cannot help you because I don't have the preset that they are using for Zynq, and I don't know the DDR Controller Configuration and other configurations. The purpose of this board is not to be used for general applications and I think you should use the Linux image provided by them, "the OS is responsible for all the device and peripheral management" they are saying on their website.
  14. I created a boot.bin file BOOT.bin I enabled only the UART and SD from Zynq. You can try it to see if it's printing in the terminal application window. Set the appropriate COM port and 115200 baud rate, 1 stop bit, no parity, 8-bit character length.
  15. I don't understand how you probed for e310? You took the SD card with boot.bin that you generated for Arty Z7 and inserted into SD port of the Ettus board? Or did you make a new project for Ettus E310, and generated a new boot.bin for it ? The Zynq chip is different for Arty and Ettus. The bitstream generated for Arty Z7 will never work on Ettus.
  16. As you can see in the reference manual for Atlys it is normal for the test to detect a short if you put JP6 and JP7 jumper, because those are digital lines. Those jumpers shouldn't be loaded in the usual applications, but if you want to loop back data through I2C, then you can load them.
  17. Hello @sapperlott, Do you have other peripherals connected to the board? Can you put here what is showing in the Status Window? Also please add here a screen capture of the Adept window. Cheers, Ana-Maria
  18. Hello @Thomas_Price, Did you follow the arty-getting-started-with-microblaze-servers tutorial? Also in this thread are some files that were replaced and this is the final project for Vivado 2018.2 after replacing those files : Arty_A7_web_server_vivado_2018_2.zip You can import the Arty_A7_web_server_vivado_2018_2.sdk project sources into your sdk project. Best regards, Ana-Maria
  19. I'm glad you worked it out! Best regards, Ana-Maria
  20. Ana-Maria Balas

    BANK ERROR

    Hello @Sunses, Which board are you using ? And what is your block design ? You need to give us more details about your project and what you want to do. Cheers, Ana-Maria
  21. Hello @jonpaolo02, I think you didn't follow the exact steps for adding the example sources to your project. 1. When you created the project in SDK you need to select C++ language, then NEXT and Empty Project. 2. Go to the location of where you saved the vivado-library folder, in the Pmod WIFI directory (something like (USER PATH)\vivado-library\ip\Pmods\PmodWIFI_v1_0\drivers\PmodWIFI_v1_0\examples ) and copy the example folder you want to use, HTTPServer. 3. Paste the HTTPServer folder into your SDK project folder and delete the main.cc file. 4. In SDK, right click the project name -> Refresh. Your HTTPServer example will be added like below 5. The only error I did get is the one from below and I replaced that line with #include "MRF24G/utility/ud_inc/internal/wf_global_includes.h" Please try again and tell me if you encounter other problems. I used Vivado 2016.4 for creating the project. Cheers, Ana-Maria
  22. Hi @Bryan_S, We don't have the necessary resources to investigate/correct the code of your project. However the source code I provided to you above, is readable and you can test it with your project. Just integrate the clk_gen_50MHz.vhd and UART_RX_CTRL.vhd files to your project. I think those files are all you need. Cheers, Ana-Maria
  23. Just now I realize you are referring to USB 2.0 port and not micro USB port. I'm sorry for that. I'm glad you worked it out. Have a great day, Ana-Maria
  24. Hello @TANII, You cannot have multiple UART channels using the Zybo Z7-20 USB port because of the FTDI chip. You can route through PL using the Pmod USBUART which has only one UART channel or you can use the pmod connector with another FTDI with 4 UART channels. Cheers, Ana-Maria Balas
  25. Hello @Bryan_S, Here is a demo project for Cmod S6 from https://reference.digilentinc.com/reference/programmable-logic/cmod-s6/start. I looked into the source files and there is clk_gen_50MHz.vhd. You can see in the top.vhd file how the clk_gen_50MHz is instantiated and used. I don't know what is the clk16x in your code, but here are some source files for serial port serialport_v3.zip The sources are for Nexys4 DDR which has a 100 MHz system clock. But in your case, if you use the clk_gen_50MHz, you'll have a 50 MHz clock instead of 100 MHz, 9600 baud rate, as shown in the UART_RX_CTRL.vhd file. The same for UART_TX_CTRL.vhd. I don't know if you'll use the sources from above, but I hope it helps. Best regards, Ana-Maria Balas