Ana-Maria Balas

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Everything posted by Ana-Maria Balas

  1. I will try it to see how it works. Thank you too.
  2. To clarify, the Microblaze clock was set to 100Mhz, and the Axi Quad SPI used the default internal frequency ratio, which I think is 16, so I got a SCLK frequency of around 6 Mhz. But you say that you fixed it, and I want to know which mode did you use and it's working properly with Pmod DA4?
  3. What is the fixed version you are using? The clock was 100Mhz when I used it with Microblaze.
  4. I know what the datasheet is telling, but I know for sure because I tested with our demo with the Pmod DA4 IP and Microblaze, and it's mode 3. That is why I said in the begining that the SPI mode is 3.
  5. Use the mode 3, not the mode 2. Yes the rising edge of clock should be in the center for mode 3.
  6. The hexa value is 08000001h not 080001h for the input register to set the internal ref. The Pmod DA4 comunicates over SPI mode 3. From your simulation I see that the mode is mode 2. The data is available on the falling edge of SCLK. Below is a diagram that can help you understand: For mode 3, you want the data to be available on the leading edge not on the falling edge of SCLK.
  7. Hello @linasr, Currently we don't have a project for FMC Pcam with Genesys 2, but there is one for ZedBoard. You can try to port the project from ZedBoard to Genesys 2. Here is the github repo: https://github.com/Digilent/ZedBoard-FMC-Pcam-Adapter-DEMO
  8. Hello @mladenik, Are you sure that you implemented the SPI protocol correctly? The SPI mode is mode 3. Also are you sure you set the correct field inside the 32 bit AD5628 Input Register?
  9. Hello @AVA, Could you post a photo from the Vivado Hardware Manager to see if the FPGA is detected by Vivado? This way we can verify if the USB 2 is working properly.
  10. Hello @bitstre@m, Unfortunately you can program the Cmod S6 flash memory only with IMPACT.
  11. Hello @jason.s and @rfx, Apparently the pins were assigned that way because the shield connector needs to be compatible with the Multi touch display shield. See this issue. So the changes won't be made to the board files. However you can modify the board file, so you can use the shield and spi_ss without being interchanged. A notice will be placed in the readme.file of the vivado-boards about this issue. Thank you, Ana-Maria
  12. Yes the transceivers are not routed on Cmod A7, because you would need a high-speed connector, which would increase the cost of the board and this was not the intention for a small board. The only board with Artix 7 is Nexys Video, which has a FMC connector.
  13. Hello @nicke, The Cmod A7 doesn't have MGT.
  14. Good luck with your project!
  15. Hello @rddlr, At the first look to your code I saw that get_ports led_2 is without {} in the xdc file. Try to put [get_ports { led_2 } ] Also did you try to use a different led and test your code to see that it runs fine?
  16. Hello @JKing, The system boards are from Xilinx, and the adapter board and DAC boards are from Analog Devices, so maybe you would find better responses on the Xilinx forum or Analog Devices, rather from our forum. However, I asked one of our engineers about this issue and here is the response I got: For KC705 case with AD-DAC-FMC-ADP adapter and AD9142A-M5375-EBZ board compatibility between the pins from the DAC board, through the adapter board and up to the FPGA seems OK, for both FMC connectors on the KC705 board. Logical levels: The DAC uses LVDS, on the KC705 board the logical levels LVDS_25 must be set (they are the only ones available from the HR banks, where the FMC connectors are connected). Maximum frequencies / maximum data rates at FPGA banks: in https://www.xilinx.com/support/documentation/data_sheets/ds182_Kintex_7_Data_Sheet.pdf on page 14, in Table 17, data rates for "DDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 14)", in the HR bank, for speed grades -2 (which is on the KC705 board), is 1250 Mb/s : -The DAC can support a maximum of 575MHz on the DCI clock, with the data squared on opposite fronts (I and Q respectively, on opposite fronts of the clock) => 575Mb/s maximum useful data rate required by the DAC. -Since we have to send the data to the DAC in quadrature, the maximum useful FPGA data rate is half of 1250 Mb/s, ie 625 Mb/s. - 575Mb/s <625Mb/s, so it should be OK. For security, you should look for a reference / example design with OSERDES for the respective board, modify it for your DAC and try to compile it with the desired frequencies, to see if the implementation passes. -DATA_WIDTH = 4 to 14 at OSERDES does not affect us, because we actually receive the data of a word in parallel, on different LVDS pairs. -If we were to use DAC in byte mode, then we would need 2 clock cycles to send 16 bits of I and 16 bits of Q. Of the 1250Mb/s that supports FPGA, we would remain with ΒΌ, that is with 312.5 Mb/s, less than 575Mb/s, so I would not reach the maximum DAC rate. Timing analysis: The FPGA must send the data synchronously with each edge of the DCI clock. Fortunately, the DAC has a DLL and a delay line respectively; Depending on the working frequency, one of the two can be used to ease the timing requirements (i.e. to apply a delay between the clock and the data, so that the timing of the DAC is satisfied). You should analyze the rest of cases: KCU105 with AD9142A-M5375-EBZ; KC705 with AD9122-M5375-EBZ; KCU105 with AD9122-M5375-EBZ. Best regards. Ana-Maria Balas
  17. Sure. We will modify it there too. Thank you!
  18. Hello @jason.s and @rfx, The board files were updated 1 month ago. See the commit: https://github.com/Digilent/vivado-boards/commit/b427ce600252806c739f1d1595cd8569d2956b0c Also the git repository where the xdc files are updated is here. We will change the pin assignment in the xdc file of the Arty-Z7-20-base-linux project too. Best regards, Ana-Maria Balas
  19. Hello @IanM, I think there is a syntax error in your code because the original code is correct(see below):
  20. Hello @pbrinkerhoff, I wrote to you a private message regarding this issue.
  21. Hello @Leo_W, I wrote to you a private message regarding this issue.
  22. Hello @Zain Zaidi, The JAXC6 and JAXC12 provides 3.3V VCC and are not inputs. The ADC differential input must be with a voltage difference between 0-1V. The input signal for each JXADC channel of the Pmod must be between 0 - 3.3V. So if you connect your XA_N channels to ground, then you must apply to the XA_P channels a voltage between 0-1V. ex : XA1_P= 0.5sin(wt), XA1_N = 0V => XA1_P - XA1_N = 0.5sin(wt) differential input for ADC. XA1_P= 2.5sin(wt), XA1_N = 2.2sin(wt) => XA1_P - XA1_N = 0.3sin(wt) differential input for +ADC. Please read ug480 pages 31-32. If you look into the schematic file of the Basys 3, you will see that the Vp(A12) and Vn(B13) pins are connected to XADCGND.
  23. Hello @gsm, The Micro USB connector is made by Wiscon Technology part number: WMRU2AB-5-xxR4D2P3. Here is the datasheet http://www.wisconn.com.tw/Products-detail-en.aspx?P_Id=1851.
  24. That warning is not critical. In UG994 Xilinx says: If there is a bus interface associated with this clock then you should add this parameter. But I see that you are not using any interfaces. I think is safe to ignore this warning.
  25. Hello @netanel_shor, Here are some steps that could help you : 1. Open your RTL project that contains the vhdl/verilog files of your RTL module EightPIRSensors. 2. Tools -> Create and Package New IP 3. Package your current project 4. After you choose the location of you IP and hit Next and Finish, it will open up a window to Package your IP. After you edit the Identification tab, choose the Compatibility, make sure you checked the other tabs too and everything looks alright then you can Package IP. 5. Add your IP to the block design (make sure that the path of where you saved your Packed IP is added in Settings -> IP -> Repository-> IP Repositories) Cheers, Ana-Maria