Ana-Maria Balas

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Ana-Maria Balas last won the day on November 14

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About Ana-Maria Balas

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  1. I created a boot.bin file BOOT.bin I enabled only the UART and SD from Zynq. You can try it to see if it's printing in the terminal application window. Set the appropriate COM port and 115200 baud rate, 1 stop bit, no parity, 8-bit character length.
  2. I don't understand how you probed for e310? You took the SD card with boot.bin that you generated for Arty Z7 and inserted into SD port of the Ettus board? Or did you make a new project for Ettus E310, and generated a new boot.bin for it ? The Zynq chip is different for Arty and Ettus. The bitstream generated for Arty Z7 will never work on Ettus.
  3. As you can see in the reference manual for Atlys it is normal for the test to detect a short if you put JP6 and JP7 jumper, because those are digital lines. Those jumpers shouldn't be loaded in the usual applications, but if you want to loop back data through I2C, then you can load them.
  4. Hello @sapperlott, Do you have other peripherals connected to the board? Can you put here what is showing in the Status Window? Also please add here a screen capture of the Adept window. Cheers, Ana-Maria
  5. Hello @Thomas_Price, Did you follow the arty-getting-started-with-microblaze-servers tutorial? Also in this thread are some files that were replaced and this is the final project for Vivado 2018.2 after replacing those files : Arty_A7_web_server_vivado_2018_2.zip You can import the Arty_A7_web_server_vivado_2018_2.sdk project sources into your sdk project. Best regards, Ana-Maria
  6. I'm glad you worked it out! Best regards, Ana-Maria
  7. Ana-Maria Balas

    BANK ERROR

    Hello @Sunses, Which board are you using ? And what is your block design ? You need to give us more details about your project and what you want to do. Cheers, Ana-Maria
  8. Hello @jonpaolo02, I think you didn't follow the exact steps for adding the example sources to your project. 1. When you created the project in SDK you need to select C++ language, then NEXT and Empty Project. 2. Go to the location of where you saved the vivado-library folder, in the Pmod WIFI directory (something like (USER PATH)\vivado-library\ip\Pmods\PmodWIFI_v1_0\drivers\PmodWIFI_v1_0\examples ) and copy the example folder you want to use, HTTPServer. 3. Paste the HTTPServer folder into your SDK project folder and delete the main.cc file. 4. In SDK, right click the project name -> Refresh. Your HTTPServer example will be added like below 5. The only error I did get is the one from below and I replaced that line with #include "MRF24G/utility/ud_inc/internal/wf_global_includes.h" Please try again and tell me if you encounter other problems. I used Vivado 2016.4 for creating the project. Cheers, Ana-Maria
  9. Hi @Bryan_S, We don't have the necessary resources to investigate/correct the code of your project. However the source code I provided to you above, is readable and you can test it with your project. Just integrate the clk_gen_50MHz.vhd and UART_RX_CTRL.vhd files to your project. I think those files are all you need. Cheers, Ana-Maria
  10. Just now I realize you are referring to USB 2.0 port and not micro USB port. I'm sorry for that. I'm glad you worked it out. Have a great day, Ana-Maria
  11. Hello @TANII, You cannot have multiple UART channels using the Zybo Z7-20 USB port because of the FTDI chip. You can route through PL using the Pmod USBUART which has only one UART channel or you can use the pmod connector with another FTDI with 4 UART channels. Cheers, Ana-Maria Balas
  12. Hello @Bryan_S, Here is a demo project for Cmod S6 from https://reference.digilentinc.com/reference/programmable-logic/cmod-s6/start. I looked into the source files and there is clk_gen_50MHz.vhd. You can see in the top.vhd file how the clk_gen_50MHz is instantiated and used. I don't know what is the clk16x in your code, but here are some source files for serial port serialport_v3.zip The sources are for Nexys4 DDR which has a 100 MHz system clock. But in your case, if you use the clk_gen_50MHz, you'll have a 50 MHz clock instead of 100 MHz, 9600 baud rate, as shown in the UART_RX_CTRL.vhd file. The same for UART_TX_CTRL.vhd. I don't know if you'll use the sources from above, but I hope it helps. Best regards, Ana-Maria Balas
  13. Glad it helped. Best regards, Ana-Maria
  14. Ana-Maria Balas

    ZYNQ UART Issue

    Hello @Irfan, Which board are you using ? Also could you post a screenshot of your block design ? Cheers, Ana-Maria
  15. If you check Reset entire system box in Run Configurations window it shows something on uart terminal ?