Ana-Maria Balas

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  1. Hello @afif.ramadhan, I think the parameters are already computed using decutil. See below Quote and example from the IP documentation pdf: You only have to take the processed calibration values using decutil and feed them to the Zmod AWG controller IP. You can load the values using the IP interface or using the external calibration signals through Constant IP blocks. Just to clarify something, through AXI Stream only the sample DATA is sent, not the calibration data.
  2. @HomaGOD, Could you post a screencapture of your whole block design from Vivado? Then screen capture from the Adress Editor tab?
  3. In boot partition please set in uEnv: #Zmod configuratio to use: adc, dac, adc-dac zmod=dac Also go to Petalinux <repo-location>/images/linux/ and copy somewhere the additional files: system.bit and system.dtb then rename them to zm-dac.bit and zm-dac.dtb and then copy these files to boot partition (replace the existing ones). So you have to use all 4 files from <repo-location>/images/linux/: BOOT.BIN image.ub zm-dac.bit zm-dac.dtb
  4. This is happening because the Linux project is using the old hardware. You have to update the Petalinux project with the new hardware I provided here, build it, then you can use the Linux demo application from Xilinx SDK. Follow the steps (see each title below) from readme https://github.com/Digilent/Eclypse-Z7-OS/tree/zmod_dac/master#readme 1. Setup (You have to install Petalinux 2019.1 see Installation Requirements to install all the necessary packages from the table and Run PetaLinux Tools Installer) 2. Source the Petalinux Tools 3. Download the Petalinux Project 4.
  5. In the Eclypse-SW project, did you right click design_1_wrapper_hw_platform_0 -> Change Hardware Platform Specification -> then selected the downloaded design_1_wrapper.hdf from above? Then regenerate the BSP sources:
  6. Hello @NithinA, I added the changes to the AXI_Zmod_DAC1411 IP on branch feature/zmod-support in vivado-library repository. https://github.com/Digilent/vivado-library/tree/feature/zmod-support If you want to update the hardware project with upgraded IP, you will have to: 1. git checkout the hw for the zmod_dac demo 2. cd into repo/vivado-library 3. git checkout feature/zmod-support with the latest changes 4. go to Vivado tcl console and create the hw project: set argv ""; source digilent-vivado-scripts/digilent-vivado-checkout.tcl 5. in Reports/Report
  7. Hello @Kyle_Jackson, We are looking into this issue. As soon as we discover something, we'll let you know. Thank you, Ana-Maria
  8. How do you see the clock? Later edit: I saw that you are measuring it through dio. I didn't see the answer that the clock works with pullup constrains.It's good that the clock works now. See this forum thread https://forum.digilentinc.com/topic/9382-anvyl-board-hidps2keyboard-interface/ The problem lays elsewhere. Are you using the right usb port? Are you sure the keyboard is recognized properly by PIC? The keyboard should have current consumption of 100 mA or lower. When the keyboard is connected to USB port, first it sends "AA" to host and this way you can find out if the boar
  9. Could you put pullup constrains to both clk and data pins, because in the reference manual it says: Try to modify like this: NET "USB2_CLK" LOC=K17 | IOSTANDARD=LVCMOS33 | PULLUP; #Bank = 1, pin name = IO_L40N_GCLK10_M1A6_1, Sch name = USBH2-CLK NET "USB2_DATA" LOC=L17 | IOSTANDARD=LVCMOS33 | PULLUP; #Bank = 1, pin name = IO_L40P_GCLK11_M1A5_1, Sch name = USBH2-DATA
  10. Why are you using NET USB2_CLK LOC=A12; NET USB2_DATA LOC=k17; You should use NET "USB2_CLK" LOC=K17 | IOSTANDARD=LVCMOS33; #Bank = 1, pin name = IO_L40N_GCLK10_M1A6_1, Sch name = USBH2-CLK NET "USB2_DATA" LOC=L17 | IOSTANDARD=LVCMOS33; #Bank = 1, pin name = IO_L40P_GCLK11_M1A5_1, Sch name = USBH2-DATA The correct ucf file for Anvyl is Anvyl_Master.ucf
  11. Did you try to simulate the code and see what happens? This is very important because it offers you a way to debug and see how it works and this way you can make adjustments. You should try it. Here is a tutorial https://www.xilinx.com/video/hardware/logic-simulation.html
  12. Hello @Pier, Did you checked the DDS Compiler IP Guide? I see at pages 13-17 that if you use the Standard Mode of Operation then:
  13. Hello @CPerez10, Are you sure the keyboard you have is working properly with the board? You could try this project first to see how it's working and to inspire from it, and then you can create your own driver: https://github.com/Digilent/Basys-3-Keyboard
  14. Did you check the source code from the bottom of the page?