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  1. I cloned the Vivado Library repository again and rebuilt a new project and have managed to get the hardware process to complete (to bit-stream) using Vivado 2017.4. Thank you for your support.
  2. it looks like the file PmodOLEDrgb_axi_quad_spi_0_0.xcix is there, but not in the correct folder - will advise if it works after I copy the files to expected folders
  3. Hello Jon. I have been following the tutorial. I have extracted the "" again, keeping the complete path and complete library (previously I only extracted the PmodOLEDrgb folder), and now the connection automation does indeed connect the output port with the "JA" connector. However, I get errors when I try and synthesize (hardware is the Cora7s platform), where it reports the following error: [IP_Flow 19-157] Failed to copy file from 'c:/MyDesigns/DigilentIP/vivado-library/ip/Pmods/pmodOLEDrgb_v1_0/ip/PmodOLEDrgb_axi_quad_spi_0_0/PmodOLEDrgb_axi_quad_spi_0_0.xci' to 'c:/MyDesigns/Xilinx/C2/C2.srcs/sources_1/bd/core/ip/core_PmodOLEDrgb_0_0/ip/PmodOLEDrgb_axi_quad_spi_0_0/PmodOLEDrgb_axi_quad_spi_0_0.xci'. Examining the content of the PmodOLEDrgb folder (extracted from the "" file), some of the subfolders are empty! However, when I look in Github, I see the files are there - so I will try and clone the repository or copy the missing files manually and try again. best wishes, Franco
  4. hello - i have tried to find method to get the PmodOLEDrgb_out connection to connect to "ja" PMOD connector, but I have no luck; I have seen numerous videos on how this happens automatically during connection automation step - I cannot get the connection! what am I missing? is it a tool or IP setup issue? I am using 2018.2. The picture below shows the trace/connection I cannot achieve. Please help!