Sameer120

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  1. Hi Jon, Thanks for your input and providing links. Hi Xc6lx45, Thanks for your refernce of Trenz Electronics "Zynqberry", will take detailed look. Thanks Sameer
  2. Hi, I checked that, No this path is not avilable, but this is created by the scripts and not manually, still I tried creating this manually but when I rerun it just delete and start again, even if i dont clean the build. Thanks Sameer
  3. Hi, Thanks for sharing the information, I am not sure how to use this TCL command in SDx 2017.4, I tried below command on SDx Terminal but its not working
  4. Yes, I followed all the steps I created SYSROOT ´╗┐environment variable Then Restarted the PC after variable creation
  5. I downloaded the zip archive from release tab below link https://github.com/Digilent/reVISION-Zybo-Z7-20/releases/download/v2017.4-3/reVISION-Zybo-Z7-20-2017.4-3.zip
  6. I started from live_IO template, I first include the custom plaform and then started building new project from template. I followed steps specified in below readme https://github.com/Digilent/reVISION-Zybo-Z7-20/tree/master/sdsoc
  7. Hi bogdan, I ran the example of (revision-samples/live_IO/filter2d_pcam/) refer below link https://github.com/Digilent/revision-samples/tree/cf507d7093a176609c6c9c1479944052b8d51660/live_IO/filter2d_pcam/src The error in above log is during build, so the compile/build fails. Operating System : Windows 10 SDx Vivado : 2017.4 Version Thanks & Regards Sameer
  8. Hi Jon, Thanks for your support, please find below log file of SDSoC. ****** Vivado v2017.4 (64-bit) **** SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017 **** IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. Sourcing tcl script 'C:/Users/samee/AppData/Roaming/Xilinx/Vivado/Vivado_init.tcl' couldn't load library "features": this library or a dependent library could not be found in library path while executing "load features core" (file "C:/Users/samee/AppData/Roaming/Xilinx/Vivado/Vivado_init.tcl" line 3) source C:/SamWork/Per/Profile/Demo/Sam/L1_Sam_XFCV/L1_Sam_XFCV/Debug/_sds/p0/_vpl/ipi/ipirun.tcl -notrace Creating Vivado project and starting FPGA synthesis. --- DEBUG: source ./rebuild.tcl to create syn project INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter. Current project path is 'C:/SamWork/Per/Profile/Demo/Sam/L1_Sam_XFCV/L1_Sam_XFCV/Debug/_sds/p0/_vpl/ipi/syn' INFO: [IP_Flow 19-234] Refreshing IP repositories WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'c:/SamWork/Per/Profile/Demo/Sam/L1_Sam_XFCV/L1_Sam_XFCV/Debug/_sds/p0/_vpl/zybo_z7_20.ipdefs/repo_0'; Can't find the specified path. If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2017.4/data/ip'. WARNING: [BD 41-1661] One or more IPs have been locked in the design 'zybo_z7_20.bd'. Please run report_ip_status for more details and recommendations on how to fix this issue. List of locked IPs: zybo_z7_20_axi_dynclk_0_0 zybo_z7_20_axi_i2s_adi_0_0 zybo_z7_20_rgb2dvi_1_0 zybo_z7_20_pwm_rgb_0 zybo_z7_20_dvi2rgb_1_0 zybo_z7_20_mipi_csi2_rx_subsystem_0_0 WARNING: [IP_Flow 19-2162] IP 'zybo_z7_20_axi_dynclk_0_0' is locked: * IP definition 'axi_dynclk (1.0)' for IP 'zybo_z7_20_axi_dynclk_0_0' (customized with software release 2017.4) was not found in the IP Catalog. Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information. WARNING: [IP_Flow 19-2162] IP 'zybo_z7_20_axi_i2s_adi_0_0' is locked: * IP definition 'axi_i2s_adi (1.0)' for IP 'zybo_z7_20_axi_i2s_adi_0_0' (customized with software release 2017.4) was not found in the IP Catalog. Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information. WARNING: [IP_Flow 19-2162] IP 'zybo_z7_20_dvi2rgb_1_0' is locked: * IP definition 'dvi2rgb (1.8)' for IP 'zybo_z7_20_dvi2rgb_1_0' (customized with software release 2017.4) was not found in the IP Catalog. Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information. WARNING: [IP_Flow 19-2162] IP 'zybo_z7_20_pwm_rgb_0' is locked: * IP definition 'PWM (2.0)' for IP 'zybo_z7_20_pwm_rgb_0' (customized with software release 2017.4) was not found in the IP Catalog. Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information. WARNING: [IP_Flow 19-2162] IP 'zybo_z7_20_rgb2dvi_1_0' is locked: * IP definition 'rgb2dvi (1.4)' for IP 'zybo_z7_20_rgb2dvi_1_0' (customized with software release 2017.4) was not found in the IP Catalog. Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information. WARNING: [IP_Flow 19-2162] IP 'bd_894b_rx_0' is locked: * IP 'bd_894b_rx_0' requires one or more mandatory licenses but no valid licenses were found. However license checkpoints may prevent use of this IP in some tool flows. Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information. WARNING: [IP_Flow 19-2162] IP 'zybo_z7_20_mipi_csi2_rx_subsystem_0_0' is locked: * IP 'zybo_z7_20_mipi_csi2_rx_subsystem_0_0' requires one or more mandatory licenses but no valid licenses were found. However license checkpoints may prevent use of this IP in some tool flows. * IP 'zybo_z7_20_mipi_csi2_rx_subsystem_0_0' contains one or more locked subcores. Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information. import_files: Time (s): cpu = 00:00:14 ; elapsed = 00:00:34 . Memory (MB): peak = 375.242 ; gain = 90.418 INFO: Project created:syn --- DEBUG: setting ip_repo_paths: C:/SamWork/Per/Profile/Demo/Sam/L1_Sam_XFCV/L1_Sam_XFCV/Debug/_sds/iprepo/repo C:/Xilinx/SDx/2017.4/data/ip/xilinx ./.local_dsa/iprepo C:/Xilinx/SDx/2017.4/data/cache/xilinx ./.local_dsa/ipcache C:/Xilinx/SDx/2017.4/data/ip/xilinx --- DEBUG: update_ip_catalog INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/SamWork/Per/Profile/Demo/Sam/L1_Sam_XFCV/L1_Sam_XFCV/Debug/_sds/iprepo/repo'. INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Xilinx/SDx/2017.4/data/ip/xilinx'. INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/SamWork/Per/Profile/Demo/Sam/L1_Sam_XFCV/L1_Sam_XFCV/Debug/_sds/p0/_vpl/ipi/.local_dsa/iprepo'. INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Xilinx/SDx/2017.4/data/cache/xilinx'. INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/SamWork/Per/Profile/Demo/Sam/L1_Sam_XFCV/L1_Sam_XFCV/Debug/_sds/p0/_vpl/ipi/.local_dsa/ipcache'. WARNING: [IP_Flow 19-2207] Repository 'c:/Xilinx/SDx/2017.4/data/ip/xilinx' already exists; ignoring attempt to add it again. INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Xilinx/SDx/2017.4/data/ip/xilinx'. update_ip_catalog: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 562.063 ; gain = 186.820 --- DEBUG: config_ip_cache -use_cache_location C:/SamWork/Per/Profile/Demo/Sam/L1_Sam_XFCV/ip_cache --- DEBUG: open_bd_design -auto_upgrade [get_files zybo_z7_20.bd] Adding cell -- digilentinc.com:ip:axi_dynclk:1.0 - axi_dynclk_0 Adding cell -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_eth Adding cell -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_led Adding cell -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_sw_btn Adding cell -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_video Adding cell -- analog.com:user:axi_i2s_adi:1.0 - axi_i2s_adi_0 Adding cell -- xilinx.com:ip:axi_vdma:6.3 - axi_vdma_0 Adding cell -- xilinx.com:ip:axi_vdma:6.3 - axi_vdma_1 Adding cell -- xilinx.com:ip:axis_subset_converter:1.1 - axis_subset_converter_in Adding cell -- xilinx.com:ip:axis_subset_converter:1.1 - axis_subset_converter_out Adding cell -- xilinx.com:ip:clk_wiz:5.4 - clk_wiz_0 Adding cell -- digilentinc.com:ip:dvi2rgb:1.8 - dvi2rgb_1 Adding cell -- xilinx.com:ip:proc_sys_reset:5.0 - proc_sys_reset_0 Adding cell -- xilinx.com:ip:processing_system7:5.5 - processing_system7_0 Adding cell -- digilentinc.com:IP:PWM:2.0 - pwm_rgb Adding cell -- digilentinc.com:ip:rgb2dvi:1.4 - rgb2dvi_1 Adding cell -- xilinx.com:ip:proc_sys_reset:5.0 - psr_fclk0 Adding cell -- xilinx.com:ip:proc_sys_reset:5.0 - psr_fclk1 Adding cell -- xilinx.com:ip:v_axi4s_vid_out:4.0 - v_axi4s_vid_out_0 Adding cell -- xilinx.com:ip:v_tc:6.1 - v_tc_in Adding cell -- xilinx.com:ip:v_tc:6.1 - v_tc_out Adding cell -- xilinx.com:ip:v_vid_in_axi4s:4.0 - v_vid_in_axi4s_0 Adding cell -- xilinx.com:ip:xadc_wiz:3.3 - xadc_wiz_0 Adding cell -- xilinx.com:ip:xlconcat:2.1 - xlconcat_0 Adding cell -- xilinx.com:ip:xlconstant:1.1 - xlconstant_0 Adding cell -- xilinx.com:ip:xlconstant:1.1 - xlconstant_1 Adding cell -- xilinx.com:ip:proc_sys_reset:5.0 - psr_clkwiz2 Adding cell -- xilinx.com:ip:proc_sys_reset:5.0 - psr_clkwiz5 Adding cell -- xilinx.com:ip:proc_sys_reset:5.0 - psr_clkwiz4 Adding cell -- xilinx.com:ip:proc_sys_reset:5.0 - psr_clkwiz3 Adding cell -- xilinx.com:ip:util_ds_buf:2.1 - util_bufg_fclk1 Adding cell -- xilinx.com:ip:mipi_csi2_rx_subsystem:3.0 - mipi_csi2_rx_subsystem_0 Adding cell -- xilinx.com:ip:axis_subset_converter:1.1 - axis_subset_converter_0 Adding cell -- xilinx.com:ip:v_frmbuf_wr:2.0 - v_frmbuf_wr_0 Adding cell -- xilinx.com:ip:axi_iic:2.0 - axi_iic_0 Adding cell -- xilinx.com:ip:axi_data_fifo:2.1 - axi_data_fifo_0 Adding cell -- xilinx.com:ip:xlslice:1.0 - PS_GPIO_0 Adding cell -- xilinx.com:ip:xlslice:1.0 - PS_GPIO_2 Adding cell -- xilinx.com:ip:xlslice:1.0 - PS_GPIO_3 Adding cell -- xilinx.com:ip:axis_data_fifo:1.1 - axis_data_fifo_0 WARNING: [BD 41-1731] Type mismatch between connected pins: /axi_dynclk_0/LOCKED_O(undef) and /rgb2dvi_1/aRst_n(rst) WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_wiz_0/clk_out1(clk) and /axi_i2s_adi_0/DATA_CLK_I(undef) WARNING: [BD 41-1731] Type mismatch between connected pins: /dvi2rgb_1/aPixelClkLckd(undef) and /proc_sys_reset_0/aux_reset_in(rst) Adding cell -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc Adding cell -- xilinx.com:ip:axi_crossbar:2.1 - xbar Adding cell -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc Adding cell -- xilinx.com:ip:axi_crossbar:2.1 - xbar Adding cell -- xilinx.com:ip:axi_register_slice:2.1 - m00_regslice Adding cell -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc Adding cell -- xilinx.com:ip:axi_register_slice:2.1 - s01_regslice Adding cell -- xilinx.com:ip:axi_register_slice:2.1 - s00_regslice Successfully read diagram <zybo_z7_20> from BD file <C:/SamWork/Per/Profile/Demo/Sam/L1_Sam_XFCV/L1_Sam_XFCV/Debug/_sds/p0/_vpl/ipi/syn/syn.srcs/sources_1/bd/zybo_z7_20/zybo_z7_20.bd> --- DEBUG: source ./top.bd.tcl WARNING: [Coretcl 2-1042] No IP was identified for upgrade. CRITICAL WARNING: [BD 41-737] Cannot set the parameter C_S_AXIS_S2MM_TDATA_WIDTH on /dm_1. It is read-only. create_bd_cell: Time (s): cpu = 00:01:18 ; elapsed = 00:01:19 . Memory (MB): peak = 769.891 ; gain = 206.176 WARNING: [IP_Flow 19-4684] Expected long value for param S_AXIS_BRAM_0_ADDR_WIDTH but, float/scientific notation value 2.0 is provided. The value is converted to long type(2) WARNING: [IP_Flow 19-4684] Expected long value for param S_AXIS_BRAM_0_ADDR_WIDTH but, float/scientific notation value 5.0 is provided. The value is converted to long type(5) create_bd_cell: Time (s): cpu = 00:01:25 ; elapsed = 00:01:25 . Memory (MB): peak = 915.109 ; gain = 125.750 WARNING: [BD 41-1753] The name 'axi_ic_processing_system7_0_M_AXI_GP1' you have specified is long. The Windows OS has path length limitations. It is recommended you use shorter names(less than 25 characters) to reduce the likelihood of issues when/if running on windows OS. WARNING: [BD 41-1753] The name 'axi_ic_processing_system7_0_S_AXI_HP2' you have specified is long. The Windows OS has path length limitations. It is recommended you use shorter names(less than 25 characters) to reduce the likelihood of issues when/if running on windows OS. WARNING: [BD 41-1753] The name 'axi_ic_processing_system7_0_S_AXI_HP3' you have specified is long. The Windows OS has path length limitations. It is recommended you use shorter names(less than 25 characters) to reduce the likelihood of issues when/if running on windows OS. WARNING: [BD 5-235] No pins matched 'get_bd_pins /dm_0/mm2s_prmry_resetn_out_n' WARNING: [BD 5-235] No pins matched 'get_bd_pins /dm_1/s2mm_prmry_resetn_out_n' --- DEBUG: save_bd_design Wrote : <C:/SamWork/Per/Profile/Demo/Sam/L1_Sam_XFCV/L1_Sam_XFCV/Debug/_sds/p0/_vpl/ipi/syn/syn.srcs/sources_1/bd/zybo_z7_20/zybo_z7_20.bd> save_bd_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:15 . Memory (MB): peak = 1261.391 ; gain = 221.570 --- DEBUG: inserting profiling cores --- DEBUG: inserting SystemILA debug cores --- DEBUG: insert_chipscope_debug: No chipscope_debugs dict name - nothing to insert --- DEBUG: assign_bd_address </processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM> is being mapped into </dm_0/Data_MM2S> at <0x00000000 [ 1G ]> </processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM> is being mapped into </dm_0/Data_SG> at <0x00000000 [ 1G ]> </processing_system7_0/S_AXI_HP3/HP3_DDR_LOWOCM> is being mapped into </dm_1/Data_S2MM> at <0x00000000 [ 1G ]> </processing_system7_0/S_AXI_HP3/HP3_DDR_LOWOCM> is being mapped into </dm_1/Data_SG> at <0x00000000 [ 1G ]> </dm_0/S_AXI_LITE/Reg> is being mapped into </processing_system7_0/Data> at <0x80400000 [ 64K ]> </dm_1/S_AXI_LITE/Reg> is being mapped into </processing_system7_0/Data> at <0x80410000 [ 64K ]> </dm_2/S_AXI/Mem0> is being mapped into </processing_system7_0/Data> at <0x83C00000 [ 64K ]> </w1_xf_filter2D_1_if/S_AXI/reg0> is being mapped into </processing_system7_0/Data> at <0x83C10000 [ 64K ]> </write_output_gray_1_if/S_AXI/reg0> is being mapped into </processing_system7_0/Data> at <0x83C20000 [ 64K ]> --- DEBUG: validate_bd_design -force ERROR: [BD 5-336] This command cannot be run, as the BD-design is locked. Locked reason(s): * Block design contains locked IPs. Please run report_ip_status for more details and recommendations on how to fix this issue. List of locked IPs: zybo_z7_20_mipi_csi2_rx_subsystem_0_0 ERROR: [Common 17-39] 'validate_bd_design' failed due to earlier errors. while executing "validate_bd_design -force" (procedure "ocl_util::init_ocl_project_unip" line 202) invoked from within "ocl_util::init_ocl_project_unip $dsa_info $config_info $clk_info $debug_profile_info" (file "C:/SamWork/Per/Profile/Demo/Sam/L1_Sam_XFCV/L1_Sam_XFCV/Debug/_sds/p0/_vpl/ipi/ipirun.tcl" line 172) INFO: [Common 17-206] Exiting Vivado at Wed Mar 13 01:52:13 2019... List of locked IPs: zybo_z7_20_mipi_csi2_rx_subsystem_0_0 ERROR: [Common 17-39] 'validate_bd_design' failed due to earlier errors. while executing "validate_bd_design -force" (procedure "ocl_util::init_ocl_project_unip" line 202) invoked from within "ocl_util::init_ocl_project_unip $dsa_info $config_info $clk_info $debug_profile_info" (file "C:/SamWork/Per/Profile/Demo/Sam/L1_Sam_XFCV/L1_Sam_XFCV/Debug/_sds/p0/_vpl/ipi/ipirun.tcl" line 172) INFO: [Common 17-206] Exiting Vivado at Wed Mar 13 01:52:13 2019... Thanks & Regards Sameer
  9. Hello, I ran the Digilent Demo (Zybo Z7-20 reVISION Platform) on FPGA, but i want to modify the OpenCV functions and I am trying to run some more OpenCV funtions but getting some errors. Is there any project I can use that have opencv function like to find some contours and mark a border on that like Suqare of Circles. The other think I want to implement is to find Bright Spot in the live video stream. I am ok with running anything like OpenCV on SDSoC or XFOpenCV using HLS, I try to run the Xilinx Examples but thoes are for ZCU102/4 Boards. It would be really helpful if someone can help me with this implementation of OpenCV function like Canny, findcontors and drawing line circle or sqaure on shapes. Thanks & Regards Sameer
  10. Hello , I am using Zybo Z7-20 Board and I am using Digilent PCAM 5C on board for doing some Image Processing. I want to know, can I use Raspberry Pi Camera Module V2-8 Megapixel,1080p(https://www.raspberrypi.org/products/camera-module-v2/) with this Zybo Z7-20 Board using MIPI interface. I know the CMOS Sensors are different, but want to know if its compatiblie as its MIPI interface( I am just thinking like a USB Camera of any make works on Linux) Please confirm if I can use this Camera as is or need to modify any drivers, if yes then any suggestions on modifications. Thanks & Regards Sameer