• Content Count

  • Joined

  • Last visited

About SeanS

  • Rank

Recent Profile Visitors

The recent visitors block is disabled and is not being shown to other users.

  1. The schematic shows that a differential pair constraint was added (two red eye looking probe thingies). I should have looked here sooner. But a colleague mentioned that the constraint may not have been used in the layout. Do you know the person who laid out the board? Perhaps he can confirm the 100 ohm line to line impedance?
  2. Hello, I have a Genesys 2 board and was wondering if there is 100 ohm line to line controlled impedance routing for differential pairs that go to the HA, HB, and LA banks on the FMC connector. -Sean
  3. SeanS

    Genesys2 Echo Server Demo

    I have found Vivado 15.4 installed on our servers and have regenerated the block diagram to match what is in the tutorial.
  4. Hello, I am running Vivado 18.1 and would like to try to get the echo server running by following this demo. I understand that the demo hasn't been verified on Vivado 18.1, but nevertheless I would like to try it. The only problem is that my block diagram doesn't quite match what is displayed on the demo screen shots, even though I have double checked the steps to create it. Is there a bd tcl file available to recreate this diagram for the demo. If not, can a higher resolution picture of the completed diagram be posted?
  5. I did some research on and found this answer record: I had two floating inputs on my concatenation block and once I connected these project creation proceeded correctly.
  6. Hello, I was following the instructions here to build the echo_server example project, but project creation failed in step 11 with the following SDK Log: I am running Vivado 2018.2 and have upgraded all IP to their most recent versions. In Vivado, I have tried deleting the microblaze_0_axi_intc interrupt controller and re-instantiating it, making sure to have Vivado Auto-assign the address, but once I try creating the project again in SDK the
  7. I am using the Genesys 2 board and I have added the mig.prj core file to the Vivado project. However, when I run synthesis and implementation, check timing reports the DDR3_dqs_p[*] pins as having no input delay with a critical warning level of 'high'. I realize the mig.prj is supposed to have the timing constraints embedded in it. What should I do about this critical warning? -Sean
  8. SeanS

    Genesys 2 DDR Constraints

    Hi JColvin, I am definitely not using ISE. I think JPeyron had it correctly. I didn't have my board.Repopaths variable set and so the project wasn't finding the board files. Once I set this variable as suggested, the pin mapping and IO types were auto populated as expected. Kudos, Sean
  9. SeanS

    Genesys 2 DDR Constraints

    I have a follow up question. I read through the solution for the Arty board but I couldn't find a way to add the mig.prj file to a new scratch project. I attempted to instantiate a mig_7series_0 instance in my project, followed by a configuration of it by double clicking the block. When prompted, I entered the path to the mig.prj file I downloaded from the git repository. Unfortunately, it doesn't look like the tool found the Bank Number, Byte Number, Pin Number, IO Stadard and VCCAUX PD values in the prj file. The dialog lists the signal names, but not the remaining parameters.
  10. SeanS

    Genesys 2 DDR Constraints

    Thanks for the info! That explains it perfectly. -Sean
  11. Hello, I am working with the Genesys 2 FPGA board and I have downloaded the master xdc constraints from here: But there doesn't appear to be any constraints for the DDR3. I downloaded the Out of the Box demo and in the Genesys2_H.xdc file there appears the following note: #_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_- #  For DDR constraints please refer to our website #_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_- Where can I find the pin, lev
  12. Hello, The Genesys 2 board reference manual on Table 4 lists the max clock rate as ~900MHz and the max data rate as 1800MT/s 1) I looked at the Genesys-2-DMA project to get a handle on how the MIG is configured. Examining the datasheet.txt file in the ip folder for the MIG seems to indicate that the AXI bus width is 256 bits. Design Clock Frequency : 2500 ps ( 0.00 MHz) <====400MHz Phy to Controller Clock Ratio : 4:1 Input Clock Period : 5000 ps <====200MHz Does this mean the AXI interface transfers 256bits, singl