SeanS

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  1. I am using the Genesys 2 board and I have added the mig.prj core file to the Vivado project. However, when I run synthesis and implementation, check timing reports the DDR3_dqs_p[*] pins as having no input delay with a critical warning level of 'high'. I realize the mig.prj is supposed to have the timing constraints embedded in it. What should I do about this critical warning? -Sean
  2. SeanS

    Genesys 2 DDR Constraints

    Hi JColvin, I am definitely not using ISE. I think JPeyron had it correctly. I didn't have my board.Repopaths variable set and so the project wasn't finding the board files. Once I set this variable as suggested, the pin mapping and IO types were auto populated as expected. Kudos, Sean
  3. SeanS

    Genesys 2 DDR Constraints

    I have a follow up question. I read through the solution for the Arty board but I couldn't find a way to add the mig.prj file to a new scratch project. I attempted to instantiate a mig_7series_0 instance in my project, followed by a configuration of it by double clicking the block. When prompted, I entered the path to the mig.prj file I downloaded from the git repository. Unfortunately, it doesn't look like the tool found the Bank Number, Byte Number, Pin Number, IO Stadard and VCCAUX PD values in the prj file. The dialog lists the signal names, but not the remaining parameters. Is there something obvious I am missing here? Is there a preferred way to add existing IP to a project?
  4. SeanS

    Genesys 2 DDR Constraints

    Thanks for the info! That explains it perfectly. -Sean
  5. SeanS

    Genesys 2 DDR Constraints

    Hello, I am working with the Genesys 2 FPGA board and I have downloaded the master xdc constraints from here: https://github.com/Digilent/digilent-xdc/blob/master/Genesys-2-Master.xdc But there doesn't appear to be any constraints for the DDR3. I downloaded the Out of the Box demo and in the Genesys2_H.xdc file there appears the following note: #_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_- #  For DDR constraints please refer to our website #_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_- Where can I find the pin, level, and timing constraints for the DDR3 peripheral interface? -Sean
  6. Hello, The Genesys 2 board reference manual on Table 4 lists the max clock rate as ~900MHz and the max data rate as 1800MT/s 1) I looked at the Genesys-2-DMA project to get a handle on how the MIG is configured. Examining the datasheet.txt file in the ip folder for the MIG seems to indicate that the AXI bus width is 256 bits. Design Clock Frequency : 2500 ps ( 0.00 MHz) <====400MHz Phy to Controller Clock Ratio : 4:1 Input Clock Period : 5000 ps <====200MHz Does this mean the AXI interface transfers 256bits, single data rate, with a 200MHz clock? Thanks, Sean