• Content Count

  • Joined

  • Last visited

  1. Hello, I am trying to get the DMA-Audio demo working on the Nexys A7-100T. I have gotten the program to run on the board and the SW 261 Hz tone plays but not the HW tone. It says its generating the tone in HW but you can't hear anything. Also when trying to store a .WAV file for playback I am using the "Send File" command in TeraTerm, the monitor says "Header Received" and the file sends but then the program seems to lock up. The buttons no longer function and I have to re-launch the program to get it to do anything. I am using the 96kHz sample rate chirp tone found at: https://www.audiocheck.net/testtones_highdefinitionaudio.php. Is this an issue with the current build of the demo or am I doing something wrong? I have attached the TeraTerm output below. The only command that plays audio is the "Demo Generating 261 Hz tone in SW" Thanks for the help! update: Okay I was able to get past the Header received stage by uploading as binary but now it doesn't seem to be storing. It plays it back once after sending but won't replay it without uploading again.
  2. @jpeyron Worked great! Thanks a bunch!
  3. Hello, I am trying to get a digilent audio storage tutorial (https://github.com/Digilent/Nexys-A7-100T-DMA-Audio) that was written for Vivado 2018.2 to work on Vivado 2018.3. I am getting the following errors when trying to run synthesis: [Synth 8-448] named port connection 'PWM_AUDIO_0_en' does not exist for instance 'design_1_i' of module 'design_1' ["C:/FPGA/AudioTutorial/AudioTutorial.srcs/sources_1/imports/hdl/design_1_wrapper.v":174] [Synth 8-448] named port connection 'PWM_AUDIO_0_pwm' does not exist for instance 'design_1_i' of module 'design_1' ["C:/FPGA/AudioTutorial/AudioTutorial.srcs/sources_1/imports/hdl/design_1_wrapper.v":175] [Synth 8-6156] failed synthesizing module 'IOBUF' ["C:/Xilinx/Vivado/2018.3/scripts/rt/data/unisim_comp.v":23615] [Synth 8-6156] failed synthesizing module 'design_1_wrapper' ["C:/FPGA/AudioTutorial/AudioTutorial.srcs/sources_1/imports/hdl/design_1_wrapper.v":12] I think my issue is that the module fifo2audpwm_0 block has two outputs (aud_en and aud_pwm) that are not connected to anything in the block diagram and I am not sure where they are supposed to connect. Any help would be greatly appreciated. Thanks