Mukul

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  1. Mukul

    VGA on Zybo

    Hi @jpeyron I replaced the counter based clock divider with fractional clock divider, now my verilog code for VGA controller work fine. But i check for clicking wizard, zynq processor. Thanks for support
  2. Mukul

    VGA on Zybo

    Hi @jpeyron @artvvb I'm using zybo zynq -7000 board https://store.digilentinc.com/zybo-zynq-7000-arm-fpga-soc-trainer-board/ And design VGA controller (640*480@60Hz) on vivado 2018.2 using verilog. I determine the clock divider value as Clock_divider_value = (board_freq / 2*pixel_clock) - 1 I'm getting "out of range" error on monitor. By the mention formula my clock_divider value came to be 2.5 so i use 2 instead as my board freq is 125MHz. And 25MHz is pixel clock with given resolution. So I'm not able to calculate the pixel_clock/ clock_divider_value, hence getting out of range error Please help me in this
  3. Hello everyone

    I'm designing asynchronous FIFO using different styles and want to know how to do latency and throughput analysis of my design.

    I need to determine latency and throughput values for each design and don't know how to do so.

    1. D@n

      D@n

      I wrote about asynchronous FIFO's here.  Not sure if you already have that information or not.  The design I wrote about has a throughput equal to one value per the speed of the slower of the two clocks.  Latency is a bit more difficult to quantify.  You'll need to use some probability to do so.

      Dan

    2. Mukul

      Mukul

      Hi @D@n

      If throughput is one value per the speed of slower clock then it is same for all design, that is not true.

      I read somewhere that throughput is (frequency*input)/ latency.

      And same for latency, it should be different for every design.

       

       

  4. Hey @jpeyron Yes selecting the correct board file is the issue here. Now project work as expected. Thanks for your support Jon.
  5. Hi @jpeyron Probably this might be the error. Do visit the link https://forums.xilinx.com/t5/Embedded-Processor-System-Design/How-to-prevent-sleep-timer-from-being-set-to-axitimer/td-p/869998
  6. Hi @jpeyron I'm getting the same error again with your file. My fpga is programmed but when i press the button/switch, led didn't glow. And when i relaunch it, i get the "DAP status f0000021" error.
  7. I did so but getting the same error every time
  8. Hi jpeyron Yes im using Digilent board files. https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-getting-started-with-zynq/start
  9. Hi I'm new in this forum My question is can we determine the Power consumption in each state of FSM design separately.
  10. Hey jpeyron Yes my boot mode jumper is set to JTAG and I'm following the "getting started with zybo" site, still facing the error. I think the core selection is the issue but as i say i did exactly same as the site.https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-getting-started-with-zynq/start I attached all screen shot related to the error
  11. I'm using zybo 7z010clg400 board with vivado 2018.2 and having the same error... Couldn't find the solution yet.