neocsc

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  1. Like
    neocsc got a reaction from john_joe in Simple HDMI pass through with NexysVideo   
    Hi @jpeyron,
    Here is the screenshot of my design. I am also attaching the properties of clock wizard, dvi2rgb and rgb2div.
    Bellow is the xdc constraints:
    ## Clock Signal
    set_property -dict { PACKAGE_PIN R4    IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L13P_T2_MRCC_34 Sch=sysclk
    create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
    ## HDMI in
    #set_property -dict { PACKAGE_PIN AA5   IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_cec }]; #IO_L10P_T1_34 Sch=hdmi_rx_cec
    set_property -dict { PACKAGE_PIN W4    IOSTANDARD TMDS_33    } [get_ports { TMDS_IN_clk_n }]; #IO_L12N_T1_MRCC_34 Sch=hdmi_rx_clk_n
    set_property -dict { PACKAGE_PIN V4    IOSTANDARD TMDS_33     } [get_ports { TMDS_IN_clk_p }]; #IO_L12P_T1_MRCC_34 Sch=hdmi_rx_clk_p
    create_clock -period 6.734 -waveform {0 3.367} [get_ports { TMDS_IN_clk_p }];
    #set_property -dict { PACKAGE_PIN AB12  IOSTANDARD LVCMOS25 } [get_ports { hdmi_rx_hpa }]; #IO_L7N_T1_13 Sch=hdmi_rx_hpa
    set_property -dict { PACKAGE_PIN Y4    IOSTANDARD LVCMOS33 } [get_ports { DDC_scl_io }]; #IO_L11P_T1_SRCC_34 Sch=hdmi_rx_scl
    set_property -dict { PACKAGE_PIN AB5   IOSTANDARD LVCMOS33 } [get_ports { DDC_sda_io }]; #IO_L10N_T1_34 Sch=hdmi_rx_sda
    #set_property -dict { PACKAGE_PIN R3    IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_txen }]; #IO_L3P_T0_DQS_34 Sch=hdmi_rx_txen
    set_property -dict { PACKAGE_PIN AA3   IOSTANDARD TMDS_33     } [get_ports { TMDS_IN_data_n[0] }]; #IO_L9N_T1_DQS_34 Sch=hdmi_rx_n[0]
    set_property -dict { PACKAGE_PIN Y3    IOSTANDARD TMDS_33     } [get_ports { TMDS_IN_data_p[0]  }]; #IO_L9P_T1_DQS_34 Sch=hdmi_rx_p[0]
    set_property -dict { PACKAGE_PIN Y2    IOSTANDARD TMDS_33     } [get_ports { TMDS_IN_data_n[1]  }]; #IO_L4N_T0_34 Sch=hdmi_rx_n[1]
    set_property -dict { PACKAGE_PIN W2    IOSTANDARD TMDS_33     } [get_ports { TMDS_IN_data_p[1] }]; #IO_L4P_T0_34 Sch=hdmi_rx_p[1]
    set_property -dict { PACKAGE_PIN V2    IOSTANDARD TMDS_33     } [get_ports { TMDS_IN_data_n[2]  }]; #IO_L2N_T0_34 Sch=hdmi_rx_n[2]
    set_property -dict { PACKAGE_PIN U2    IOSTANDARD TMDS_33     } [get_ports { TMDS_IN_data_p[2] }]; #IO_L2P_T0_34 Sch=hdmi_rx_p[2]

    ## HDMI out
    #set_property -dict { PACKAGE_PIN AA4   IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_cec }]; #IO_L11N_T1_SRCC_34 Sch=hdmi_tx_cec
    set_property -dict { PACKAGE_PIN U1    IOSTANDARD TMDS_33     } [get_ports { TMDS_OUT_clk_n }]; #IO_L1N_T0_34 Sch=hdmi_tx_clk_n
    set_property -dict { PACKAGE_PIN T1    IOSTANDARD TMDS_33     } [get_ports { TMDS_OUT_clk_p  }]; #IO_L1P_T0_34 Sch=hdmi_tx_clk_p
    set_property -dict { PACKAGE_PIN AB13  IOSTANDARD LVCMOS25 } [get_ports { hdmi_tx_hpd }]; #IO_L3N_T0_DQS_13 Sch=hdmi_tx_hpd
    set_property -dict { PACKAGE_PIN U3    IOSTANDARD LVCMOS33 } [get_ports { DDC_scl_io }]; #IO_L6P_T0_34 Sch=hdmi_tx_rscl
    set_property -dict { PACKAGE_PIN V3    IOSTANDARD LVCMOS33 } [get_ports { DDC_sda_io }]; #IO_L6N_T0_VREF_34 Sch=hdmi_tx_rsda
    set_property -dict { PACKAGE_PIN Y1    IOSTANDARD TMDS_33     } [get_ports {TMDS_OUT_data_n[0] }]; #IO_L5N_T0_34 Sch=hdmi_tx_n[0]
    set_property -dict { PACKAGE_PIN W1    IOSTANDARD TMDS_33     } [get_ports { TMDS_OUT_data_p[0]  }]; #IO_L5P_T0_34 Sch=hdmi_tx_p[0]
    set_property -dict { PACKAGE_PIN AB1   IOSTANDARD TMDS_33     } [get_ports { TMDS_OUT_data_n[1] }]; #IO_L7N_T1_34 Sch=hdmi_tx_n[1]
    set_property -dict { PACKAGE_PIN AA1   IOSTANDARD TMDS_33     } [get_ports { TMDS_OUT_data_p[1] }]; #IO_L7P_T1_34 Sch=hdmi_tx_p[1]
    set_property -dict { PACKAGE_PIN AB2   IOSTANDARD TMDS_33     } [get_ports { TMDS_OUT_data_n[2]  }]; #IO_L8N_T1_34 Sch=hdmi_tx_n[2]
    set_property -dict { PACKAGE_PIN AB3   IOSTANDARD TMDS_33     } [get_ports { TMDS_OUT_data_p[2] }]; #IO_L8P_T1_34 Sch=hdmi_tx_p[2]

    ## Configuration options, can be used for all designs
    set_property CONFIG_VOLTAGE 3.3 [current_design]
    set_property CFGBVS VCCO [current_design]
    #---------------------------------------------------------------------------------
     
    I am able to generate the bitstream but no signal is detected by the HDMI display. I got stuck in this project. I have seen some threads where they say that one hot plug should be added (I added on at hdmi_tx_hpd) but it did not work.
     
    Could you please help me?
    Thank you





  2. Like
    neocsc reacted to jpeyron in Simple HDMI pass through with NexysVideo   
    Hi @neocsc,
    Here is a verified Nexys Video HDMI project updated from Vivado 2016.4 to Vivado 2017.4. You should be able to find the updated project in the proj folder .  Here is a GitHub project done in HDL using the clocking wizard, DVI2RGB and RGB2DVI IP Cores for another FPGA.  Here is a unverified Nexys Video Vivado 2017.4 HDMI pass through project made from the linked Github project. In the next few days I should have the bandwidth to verify this project.
    thank you,
    Jon
  3. Like
    neocsc reacted to kwilber in Simple HDMI pass through with NexysVideo   
    Here is an archive for the zybo z7 version of a 720p hdmi pass thru I did for someone a few days ago. You should be able to unzip it, open it in vivado and examine it.
  4. Like
    neocsc reacted to kwilber in Simple HDMI pass through with NexysVideo   
    Unfortunately, I do not have a NexysVideo board available. I have run the simple hdmi pass thru on both zybo and arty boards.
    Have you tried using a resolution of 720p yet? I find it useful to start with the lower frequencies first. Most sources and monitors have no trouble working with that.
  5. Like
    neocsc reacted to jpeyron in Simple HDMI pass through with NexysVideo   
    Hi @neocsc,
    I believe you should be using the hdmi_rx_hpa from the master xdc for the Nexys Video here.
    #set_property -dict { PACKAGE_PIN AB12 IOSTANDARD LVCMOS25 } [get_ports { hdmi_rx_hpa }]; #IO_L7N_T1_13 Sch=hdmi_rx_hpa
    thank you,
    Jon
  6. Like
    neocsc reacted to jpeyron in Simple HDMI pass through with NexysVideo   
    Hi Dnappier, 
    The clk wizard and the DVI2rgb both use a mmcm but they are on the same bank (bank 34). So to fix this issue you will need to open the clk_wiz_0 and select clocking options and select pll instead of mmcm. I have attached a fixed project of your design.  
    thank you, 
    Jon
    simple_project_esc.zip
  7. Like
    neocsc reacted to jpeyron in Simple HDMI pass through with NexysVideo   
    Hi @neocsc,
    Please attach a screen shot of the error.  Not all timing errors will break a project. 
    1) Are you still able to generate a bitstream or does the timing error force the bitstream generation to stop?
    2) If you are able to generate a bitstream please export the hardware(include bitstream), launch sdk and import application. Then program the fpga and run as ->launch on hardware(system debugger). 
    3) If so does the project make a serial terminal menu?
    $) If so does the project generate a HDMI pass through along with a pre-generated image?
    thank you,
    Jon
  8. Like
    neocsc reacted to kwilber in Simple HDMI pass through with NexysVideo   
    The hot plug detect should be on the rx side. The source will see that and will then initiate the DDC conversation.