neocsc

Members
  • Content Count

    15
  • Joined

  • Last visited

Everything posted by neocsc

  1. Hi @jpeyron, thank you very much for this. I was able to run the HDMI video but when I try to get the pass-through mode there is only a black screen. I was also able to do a simple pass-through video with no critical warnings or errors but still no signal is detected. My configuration is as follows: ASUS laptop is sourcing the HDMI in to the FPGA and one iiyama monitor is being used to display. I did test with different resolutions several projects but only the default bitstream from the FPGA is working properly.
  2. Hi @kwilber, I was able to compile with no errors or critical warnings the project but it just display no signal detected on the monitor. I also tried 720p and it has the same behavior of 1080p (no signal, just a black screen). I will further analyze your project. Thank you.
  3. Hi @jpeyron and @kwilber, still did not work. Could you please provide one working project for me to test? It is over one week and I am still unable to generate one simple pass-through buffer. Thank you
  4. Hi @kwilber, I could not find the hdmi_rx_hpd in the NexysVideo.xdc constraint file. Could you please let me know the name of the pin? Thank you
  5. Hi @jpeyron, Here is the screenshot of my design. I am also attaching the properties of clock wizard, dvi2rgb and rgb2div. Bellow is the xdc constraints: ## Clock Signal set_property -dict { PACKAGE_PIN R4 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L13P_T2_MRCC_34 Sch=sysclk create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk] ## HDMI in #set_property -dict { PACKAGE_PIN AA5 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_cec }]; #IO_L10P_T1_34 Sch=hdmi_rx_cec set_property -dict { PACKAGE_PIN W4 IOSTANDARD TMDS_33 } [get_ports { TMDS_IN_clk_n }]; #IO_L12N_T1_MRCC_34 Sch=hdmi_rx_clk_n set_property -dict { PACKAGE_PIN V4 IOSTANDARD TMDS_33 } [get_ports { TMDS_IN_clk_p }]; #IO_L12P_T1_MRCC_34 Sch=hdmi_rx_clk_p create_clock -period 6.734 -waveform {0 3.367} [get_ports { TMDS_IN_clk_p }]; #set_property -dict { PACKAGE_PIN AB12 IOSTANDARD LVCMOS25 } [get_ports { hdmi_rx_hpa }]; #IO_L7N_T1_13 Sch=hdmi_rx_hpa set_property -dict { PACKAGE_PIN Y4 IOSTANDARD LVCMOS33 } [get_ports { DDC_scl_io }]; #IO_L11P_T1_SRCC_34 Sch=hdmi_rx_scl set_property -dict { PACKAGE_PIN AB5 IOSTANDARD LVCMOS33 } [get_ports { DDC_sda_io }]; #IO_L10N_T1_34 Sch=hdmi_rx_sda #set_property -dict { PACKAGE_PIN R3 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_txen }]; #IO_L3P_T0_DQS_34 Sch=hdmi_rx_txen set_property -dict { PACKAGE_PIN AA3 IOSTANDARD TMDS_33 } [get_ports { TMDS_IN_data_n[0] }]; #IO_L9N_T1_DQS_34 Sch=hdmi_rx_n[0] set_property -dict { PACKAGE_PIN Y3 IOSTANDARD TMDS_33 } [get_ports { TMDS_IN_data_p[0] }]; #IO_L9P_T1_DQS_34 Sch=hdmi_rx_p[0] set_property -dict { PACKAGE_PIN Y2 IOSTANDARD TMDS_33 } [get_ports { TMDS_IN_data_n[1] }]; #IO_L4N_T0_34 Sch=hdmi_rx_n[1] set_property -dict { PACKAGE_PIN W2 IOSTANDARD TMDS_33 } [get_ports { TMDS_IN_data_p[1] }]; #IO_L4P_T0_34 Sch=hdmi_rx_p[1] set_property -dict { PACKAGE_PIN V2 IOSTANDARD TMDS_33 } [get_ports { TMDS_IN_data_n[2] }]; #IO_L2N_T0_34 Sch=hdmi_rx_n[2] set_property -dict { PACKAGE_PIN U2 IOSTANDARD TMDS_33 } [get_ports { TMDS_IN_data_p[2] }]; #IO_L2P_T0_34 Sch=hdmi_rx_p[2] ## HDMI out #set_property -dict { PACKAGE_PIN AA4 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_cec }]; #IO_L11N_T1_SRCC_34 Sch=hdmi_tx_cec set_property -dict { PACKAGE_PIN U1 IOSTANDARD TMDS_33 } [get_ports { TMDS_OUT_clk_n }]; #IO_L1N_T0_34 Sch=hdmi_tx_clk_n set_property -dict { PACKAGE_PIN T1 IOSTANDARD TMDS_33 } [get_ports { TMDS_OUT_clk_p }]; #IO_L1P_T0_34 Sch=hdmi_tx_clk_p set_property -dict { PACKAGE_PIN AB13 IOSTANDARD LVCMOS25 } [get_ports { hdmi_tx_hpd }]; #IO_L3N_T0_DQS_13 Sch=hdmi_tx_hpd set_property -dict { PACKAGE_PIN U3 IOSTANDARD LVCMOS33 } [get_ports { DDC_scl_io }]; #IO_L6P_T0_34 Sch=hdmi_tx_rscl set_property -dict { PACKAGE_PIN V3 IOSTANDARD LVCMOS33 } [get_ports { DDC_sda_io }]; #IO_L6N_T0_VREF_34 Sch=hdmi_tx_rsda set_property -dict { PACKAGE_PIN Y1 IOSTANDARD TMDS_33 } [get_ports {TMDS_OUT_data_n[0] }]; #IO_L5N_T0_34 Sch=hdmi_tx_n[0] set_property -dict { PACKAGE_PIN W1 IOSTANDARD TMDS_33 } [get_ports { TMDS_OUT_data_p[0] }]; #IO_L5P_T0_34 Sch=hdmi_tx_p[0] set_property -dict { PACKAGE_PIN AB1 IOSTANDARD TMDS_33 } [get_ports { TMDS_OUT_data_n[1] }]; #IO_L7N_T1_34 Sch=hdmi_tx_n[1] set_property -dict { PACKAGE_PIN AA1 IOSTANDARD TMDS_33 } [get_ports { TMDS_OUT_data_p[1] }]; #IO_L7P_T1_34 Sch=hdmi_tx_p[1] set_property -dict { PACKAGE_PIN AB2 IOSTANDARD TMDS_33 } [get_ports { TMDS_OUT_data_n[2] }]; #IO_L8N_T1_34 Sch=hdmi_tx_n[2] set_property -dict { PACKAGE_PIN AB3 IOSTANDARD TMDS_33 } [get_ports { TMDS_OUT_data_p[2] }]; #IO_L8P_T1_34 Sch=hdmi_tx_p[2] ## Configuration options, can be used for all designs set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design] #--------------------------------------------------------------------------------- I am able to generate the bitstream but no signal is detected by the HDMI display. I got stuck in this project. I have seen some threads where they say that one hot plug should be added (I added on at hdmi_tx_hpd) but it did not work. Could you please help me? Thank you
  6. Hi @jpeyron, I tried to use your fixed example in Vivado 2017.4 but I am getting the following error: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations. Could you please help? Thank you
  7. Hi Jon, thank you very much for the reply. I have tested the user demo in the following way: one HDMI cable from PC to HDMI in in the FPGA (J9) and another HDMI cable from HDMI out (J8). The internally generated pattern works fine but I am not able to get the pass-through buffer. Is there a sign for damage in the HDMI port on the FPGA or should I use another cable instead of HDMI to HDMI? Thank you.
  8. Hi Jon, thank you for the reply. Regarding your points: 1. Yes, they were connected properly. 2. I am not pretty sure if there is any damage to the HDMI ports in and out. The first time I connected the cables the FPGA was turned off, but the monitor might be on. Thank you.
  9. Hi Jon, thank you for the reply. Actually, the HDMI project works fine for functions 1-5. The screenshot in my previous comment is related to function 7 in the uart menu. It does not input the HDMI in, just a strange pattern. I tried to reset it a couple of times and before of getting that image I got a blank image (when selecting function 8 it turned onto black). I checked that the HDMI cables are working (at least to output the video to the monitor). Thank you
  10. Thank you jpeyron. All the best.
  11. Hi, I am also getting the same problem. I am able to change the resolution of the screen and reproduce the frame patters but when trying to input the HDMI in I get a strange screen as can be seen in the photo (I was expecting to see the desktop instead). When I connect back the HDMI from the computer to monitor everything works fine. Any clue? Thank you
  12. Hi jpeyron, I just would like to tell you that I was able to run the SDK and the board in running the code. The solutions was installing the ia32-libs (apt-get install ia32-libs). Thank you
  13. Dear jpeyron, thank you again for the reply. I have tested a blinking led using the device and the cables are working properly. I tried to install Adept 2 and when I type the command djtgcfg enum the command is not found. After exporting the project again to SDK I got the following errors: 18:12:23 ERROR : (XSDB Server)ERROR: [Hsi 55-1545] Problem running tcl command ::sw_standalone_v6_1::post_generate : couldn't execute "mb-ar": no such file or directory while executing "exec $archiver -d $libgloss_a _interrupt_handler.o" (procedure "::sw_standalone_v6_1::post_generate" line 18) invoked from within "::sw_standalone_v6_1::post_generate standalone" ERROR: [Hsi 55-1443] Error(s) while running TCL procedure post_generate() 18:12:23 ERROR : (XSDB Server)ERROR: [Hsi 55-1450] Error: running generate_bsp. 18:12:23 ERROR : Failed in generating sources I am still trying but have no idea how to fix these issues. I do appreciate your help. Thank you
  14. Hi jpeyron, thank you for the reply. After proceeding as you mentioned this is the screenshot that I got in SDK. And t he JP4 is in the mode according to the picture enclosed here. There are errors in videodemo and videodemo_bsp folders. Thank you.
  15. Hi jpeyron, I just started using the Nexys Video with Vivado 2017.4 on Linux Mint inside a Virtual Machine and I was able to generate the bitstream following your steps. However, when I try to program the device there is a message ""There are no debug cores" and the device cannot be programmed. I tried to refresh the device but nothing happens. I have no idea what is going on. Could you please help me? Thank you.