Kris Persyn

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Kris Persyn last won the day on April 15

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  1. Dear community, I accidently shorted the 3v3 pin of the JC PMOD on my zybo z7 020. Is there any hope to get it back to life? Kg, Kris
  2. Kris Persyn

    Stuck in SDK

    Hi @Notarobot, Oh that's a standard uart AXI IP core (Uartlite) I wan't to use for my project. I connected the TX and RX to the PMOD outputs. It has nothing to do with xil_printf right?
  3. Kris Persyn

    Stuck in SDK

    Hi @Notarobot , Thanks for your reply. This is a 'known path' to me. I've used this template during schoolprojects on a zybo z7-10. Configuration of interrupts on hardware level is done by activating fabric interrupts. On software level I use ScuGicInterrupt_Init to correctly map them to a certain IR routine function. I'm not sure what you are trying to point out with this.
  4. Kris Persyn

    Stuck in SDK

    @jpeyron @Ciprian Any ideas?
  5. Kris Persyn

    Stuck in SDK

    Hi, I'm stuck in SDK. I want to control my hardware design through the use of IP cores, but can't seem to get my software to run properly. I cant even xil_printf nor light some LEDs on my Zybo z20. Any suggestions? head.h helloworld.c
  6. @vicentiu My bad!
  7. @vicentiu I'm using the Zynq-7000 AP SoC..
  8. Hi, I'm stuck in SDK. I want to control visuals by manipulating an hdmi out design, but can't seem to get my software to run properly. I cant even xil_printf nor light some LEDs on my Zybo z20. Any suggestions? head.h helloworld.c
  9. Kris Persyn

    SDK issue

    Hi, I'm using a zyb z7-020 and have made a block design with PS and PL elements. However when I export my hardware (w bitstream) and try to create a new project SDK makes an incomplete project folder? Any ideas about what could cause this? For another project I basically did the same steps and it produces no errors..
  10. Hello all who are reading this. I managed to get it working with this timing block. Constraints files can be found in the repository. Enjoy.
  11. Timing sequence should be fine now (feel free to test out with this testbench). I've taken a look at the synthesized design and found something odd. For some reason these output signals are tied to ground (as if they weren't used..). There are other warnings as well which I found rather bizar.
  12. In the meantime I've found some errors in my timing module code. I will update as soon as I've rectified them.
  13. Hi there, I designed a small module that's supposed to feed timing signals into the rgb2dvi block provided by digilent. The code I wrote which produces this can be found here. The connections required in the block design can be seen below in the picture. The I/O planning is shown as well. I'm not getting any HDMI out of it. I checked the testbench and it produced the correct sequence of outputs. (When the VDE signal is high the screen uses the color rgb_in) Can anyone test this on his board or notice any flaws? If you run this on a zybo z7-20: To create the required clock signal use clock wizard (input 125 MHz clock on pin k17 and produce 148.5 MHz to the timing module) Thanks a lot in advance.
  14. I was able to solve it by selecting 'global' when generating output products. Other solutions are mentioned here (https://forums.xilinx.com/t5/Implementation/Drc-23-20-Rule-violation-REQP-1712-Input-clock-driver/td-p/586641)
  15. Hi @elodg, Now I'm getting this error. I think I've configured the clocking wizard wrongly?