Display image using VGA from block RAM in FPGA Posted February 20, 2019 Thank you very much @[email protected] ! Your website is rich with guidelines and tips. Following your advice, I changed the way I divide my clock. I used a PLL from the Vivado (Clocking Wizard) to generate 25 MHz clock from 100 MHZ clock. Before doing that, I had performed test bench for my top module, but all output signals were appearing to be (undefined). Using the PLL, The test bench runs fine now! I found out what where the problem was. I was resetting the BRAM address at a wrong point in the code. Which lead to a repeated display of the first row of the image only. Now the image appears like this: As seen, it's close to the original image but skewed for some reason. So far I am very happy with the result and hopefully will try to know the reason of such skew.