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Everything posted by khaledismail

  1. Thank you very much @[email protected] ! Your website is rich with guidelines and tips. Following your advice, I changed the way I divide my clock. I used a PLL from the Vivado (Clocking Wizard) to generate 25 MHz clock from 100 MHZ clock. Before doing that, I had performed test bench for my top module, but all output signals were appearing to be (undefined). Using the PLL, The test bench runs fine now! I found out what where the problem was. I was resetting the BRAM address at a wrong point in the code. Which lead to a repeated display of the first row of the image only. Now the image appears lik
  2. Hi everyone, I am trying to display image pixels stored in block RAM .coe file though VGA on the board BASYS 3. Description of what I have done so far, Passed this image to MATLAB to create a .coe file: The image is a 300*300 pixels. The .coe file stores each pixel RGB data scanning from left to right horizontally then moves to the second row, imitating how the VGA code scans the screen. So the .coe file is 300 pixel* 300 pixel=90000 lines long where each line is 12 bits, Red=4 bits followed by Green=4 bits followed by Blue=4 bits. This is a VHDL code to display