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  1. Thank you. I will also post my queries on Xilinx but if you know anything, please do let me know.
  2. Hi, I have been trying to implement Partial Reconfiguration of AES on Zedboard. I wanted to ask if i have netlist with me, can i use that netlist as one of my Partially reconfigured module? My second question is that if i create a block design having AXI interconnect, my IP and Processor, is it possible that i only declare my own IP as partially reconfigurable module? Any help would be highly appreciated. Thank you
  3. yes, i have already tried all the steps, i have checked the device on all the frequencies given (reduction of cable speed) but i could not succeed. My .xdc file also has IOSTANDARD and PACKAGE_PIN assigned to all the pins but still it did not help me program by device without error. Can you please suggest me anything else that i might be doing wrong?
  4. Hi, its me again with a new issue I tried to do all the previously discussed steps and i successfully generated the bit stream. I verified everything using simulations and then implemented the design to generate bitstream. After that i moved to hardware implementation. I am using Zedboard to implement my algorithm and vivado standalone programmer 2018.3 for programming. Whenever i try to program my device, i fail. I get the following error: Labtools-27-3165-End-of-startup-status-LOW hardware shutdown In order to solve this issue, i tried many steps like reinstalling the drivers, changing the USB cable etc. I also wrote simple programs like NAND gate just to make sure if my board is working fine or not. I was able to program the board successfully (NAND gate implementation) but not the actual AES128 which i intend to implement. Any help in this regard will be appreciated. Thanks in advance.
  5. Hi, I have generated the bitstream successfully and now going to test it on actual board. Thank you for your help @zygot and @jpeyron I have one more query to resolve if you may please guide me a little. While running the simulations, i have encountered few errors. It says: [XSIM 43-4287] "/Testbench/aes_tb_vpi.v" Line 126. Undefined system task '$init', I have tried to solve this error using include file search options but i am unable to resolve it. There are several more errors of same type as well. I have also tried to define this task separately but till now no success. I would appreciate any guideline on it. Thanks in advance.
  6. @zygot Thank you for your reply. You are right i am new to it. As you said that one should first try to recreate the project and verify results, i tried to do the same. But the problem was that i could not select the same board that was used in thr project, as it is a very old board and in vivado, the option was not given to select that one. It is always wise to reproduce results and move forward, i had no choice but to choose a new board and start. Porting HDL sources is not an issue, trying to see the bitstream of an old version and new is an issue.
  7. Thank you for your reply. I got the benchmark code from this link, they have used a different FPGA board (sparten 3e xc3s500e-4ft256) for the project but I am using zedboard part number xc7z020clg4841 for my project. The problem is, whenever i try to synthesize and implement the code in vivado, it show no errors, But when i generate bitstream, several errors occur in implementation stage as shown in the last post. After searching through net, i concluded that my xdc or constraint file is missing but as you said that vivado optimizes the pins even if it is missing then it is again an issue for me. I think the problem is with clocking or pin selection but I am unable to correct it. Would really appreciate some guidelines.
  8. Hello, I have been working on a benchmark code of AES128 for few days. When I import the project in vivado, synthesis and implementation run fine, but when i generate bitstream, i get error in implementation. I am using zedboard xc7z020clg484-1 I get the following error in my log. --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:32 ; elapsed = 00:00:34 . Memory (MB): peak = 1819.996 ; gain = 352.055 ; free physical = 75883 ; free virtual = 95116 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 4 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:32 ; elapsed = 00:00:34 . Memory (MB): peak = 1819.996 ; gain = 352.055 ; free physical = 75886 ; free virtual = 95119 Synthesis Optimization Complete : Time (s): cpu = 00:00:32 ; elapsed = 00:00:34 . Memory (MB): peak = 1820.000 ; gain = 352.055 ; free physical = 75897 ; free virtual = 95130 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 8 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1894.148 ; gain = 0.000 ; free physical = 75796 ; free virtual = 95029 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Common 17-83] Releasing license: Synthesis 70 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:37 ; elapsed = 00:00:40 . Memory (MB): peak = 1894.148 ; gain = 426.207 ; free physical = 75847 ; free virtual = 95080 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1894.148 ; gain = 0.000 ; free physical = 75847 ; free virtual = 95080 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. INFO: [Common 17-1381] The checkpoint '/home/s2256800/AES128/AES128.runs/synth_1/aes_ip.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file aes_ip_utilization_synth.rpt -pb aes_ip_utilization_synth.pb INFO: [Common 17-206] Exiting Vivado at Fri Feb 15 11:50:46 2019... Please help me where i got wrong. Thanks in advance.