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  1. Thank you. I will also post my queries on Xilinx but if you know anything, please do let me know.
  2. Hi, I have been trying to implement Partial Reconfiguration of AES on Zedboard. I wanted to ask if i have netlist with me, can i use that netlist as one of my Partially reconfigured module? My second question is that if i create a block design having AXI interconnect, my IP and Processor, is it possible that i only declare my own IP as partially reconfigurable module? Any help would be highly appreciated. Thank you
  3. yes, i have already tried all the steps, i have checked the device on all the frequencies given (reduction of cable speed) but i could not succeed. My .xdc file also has IOSTANDARD and PACKAGE_PIN assigned to all the pins but still it did not help me program by device without error. Can you please suggest me anything else that i might be doing wrong?
  4. Hi, its me again with a new issue I tried to do all the previously discussed steps and i successfully generated the bit stream. I verified everything using simulations and then implemented the design to generate bitstream. After that i moved to hardware implementation. I am using Zedboard to implement my algorithm and vivado standalone programmer 2018.3 for programming. Whenever i try to program my device, i fail. I get the following error: Labtools-27-3165-End-of-startup-status-LOW hardware shutdown In order to solve this issue, i tried many steps like reinstalling the d
  5. Hi, I have generated the bitstream successfully and now going to test it on actual board. Thank you for your help @zygot and @jpeyron I have one more query to resolve if you may please guide me a little. While running the simulations, i have encountered few errors. It says: [XSIM 43-4287] "/Testbench/aes_tb_vpi.v" Line 126. Undefined system task '$init', I have tried to solve this error using include file search options b
  6. @zygot Thank you for your reply. You are right i am new to it. As you said that one should first try to recreate the project and verify results, i tried to do the same. But the problem was that i could not select the same board that was used in thr project, as it is a very old board and in vivado, the option was not given to select that one. It is always wise to reproduce results and move forward, i had no choice but to choose a new board and start. Porting HDL sources is not an issue, trying to see the bitstream of an old version and new is an issue.
  7. Thank you for your reply. I got the benchmark code from this link, they have used a different FPGA board (sparten 3e xc3s500e-4ft256) for the project but I am using zedboard part number xc7z020clg4841 for my project. The problem is, whenever i try to synthesize and implement the code in vivado, it show no errors, But when i generate bitstream, several errors occur in implementation stage as shown in the last post. After searching through net, i concluded that my xdc or constraint file is missing but as you said that vivado optimizes the pins even if i
  8. Hello, I have been working on a benchmark code of AES128 for few days. When I import the project in vivado, synthesis and implementation run fine, but when i generate bitstream, i get error in implementation. I am using zedboard xc7z020clg484-1 I get the following error in my log. --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:32 ; elapsed = 00:00:34 . Memory (MB): peak = 1819.996 ; gain = 352.055 ; free physical = 75883 ; free virtual = 95116 ---------------------------------------