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  1. I'm sorry my fault. I erased the question was just for attention. type rom_type is array (0 to 7) of std_logic_vector(7 downto 0); -- This is type. Also this is not a quiz question. The following code is quoted from pog chu's book. The code I shared in my first post is a different spelling of pong chu's code and it works. I am wondering how it works. I've never seen such syntax before. rom_data <= BALL_ROM(to_integer(rom_addr)); rom_bit <= rom_data(to_integer(rom_co1));
  2. askhunter

    A question about vhdl.

    Hi, can anyone explain this syntax? rom_bit <= xxx(to_integer(rom_addr))(to_integer(rom_col)); constant xxx: rom_type := ( "00111100", -- **** "01111110", -- ****** "11111111", -- ******** "11111111", -- ******** "11111111", -- ******** "11111111", -- ******** "01111110", -- ****** "00111100" -- **** ); signal rom_addr, rom_col: unsigned(0 to 2); signal rom_bit: std_logic; rom_bit <= xxx(to_integer(rom_addr))(to_integer(rom_col));
  3. I get the same error again. Also the clock wizard uses pll.
  4. askhunter

    hdmi ip clocking error

    Hi,I got this error. The old version also didn't have such a problem (I think 2016). I'll be happy if you can help me. note: board Arty z7 20 ## This file is a general .xdc for the ARTY Z7-20 Rev.B ## To use it in a project: ## - uncomment the lines corresponding to used pins ## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project ## Clock Signal set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { sys_clock }]; #IO_L13P_T2_MRCC_35 Sch=SYSCLK create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { sys_clock }]; ##Buttons set_property -dict { PACKAGE_PIN D19 IOSTANDARD LVCMOS33 } [get_ports { rst }]; #IO_L4P_T0_35 Sch=btn[0] set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { led0 }]; #IO_L6N_T0_VREF_34 Sch=LED0 set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { led1 }]; #IO_L6P_T0_34 Sch=LED1 set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { led2 }]; #IO_L21N_T3_DQS_AD14N_35 Sch=LED2 set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { led3 }]; #IO_L23P_T3_35 Sch=LED3 ##HDMI RX Signals #set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_cec }]; #IO_L13N_T2_MRCC_35 Sch=HDMI_RX_CEC set_property -dict { PACKAGE_PIN P19 IOSTANDARD TMDS_33 } [get_ports { TMDS_clk_n }]; #IO_L13N_T2_MRCC_34 Sch=HDMI_RX_CLK_N set_property -dict { PACKAGE_PIN N18 IOSTANDARD TMDS_33 } [get_ports { TMDS_clk_p }]; #IO_L13P_T2_MRCC_34 Sch=HDMI_RX_CLK_P set_property -dict { PACKAGE_PIN W20 IOSTANDARD TMDS_33 } [get_ports { TMDS_data_n[0]}]; #IO_L16N_T2_34 Sch=HDMI_RX_D0_N set_property -dict { PACKAGE_PIN V20 IOSTANDARD TMDS_33 } [get_ports { TMDS_data_p[0]}]; #IO_L16P_T2_34 Sch=HDMI_RX_D0_P set_property -dict { PACKAGE_PIN U20 IOSTANDARD TMDS_33 } [get_ports { TMDS_data_n[1]}]; #IO_L15N_T2_DQS_34 Sch=HDMI_RX_D1_N set_property -dict { PACKAGE_PIN T20 IOSTANDARD TMDS_33 } [get_ports { TMDS_data_p[1]}]; #IO_L15P_T2_DQS_34 Sch=HDMI_RX_D1_P set_property -dict { PACKAGE_PIN P20 IOSTANDARD TMDS_33 } [get_ports { TMDS_data_n[2]}]; #IO_L14N_T2_SRCC_34 Sch=HDMI_RX_D2_N set_property -dict { PACKAGE_PIN N20 IOSTANDARD TMDS_33 } [get_ports { TMDS_data_p[2]}]; #IO_L14P_T2_SRCC_34 Sch=HDMI_RX_D2_P set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_in_hpd}]; #IO_25_34 Sch=HDMI_RX_HPD set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { DDC_scl_io }]; #IO_L11P_T1_SRCC_34 Sch=HDMI_RX_SCL set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { DDC_sda_io }]; #IO_L11N_T1_SRCC_34 Sch=HDMI_RX_SDA ##HDMI TX Signals #set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_cec }]; #IO_L19N_T3_VREF_35 Sch=HDMI_TX_CEC set_property -dict { PACKAGE_PIN L17 IOSTANDARD TMDS_33 } [get_ports { TMDS_1_clk_n }]; #IO_L11N_T1_SRCC_35 Sch=HDMI_TX_CLK_N set_property -dict { PACKAGE_PIN L16 IOSTANDARD TMDS_33 } [get_ports { TMDS_1_clk_p }]; #IO_L11P_T1_SRCC_35 Sch=HDMI_TX_CLK_P set_property -dict { PACKAGE_PIN K18 IOSTANDARD TMDS_33 } [get_ports { TMDS_1_data_n[0] }]; #IO_L12N_T1_MRCC_35 Sch=HDMI_TX_D0_N set_property -dict { PACKAGE_PIN K17 IOSTANDARD TMDS_33 } [get_ports { TMDS_1_data_p[0] }]; #IO_L12P_T1_MRCC_35 Sch=HDMI_TX_D0_P set_property -dict { PACKAGE_PIN J19 IOSTANDARD TMDS_33 } [get_ports { TMDS_1_data_n[1] }]; #IO_L10N_T1_AD11N_35 Sch=HDMI_TX_D1_N set_property -dict { PACKAGE_PIN K19 IOSTANDARD TMDS_33 } [get_ports { TMDS_1_data_p[1] }]; #IO_L10P_T1_AD11P_35 Sch=HDMI_TX_D1_P set_property -dict { PACKAGE_PIN H18 IOSTANDARD TMDS_33 } [get_ports { TMDS_1_data_n[2] }]; #IO_L14N_T2_AD4N_SRCC_35 Sch=HDMI_TX_D2_N set_property -dict { PACKAGE_PIN J18 IOSTANDARD TMDS_33 } [get_ports { TMDS_1_data_p[2] }]; #IO_L14P_T2_AD4P_SRCC_35 Sch=HDMI_TX_D2_P
  5. thank you. I did what you said now it works. may i ask you what is the mandatory files that need to be included for the DVI2RGB IP Core to work.?
  6. Hi, When İ try to" make external" to the TMDS port it give me this warning and nothing happen(that is, it does not create an "external port".). what is the cause of this error?
  7. these two photos maybe a little more revealing about my problem.
  8. Hi, I design a module for rgbtogrey. When i start post implementation timing simulation,I get the following result.(gryodata) Everything was seamless until post implementation timing simulation, but here I came across something like this. I would be very happy if someone could help me with this subject. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.types.all; entity rgb2grey is Port ( clk : in std_logic; active_i : in std_logic; active_o : out std_logic; rgb_in : in std_logic_vector(23 downto 0); gry_o : out std_logic_vector(7 downto 0) ); end rgb2grey; architecture Behavioral of rgb2grey is signal active,active2,active3,active4: std_logic:='0'; --signal temp_gry,temp_gry2,temp_gry3,temp_gry4 : std_logic_vector(7 downto 0):=(others=>'0'); signal temp_gry,temp_gry2,temp_gry3,temp_gry4,tempy_reg,temp_son : integer:=0; --temp_gry<= std_logic_vector(to_unsigned((to_integer(unsigned(rgb_in(7 downto 0))) + to_integer(unsigned(rgb_in(15 downto 8))) + to_integer(unsigned(rgb_in(23 downto 16))))/3,8)); BEGIN process(clk) begin if rising_edge(clk) then if active_i='1' then temp_gry<= to_integer(unsigned(rgb_in(7 downto 0)))/3; temp_gry2<=to_integer(unsigned(rgb_in(15 downto 8)))/3; temp_gry3<=to_integer(unsigned(rgb_in(23 downto 16)))/3; active<='1'; else active<='0'; end if; temp_gry4<=temp_gry+temp_gry2; tempy_reg<=temp_gry3; temp_son<=temp_gry4+tempy_reg; gry_o<=std_logic_vector(to_unsigned(temp_son,8)); active2<=active; active3<=active2; active4<=active3; end if; end process; -- gry_o<=temp_gry3; active_o<=active4; end Behavioral;
  9. thank you for interesting. Actually, I read this documentation but this has so many detail and i'am very newbie in fpga. so i didn't understand mostly. even so I'll read it again.
  10. first : without dsp attribute - attribute use_dsp of sum : signal is "no"; second image : with dsp attribute - attribute use_dsp of sum : signal is "yes";
  11. Hi, I try to simple multiplication, but when i use dsp attribute then i got different result in simulation .what is the reason of this? without dsp attribute - attribute use_dsp of sum : signal is "no"; with dsp attribute - attribute use_dsp of sum : signal is "yes"; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.types.all; entity convolution2d is port ( clk, rst : in std_logic; start : in std_logic; window : in frame9; done : out std_logic; pixel : out pixel8 ); end convolution2d; architecture rtl of convolution2d is constant mask : mask_9 := (-1, -1, -1, -1, 8, -1, -1, -1, -1); signal sum : integer:=0; attribute use_dsp : string; attribute use_dsp of sum : signal is "yes"; begin -- iterative way process(clk) is --variable tick : std_logic:='0'; begin done<='0'; if rising_edge(clk) then if start = '1' then sum <= 0; for n in 0 to 2 loop for k in 0 to 2 loop sum <= sum + (to_integer(unsigned(window(n*3 + k))) * mask(n*3 + k)); end loop; end loop; done<='1'; pixel <= std_logic_vector(to_unsigned(sum, 8)); end if; end if; end process; end rtl; "
  12. I did the "port mapping" manually. then I synthesized and gave no error. Does this mean that the "user defined" type , which i defined, will runs on the card without any problems?
  13. I'm trying to add module to the schematic I designed, but I got an error because of types.vhdl. I hope we can solve the problem. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; package types is subtype pixel8 is std_logic_vector(7 downto 0); type frame_type is array(natural range <>) of pixel8 subtype frame9 is frame_type(0 to 8); end types;
  14. Hello, I try to add my rtl design to block diagram, but my top.vhdl design is seeing incompatible. How can i solve this problem? Thank you.