askhunter

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  1. I'm sorry my fault. I erased the question mark.it was just for attention. type rom_type is array (0 to 7) of std_logic_vector(7 downto 0); -- This is type. Also this is not a quiz question. The following code is quoted from pog chu's book. The code I shared in my first post is a different spelling of pong chu's code and it works. I am wondering how it works. I've never seen such syntax before. rom_data <= BALL_ROM(to_integer(rom_addr)); rom_bit <= rom_data(to_integer(rom_co1));
  2. Hi, can anyone explain this syntax? rom_bit <= xxx(to_integer(rom_addr))(to_integer(rom_col)); constant xxx: rom_type := ( "00111100", -- **** "01111110", -- ****** "11111111", -- ******** "11111111", -- ******** "11111111", -- ******** "11111111", -- ******** "01111110", -- ****** "00111100" -- **** ); signal rom_addr, rom_col: unsigned(0 to 2); signal rom_bit: std_logic; rom_bit <= xxx(to_integer(rom_addr))(to_integer(rom_col));
  3. I get the same error again. Also the clock wizard uses pll.
  4. Hi,I got this error. The old version also didn't have such a problem (I think 2016). I'll be happy if you can help me. note: board Arty z7 20 ## This file is a general .xdc for the ARTY Z7-20 Rev.B ## To use it in a project: ## - uncomment the lines corresponding to used pins ## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project ## Clock Signal set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { sys_clock }]; #IO_L13P_T2_MRCC_35 Sch=SYSCLK create_clock -add -name sys_clk_pin -period 8.00 -waveform
  5. thank you. I did what you said now it works. may i ask you what is the mandatory files that need to be included for the DVI2RGB IP Core to work.?
  6. Hi, When İ try to" make external" to the TMDS port it give me this warning and nothing happen(that is, it does not create an "external port".). what is the cause of this error?
  7. these two photos maybe a little more revealing about my problem.
  8. Hi, I design a module for rgbtogrey. When i start post implementation timing simulation,I get the following result.(gryodata) Everything was seamless until post implementation timing simulation, but here I came across something like this. I would be very happy if someone could help me with this subject. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.types.all; entity rgb2grey is Port ( clk : in std_logic; active_i : in std_logic;
  9. thank you for interesting. Actually, I read this documentation but this has so many detail and i'am very newbie in fpga. so i didn't understand mostly. even so I'll read it again.
  10. first : without dsp attribute - attribute use_dsp of sum : signal is "no"; second image : with dsp attribute - attribute use_dsp of sum : signal is "yes";
  11. Hi, I try to simple multiplication, but when i use dsp attribute then i got different result in simulation .what is the reason of this? without dsp attribute - attribute use_dsp of sum : signal is "no"; with dsp attribute - attribute use_dsp of sum : signal is "yes"; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.types.all; entity convolution2d is port ( clk, rst : in std_logic; start : in std_logic; window : in frame9; done : out std_logic; pixel : out pixel8 ); end convolution
  12. I did the "port mapping" manually. then I synthesized and gave no error. Does this mean that the "user defined" type , which i defined, will runs on the card without any problems?
  13. I'm trying to add module to the schematic I designed, but I got an error because of types.vhdl. I hope we can solve the problem. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; package types is subtype pixel8 is std_logic_vector(7 downto 0); type frame_type is array(natural range <>) of pixel8 subtype frame9 is frame_type(0 to 8); end types;
  14. Hello, I try to add my rtl design to block diagram, but my top.vhdl design is seeing incompatible. How can i solve this problem? Thank you.