Sduru

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  1. Sduru

    PCAM OV5640 Power

    Hello All, Is the CMOS OV5640 on PCAM PCB powered up directly from Zybo Z7? Do we need a special SDK project to trigger the OV5640 on PCAM? Can it work normally with its defaults settings from a simple hello world SDK apps? I mean that I cannot get OV5640 streaming through MIPI CSI-2 into Vivado ILA core although it is supplied 3.3V through FFC cable normally (I physically measured it). As you can see in the attachment, I am getting "no streams" warning in the waveform window of HW manager. Does anyone has an idea about this? Could it be related to some hardware/component problem on OV5650 or somewhere else PCAM? Best regards Sami
  2. Sduru

    AXI4 and Vivado ILA

    Hello Jon, Thanks for your reply. The problem has been solved.
  3. Sduru

    Vivado sysnthesis fail..Pcam

    Hello Dear @elodg , @jpeyron , @Ciprian I've downloaded PCAM demo from the link here as elodg provided and I also installed the Vivado version of 2018.2. Everything went good, and generated bitstream normally. After I launched SDK and I run the application "pcam_vdma_hdmi" or "fsbl", I cannot capture the video from the sensor. I am getting the attached errors. There is no HDMI output, no streaming to ILA core, and no tera term connection. What may be the problem? My best regards
  4. Sduru

    AXI4 and Vivado ILA

    Hi @jpeyron I've made S_AXI_Lite input as 'external', and then solved the problem. Now, there is no any constraints issue at the moment, and the validation is OK that screenshot is attached. After the successful validation of my project, I started to synthesize it. But, at this time, I've got the error 'Submodule Runs Failed' . The error screen is attached. The error log: ERROR: [Synth 8-439] module 'design_1_MIPI_CSI_2_RX_1_0' not found --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 485.297 ; gain = 153.523 --------------------------------------------------------------------------------- RTL Elaboration failed INFO: [Common 17-83] Releasing license: Synthesis 5 Infos, 1 Warnings, 0 Critical Warnings and 2 Errors encountered. synth_design failed ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details INFO: [Common 17-206] Exiting Vivado at Wed May 8 13:18:21 2019... There is an explanation in the Xilinx link here . I've followed the steps, but I am not able to synthesize it. As a result, I still couldn't finish my project, and cannot see my PCAM digital signals on ILA... Cheers, Sami
  5. Sduru

    AXI4 and Vivado ILA

    Hello All @jpeyron @JColvin , Do I have to include all the ports definitions of the wrapper in the Constraints file? For example, there are some ports (resets, sys_clock etc.) which are not in the constraints like m_axis_video_0_tdata : out STD_LOGIC_VECTOR ( 39 downto 0 ); m_axis_video_0_tlast : out STD_LOGIC; m_axis_video_0_tready : in STD_LOGIC; m_axis_video_0_tuser : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axis_video_0_tvalid : out STD_LOGIC; reset_rtl : in STD_LOGIC; reset_rtl_0 : in STD_LOGIC; sys_clock : in STD_LOGIC Could it be the reason? Regards Sami
  6. Sduru

    AXI4 and Vivado ILA

    Hi Dear @jpeyron Please find the xdc and wrapper files from my project. I have corrected some of the port names in the xdc file and matched with the wrapper port names but still getting the same errors. From my observation, there is no any definition in the xdc file for the m_axis_video port from CSI-2 to ILA. Do you think that it maybe the reason? Many thanks.. Sami Wrapper.txt Constraints.txt
  7. Sduru

    AXI4 and Vivado ILA

    Hello Dear @jpeyron I have updated the Vivado library from the link you provided. Now, I am using the latest versions MIPI_D_PHY_RX_1 and MIPI_CSI_2_RX_1. I double checked that I've installed Digilent board files. I see it with the correct name as Zybo Z7-20 (xc7z020clg400-1) in my project summary. You can see my block design like in the attachment. (My simple aim is just to see digital image data in the output of MIPI CSI-2 captured from PCAM OV5640 CMOS). You can also see my constraints file in the attachment. I am just using that from the git hub link here At the end, I am getting the same errors attached when I validate it. Maybe I am doing a simple mistake related to connections and/or clocking / resetting etc. but I don't know. Cheers, Sami
  8. Sduru

    MIPI D-PHY and CSI-2

    Dear All, I am asking this question because I cannot generate bitstream for my project like in the following: I am using Zybo Z7 and PCAM OV5640 CMOS with Vivado 2018.3 version. I just wanna put ILA function and observe digital image data captured by MIPI CSI-2. But, I am getting the following errors: [Common 17-55] 'get_property' expects at least one object. Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. [BD 41-1273] Error running post_propagate TCL procedure: ERROR: [Common 17-55] 'get_property' expects at least one object. ::digilentinc.com_ip_MIPI_D_PHY_RX_1.3::post_propagate Line 6 Does any body know the root causes of this failure? Is it related to Vivado version, or Digilent MIPI IPs version or my block design? Many thanks.. Cheers..
  9. Sduru

    MIPI D-PHY and CSI-2

    Hi everyone, I am dealing with MIPI CSI-2 RX and D-PHY RX IPs which are open source IPs by Digilent. Where is the latest versions of those IPs? Is there new versions of those which are compatible with Vivado 2018.3? Many thanks...
  10. I am also interested in this kind of task. But I will be using AXI Stream and MIPI interfaces with a lot errors that I need to solve..
  11. Sduru

    AXI4 and Vivado ILA

    Thanks for your reply @zygot . As you said about the problem, I've checked the constraints names. I am using Zybo Z7 board and its constraints file in the link https://github.com/Digilent/digilent-xdc/blob/master/Zybo-Z7-Master.xdc . I realised that some of the port names of MIPI D-PHY IP are different from those in the constraints file. I've corrected all of them and toggled non-used pins like in the following: However, I am still getting the same errors. I will be very appreciated if we solve this problem... Many thanks...
  12. Sduru

    AXI4 and Vivado ILA

    In the link https://www.xilinx.com/support/answers/56169.html , it says that this error is related to XDC file. "The following are some common causes of this issue. XDC constraints are case sensitive. These warnings can occur if the case type of the object name in XDC is not the same as the signal in the RTL code" But in my constraints file, there is no case sensitive problem. I cannot solve the problem. Please help...
  13. Sduru

    AXI4 and Vivado ILA

    Thank you @zygot . I've created the block design without AXI4 Stream like in the following: But, I am getting the following errors: [Common 17-55] 'get_property' expects at least one object. Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. [BD 41-1273] Error running post_propagate TCL procedure: ERROR: [Common 17-55] 'get_property' expects at least one object. ::digilentinc.com_ip_MIPI_D_PHY_RX_1.3::post_propagate Line 6 Do you have any idea for those errors above?
  14. Sduru

    AXI4 and Vivado ILA

    Hello, My question is related to AXI4 usage in digital image processing. As I am new in image processing with HDL coding, I need to get this valuable answer from you @jpeyron @zygot @JColvin especially. I am using Zybo Z7 and PCAM 5C for my project. As a good start in my opinion, I wanna get digital image from CMOS through D-PHY and MIPI CSI-2 RX. And then, I just wanna scope the digital image bits by using Integrated Logic Analyzer (ILA). For this purpose, do I have to use AXI4 streaming and/or other AXI IPs in my VHDL design? In other words, can I pass the data from CSI-2 interface to ILA directly? If it is possible only with AXI interface, so I will deeply study the AXI4 referance manuals. Many thanks...
  15. Yes, you are right @kwilber Now there is no problem through Xilinx SDK