Sduru

Members
  • Content Count

    29
  • Joined

  • Last visited

About Sduru

  • Rank
    Member

Recent Profile Visitors

510 profile views
  1. Sduru

    PCAM OV5640 Power

    Hi @Ciprian I re-generated BSP sources, but the same errors like above still remain! The situation is the same: PCAM project code does not run and there is no menu on the console although it says it is connected to COM1. I am able to connect to COM1 with a simple hello world application and see the messages on the console over the same Vivado block design. Best regards...
  2. Sduru

    PCAM OV5640 Power

    Hello Dear @Ciprian I've put xil_printf("hello world\n"); command at the beginning of the main function like in the attached screenshot with no additional changing. But SDK gave some strange errors. The error codes are also attached. Moreover, I run the project, nothing has been changed: It says it is connected to COM1 and there is no menu on the console or any traffic on the ILA.
  3. Sduru

    PCAM OV5640 Power

    Hi @jpeyron Thank you very much. I am looking forward to your response. Best regards..
  4. Sduru

    PCAM OV5640 Power

    Hi Dear @jpeyron I am %100 sure that Zybo-Z7 is on COM1. For that I have attached the screenshot of this com1 showing Digilent USB adapter on COM1. In addition to this, I am able to program the Xilinx device on Zybo-Z7 by using the same micro USB port. I have hit the enter button on both of Tera Term and SDK terminal, but it didn't solve the problem. It is not transmitting HDMI output from HDMI TX to my monitor. Moreover, I bought a new PCAM 5C PCB to see if there is a component problem on it. But nothing changed.
  5. Sduru

    PCAM OV5640 Power

    Hello @jpeyron SDK Application window is attached. As you can see, it is Connected to COM1 at 115200. But there is no serial terminal menu. Block design is also attached. The only difference from your origiinal design is ila core (validated). And finally, this is the wrapper: library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity system_wrapper is port ( DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 ); DDR_cas_n : inout STD_LOGIC; DDR_ck_n : inout STD_LOGIC; DDR_ck_p : inout STD_LOGIC; DDR_cke : inout STD_LOGIC; DDR_cs_n : inout STD_LOGIC; DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 ); DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_odt : inout STD_LOGIC; DDR_ras_n : inout STD_LOGIC; DDR_reset_n : inout STD_LOGIC; DDR_we_n : inout STD_LOGIC; FIXED_IO_ddr_vrn : inout STD_LOGIC; FIXED_IO_ddr_vrp : inout STD_LOGIC; FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 ); FIXED_IO_ps_clk : inout STD_LOGIC; FIXED_IO_ps_porb : inout STD_LOGIC; FIXED_IO_ps_srstb : inout STD_LOGIC; cam_gpio_tri_io : inout STD_LOGIC_VECTOR ( 0 to 0 ); cam_iic_scl_io : inout STD_LOGIC; cam_iic_sda_io : inout STD_LOGIC; dphy_clk_lp_n : in STD_LOGIC; dphy_clk_lp_p : in STD_LOGIC; dphy_data_hs_n : in STD_LOGIC_VECTOR ( 1 downto 0 ); dphy_data_hs_p : in STD_LOGIC_VECTOR ( 1 downto 0 ); dphy_data_lp_n : in STD_LOGIC_VECTOR ( 1 downto 0 ); dphy_data_lp_p : in STD_LOGIC_VECTOR ( 1 downto 0 ); dphy_hs_clock_clk_n : in STD_LOGIC; dphy_hs_clock_clk_p : in STD_LOGIC; hdmi_tx_clk_n : out STD_LOGIC; hdmi_tx_clk_p : out STD_LOGIC; hdmi_tx_data_n : out STD_LOGIC_VECTOR ( 2 downto 0 ); hdmi_tx_data_p : out STD_LOGIC_VECTOR ( 2 downto 0 ) ); end system_wrapper; architecture STRUCTURE of system_wrapper is component system is port ( dphy_clk_lp_n : in STD_LOGIC; dphy_clk_lp_p : in STD_LOGIC; dphy_data_hs_n : in STD_LOGIC_VECTOR ( 1 downto 0 ); dphy_data_hs_p : in STD_LOGIC_VECTOR ( 1 downto 0 ); dphy_data_lp_n : in STD_LOGIC_VECTOR ( 1 downto 0 ); dphy_data_lp_p : in STD_LOGIC_VECTOR ( 1 downto 0 ); dphy_hs_clock_clk_p : in STD_LOGIC; dphy_hs_clock_clk_n : in STD_LOGIC; DDR_cas_n : inout STD_LOGIC; DDR_cke : inout STD_LOGIC; DDR_ck_n : inout STD_LOGIC; DDR_ck_p : inout STD_LOGIC; DDR_cs_n : inout STD_LOGIC; DDR_reset_n : inout STD_LOGIC; DDR_odt : inout STD_LOGIC; DDR_ras_n : inout STD_LOGIC; DDR_we_n : inout STD_LOGIC; DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 ); DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 ); DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 ); FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 ); FIXED_IO_ddr_vrn : inout STD_LOGIC; FIXED_IO_ddr_vrp : inout STD_LOGIC; FIXED_IO_ps_srstb : inout STD_LOGIC; FIXED_IO_ps_clk : inout STD_LOGIC; FIXED_IO_ps_porb : inout STD_LOGIC; cam_gpio_tri_i : in STD_LOGIC_VECTOR ( 0 to 0 ); cam_gpio_tri_o : out STD_LOGIC_VECTOR ( 0 to 0 ); cam_gpio_tri_t : out STD_LOGIC_VECTOR ( 0 to 0 ); cam_iic_sda_i : in STD_LOGIC; cam_iic_sda_o : out STD_LOGIC; cam_iic_sda_t : out STD_LOGIC; cam_iic_scl_i : in STD_LOGIC; cam_iic_scl_o : out STD_LOGIC; cam_iic_scl_t : out STD_LOGIC; hdmi_tx_clk_p : out STD_LOGIC; hdmi_tx_clk_n : out STD_LOGIC; hdmi_tx_data_p : out STD_LOGIC_VECTOR ( 2 downto 0 ); hdmi_tx_data_n : out STD_LOGIC_VECTOR ( 2 downto 0 ) ); end component system; component IOBUF is port ( I : in STD_LOGIC; O : out STD_LOGIC; T : in STD_LOGIC; IO : inout STD_LOGIC ); end component IOBUF; signal cam_gpio_tri_i_0 : STD_LOGIC_VECTOR ( 0 to 0 ); signal cam_gpio_tri_io_0 : STD_LOGIC_VECTOR ( 0 to 0 ); signal cam_gpio_tri_o_0 : STD_LOGIC_VECTOR ( 0 to 0 ); signal cam_gpio_tri_t_0 : STD_LOGIC_VECTOR ( 0 to 0 ); signal cam_iic_scl_i : STD_LOGIC; signal cam_iic_scl_o : STD_LOGIC; signal cam_iic_scl_t : STD_LOGIC; signal cam_iic_sda_i : STD_LOGIC; signal cam_iic_sda_o : STD_LOGIC; signal cam_iic_sda_t : STD_LOGIC; begin cam_gpio_tri_iobuf_0: component IOBUF port map ( I => cam_gpio_tri_o_0(0), IO => cam_gpio_tri_io(0), O => cam_gpio_tri_i_0(0), T => cam_gpio_tri_t_0(0) ); cam_iic_scl_iobuf: component IOBUF port map ( I => cam_iic_scl_o, IO => cam_iic_scl_io, O => cam_iic_scl_i, T => cam_iic_scl_t ); cam_iic_sda_iobuf: component IOBUF port map ( I => cam_iic_sda_o, IO => cam_iic_sda_io, O => cam_iic_sda_i, T => cam_iic_sda_t ); system_i: component system port map ( DDR_addr(14 downto 0) => DDR_addr(14 downto 0), DDR_ba(2 downto 0) => DDR_ba(2 downto 0), DDR_cas_n => DDR_cas_n, DDR_ck_n => DDR_ck_n, DDR_ck_p => DDR_ck_p, DDR_cke => DDR_cke, DDR_cs_n => DDR_cs_n, DDR_dm(3 downto 0) => DDR_dm(3 downto 0), DDR_dq(31 downto 0) => DDR_dq(31 downto 0), DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0), DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0), DDR_odt => DDR_odt, DDR_ras_n => DDR_ras_n, DDR_reset_n => DDR_reset_n, DDR_we_n => DDR_we_n, FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn, FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp, FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0), FIXED_IO_ps_clk => FIXED_IO_ps_clk, FIXED_IO_ps_porb => FIXED_IO_ps_porb, FIXED_IO_ps_srstb => FIXED_IO_ps_srstb, cam_gpio_tri_i(0) => cam_gpio_tri_i_0(0), cam_gpio_tri_o(0) => cam_gpio_tri_o_0(0), cam_gpio_tri_t(0) => cam_gpio_tri_t_0(0), cam_iic_scl_i => cam_iic_scl_i, cam_iic_scl_o => cam_iic_scl_o, cam_iic_scl_t => cam_iic_scl_t, cam_iic_sda_i => cam_iic_sda_i, cam_iic_sda_o => cam_iic_sda_o, cam_iic_sda_t => cam_iic_sda_t, dphy_clk_lp_n => dphy_clk_lp_n, dphy_clk_lp_p => dphy_clk_lp_p, dphy_data_hs_n(1 downto 0) => dphy_data_hs_n(1 downto 0), dphy_data_hs_p(1 downto 0) => dphy_data_hs_p(1 downto 0), dphy_data_lp_n(1 downto 0) => dphy_data_lp_n(1 downto 0), dphy_data_lp_p(1 downto 0) => dphy_data_lp_p(1 downto 0), dphy_hs_clock_clk_n => dphy_hs_clock_clk_n, dphy_hs_clock_clk_p => dphy_hs_clock_clk_p, hdmi_tx_clk_n => hdmi_tx_clk_n, hdmi_tx_clk_p => hdmi_tx_clk_p, hdmi_tx_data_n(2 downto 0) => hdmi_tx_data_n(2 downto 0), hdmi_tx_data_p(2 downto 0) => hdmi_tx_data_p(2 downto 0) ); end STRUCTURE;
  6. Sduru

    PCAM OV5640 Power

    Hi @jpeyron 1. I am using Zybo Z7-20 and Vivado 2018.2 2. I have generated bitstream normally with the updated version of Pcam application. I have imported sdk project with no problem and no error! 3. I am using Windows 10 and tera term. Com-port is also currect. 4. I have just added an ila core to the block desing, and validated succussfully. I didnt make any other change. I am sorry but I am not able to share my screenshots at the moment. I can do it later but I summarized the situation above correctly. Thanks
  7. Sduru

    PCAM OV5640 Power

    Hi @jpeyron No, this is a different issue. I don't get any error, but also I don't get camera streaming! Additionally, I can't get application options (change resolution or fps etc) in the terminal although everything seems OK. There is no hdmi output and no streaming into ila core of hw manager. If I Apply a hello world application, I am just getting hello world message in the Sdk terminal with no error! I am not sure if it is a cmos hardware problem or a software problem.
  8. Sduru

    Vivado sysnthesis fail..Pcam

    Hello Dear @jpeyron I've already solved the problem. It was related to selecting wrong language C instead of C++ when creating new application project. PCAM project was written in C++, but I wrongly selected C! After I corrected that mistake, now there is no any linking error. Thanks...
  9. Sduru

    PCAM OV5640 Power

    Hello All, Is the CMOS OV5640 on PCAM PCB powered up directly from Zybo Z7? Do we need a special SDK project to trigger the OV5640 on PCAM? Can it work normally with its defaults settings from a simple hello world SDK apps? I mean that I cannot get OV5640 streaming through MIPI CSI-2 into Vivado ILA core although it is supplied 3.3V through FFC cable normally (I physically measured it). As you can see in the attachment, I am getting "no streams" warning in the waveform window of HW manager. Does anyone has an idea about this? Could it be related to some hardware/component problem on OV5650 or somewhere else PCAM? Best regards Sami
  10. Sduru

    AXI4 and Vivado ILA

    Hello Jon, Thanks for your reply. The problem has been solved.
  11. Sduru

    Vivado sysnthesis fail..Pcam

    Hello Dear @elodg , @jpeyron , @Ciprian I've downloaded PCAM demo from the link here as elodg provided and I also installed the Vivado version of 2018.2. Everything went good, and generated bitstream normally. After I launched SDK and I run the application "pcam_vdma_hdmi" or "fsbl", I cannot capture the video from the sensor. I am getting the attached errors. There is no HDMI output, no streaming to ILA core, and no tera term connection. What may be the problem? My best regards
  12. Sduru

    AXI4 and Vivado ILA

    Hi @jpeyron I've made S_AXI_Lite input as 'external', and then solved the problem. Now, there is no any constraints issue at the moment, and the validation is OK that screenshot is attached. After the successful validation of my project, I started to synthesize it. But, at this time, I've got the error 'Submodule Runs Failed' . The error screen is attached. The error log: ERROR: [Synth 8-439] module 'design_1_MIPI_CSI_2_RX_1_0' not found --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 485.297 ; gain = 153.523 --------------------------------------------------------------------------------- RTL Elaboration failed INFO: [Common 17-83] Releasing license: Synthesis 5 Infos, 1 Warnings, 0 Critical Warnings and 2 Errors encountered. synth_design failed ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details INFO: [Common 17-206] Exiting Vivado at Wed May 8 13:18:21 2019... There is an explanation in the Xilinx link here . I've followed the steps, but I am not able to synthesize it. As a result, I still couldn't finish my project, and cannot see my PCAM digital signals on ILA... Cheers, Sami
  13. Sduru

    AXI4 and Vivado ILA

    Hello All @jpeyron @JColvin , Do I have to include all the ports definitions of the wrapper in the Constraints file? For example, there are some ports (resets, sys_clock etc.) which are not in the constraints like m_axis_video_0_tdata : out STD_LOGIC_VECTOR ( 39 downto 0 ); m_axis_video_0_tlast : out STD_LOGIC; m_axis_video_0_tready : in STD_LOGIC; m_axis_video_0_tuser : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axis_video_0_tvalid : out STD_LOGIC; reset_rtl : in STD_LOGIC; reset_rtl_0 : in STD_LOGIC; sys_clock : in STD_LOGIC Could it be the reason? Regards Sami
  14. Sduru

    AXI4 and Vivado ILA

    Hi Dear @jpeyron Please find the xdc and wrapper files from my project. I have corrected some of the port names in the xdc file and matched with the wrapper port names but still getting the same errors. From my observation, there is no any definition in the xdc file for the m_axis_video port from CSI-2 to ILA. Do you think that it maybe the reason? Many thanks.. Sami Wrapper.txt Constraints.txt
  15. Sduru

    AXI4 and Vivado ILA

    Hello Dear @jpeyron I have updated the Vivado library from the link you provided. Now, I am using the latest versions MIPI_D_PHY_RX_1 and MIPI_CSI_2_RX_1. I double checked that I've installed Digilent board files. I see it with the correct name as Zybo Z7-20 (xc7z020clg400-1) in my project summary. You can see my block design like in the attachment. (My simple aim is just to see digital image data in the output of MIPI CSI-2 captured from PCAM OV5640 CMOS). You can also see my constraints file in the attachment. I am just using that from the git hub link here At the end, I am getting the same errors attached when I validate it. Maybe I am doing a simple mistake related to connections and/or clocking / resetting etc. but I don't know. Cheers, Sami