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  1. Hi, I have a similar question but before I ask it I should explain my code that is attached below. I have developed a Discrete Fourier Transform (DFT) algorithm on a NEXYS 4 DDR board using Vivado 2018.3. The code takes an external clock signal of 10 MHz and generates 100 MHz, 200 MHz, and 10 MHz clocks synchronous to the external clock input. The 200 MHz clock is used for DFT analysis. The generated 10 MHz clock is fed into the ADC of a signal detector which converts a captured signal into a 12 bit digital data that is in turn being read into the FPGA code through 12 digital input. The D