DoctorWkt

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DoctorWkt last won the day on July 30 2015

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  1. Wow, many thanks for that Tommy. I'll download it and have a look. Cheers All, Warren
  2. Hi Tommy, sorry for the delay in writing, I've had other things that needed attention. Yes, I've tried putting the definitions of the pins in my top-level VHD file but I'm still getting the same warnings. I've looked at the looper demo and it seems to put the pin definitions in the top-level Verilog file (I don't know Verilog). Is there a VHDL example around that uses the SRAM2DDR component that I could look at? Anybody? Thanks all! Warren
  3. I've just tried Tommy's suggestion. I imported the "Ram2Ddr_RefComp/Source/Ram2DdrXadc_Ref_Comp/ram2ddrxadc.vhd" file into a new project. I then imported (as IP) the file "ddr.xco". I added a 200MHz clock. In the top-level project file, I created components "clk_200M" and "ram2ddrxadc", and I added port maps for both of them. But when I go to do Synthesis, I get exactly the same SLEW warning that I got when I used the MIG generator. This time the warning is for the same lines, but these are for a constraints file that was imported with the "ddr.xco" IP. So now I'm stuck! What am I doing wrong? There must be a missing step that I'm not following. James, if you read this, can you pass it up to the folk that wrote the SRAM2DDR component for comment? Thanks all! Warren
  4. Thanks for the feedback James. Each axis of the Apple 2 joystick is a potentiometer which, together with a capacitor, forms an RC circuit that is the input to a 555 one-shot timer. When a program wants to read the position of the axis, it toggles a memory location that triggers the 555 timer. This causes the 555 output to go high initially; then the output goes low after a time delay based on the value of the potentiometer on that axis. The program then loops reading the 555 output, counting the number of cycles before the output goes low. When the output goes low, the counter holds the positional value of that axis. Because I don't want to modify the timer sampling code in the Apple 2 ROM, I need to build the same type of one-shot timer circuit into the joystick :-) Cheers, Warren
  5. Now that I've got Stephen Edwards' Apple2 FPGA project working, I want to build a joystick for it. The original Apple 2 joystick was two potentiometers connected to a NE556 timer (on the Apple 2 motherboard), plus two pushbuttons. Attached is the original schematic. What I want to do is to find an old analog joystick, put the 556 timer into the joystick itself (I'll probably need a TS3V556 3.3V version), and interface this to a Pmod port. I'll need these seven lines: gnd, Vcc, two digital pushbutton inputs, two digital joystick inputs, one digital output to trigger the timer. Does this sound feasible? I assume the Pmod lines are bidirectional, so I'd need to declare them inout in VHDL. Is there anything else I should consider? P.S If I buy a 6pos 2row 2.54mm header from someone like Element14, this will plug into a Pmod socket OK? Many thanks for feedback, Warren
  6. Thanks for the suggestions, Tommy. I actually found a different path but now I'm stuck elsewhere. I found the MIG files for the DDR component in the resource center. I've been able to import these and create a component called mig_7series_0. I've also imported the ram2ddrxadc.vhd file, also from the resource center. I modified this file so that it uses the "mig_7series_0" component and not the "ddr" component (I didn't set the DDR name up when I generated it). I have instantiated the ram2ddrxadc component in my top-level file, along with a port map. Ditto a 200MHz clock. Synthesis runs OK. However, when I run Implementation, I get these critical errors: [Netlist 29-160] Cannot set property 'SLEW', because the property does not exist for objects of type 'pin'. ["/home/wkt/Vivado/Ram2DDR/ Ram2DDR.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/constraints/ mig_7series_0.xdc":33] Looking at that xdc file, it looks like the pin mapping for the FPGA to the DDR chips. Can anybody explain why the xdc file is causing these errors? Line 33 and friends say: # PadFunction: IO_L23P_T3_34 set_property SLEW FAST [get_ports {ddr2_dq[0]}] set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr2_dq[0]}] set_property IOSTANDARD SSTL18_II [get_ports {ddr2_dq[0]}] set_property PACKAGE_PIN R7 [get_ports {ddr2_dq[0]}] Now that I've seen Tommy's post, I'll also go and try that. I'll report back later! What I'm aiming to do here is to make a simple VHDL project that uses the SRAM2DDR component, along with a list of instructions as to how I built it from scratch. This will serve as a useful how-to guide for others who don't know how to use the SRAM2DDR component. Cheers & thanks for any feedback, Warren
  7. Here's a game of tic tac toe in VHDL for the Nexys4 DDR, written as a set of finite state machines and not as a computer running a program. The design is inspired from John F. Wakerly's tic tac toe code from his book "Digital Design: Principles and Practices", but I've completely rewritten it. The game logic is contained in the files TTTdefs.vhd, TwoInARow.vhd and game_logic.vhd. The rest of the code is there to interface with the user: to print strings to the user, to get digits and to control when moves are made. There are also two UART driver components. You should be able to set this up as a Vivado project by importing all the .vhd files and setting up the .xdc file as the constraints. When you run the bitstream, open up a 9600 bps serial connection to the Nexys4 DDR board and follow the instructions that you should see: Welcome to the computerless tic-tac-toe game. You get to make the first move. Please enter moves as digits from 1 to 9. What move would you like to make? Cheers, Warren (c) GPL3, 2015 tic_tac_toe.zip
  8. I've ported Stephen Edwards' Apple2FPGA project to the Nexys4 DDR board; attached below are the Nexys4-specific VHDL files and some instructions. It should also work on the non-DDR Nexys4, but you should use the constraints file for the non-DDR Nexys4 as I believe it has different pinouts to the I/O devices. Cheers, Warren nexys4_apple2_v1.2.tar.gz
  9. I'm about to play with the Nexys4 DDR "SRAM to DDR" component, but I've never used a MIG or a pre-existing netlist before. The instructions say "Components can either be inserted into a project as a pre-compiled netlist (.ngc), or as sources by copying the VHDL and MIG project files into your project." Can someone help me with an explanation on how to do this?! I'm using Vivado 2015.1. Thanks all! Warren
  10. This isn't a question, but a working project. I've ported Stephen Edwards' FPGA Apple ][+ project to work on the Nexys4 board. I'm not using the DDR RAM or the cellular RAM so it should work on the non-DDR board too. Attached are my extra files and instructions. Lots of fun! Cheers, Warren P.S Is there a better place to post useful information instead of questions? nexys4_apple2_v1.1.tar.gz
  11. OK, I should have read those slides by Erkay SavaƟ first. Attached is my first cut at a suitable SRAM model plus a simple testbench. Comments or suggestions gratefully accepted. Cheers, Warren ram2ddrxadc.vhd ram2ddrxadc_tb.vhd
  12. Could someone help me interpret the bus timing diagram on the SRAM2DDR wiki page? There are two timing parameters: tRC (read cycle time) = min 210 ns, and tWR (write cycle time) = min 260 ns. The read timing diagram shows valid data immediately after ram_cen and ram_oen go active low, and lasting for tRC. Does this mean that the read data is available immediately? I was expecting that there would be some delay. And, does it mean that the address value has to be asserted for at least tRC? Actually, now I'm even more confused because the valid data in the diagram is on ram_dq_i which is an input to the component. On the write timing diagram, ram_wen and ram_cen are enabled low and the address is kept valid for tWC. The ram_dq_i input data to the component isn't shown. The ram_dq_o output becomes valid at an indeterminate time after ram_wen. Also, there's no output on the SRAM side to let the user know when the read data is available and when the write has been successful. So, how does the user know when reads and writes are successful? I guess I'm still new to real hardware timing diagrams :-) Thanks in advance for any help, pointers to useful web sites. Cheers, Warren
  13. Thanks Hamster, I'll give it a go in the next few days. Warren
  14. Ah yes, but I want to simulate the SRAM in GHDL and/or Vivado so that I can see the waveforms and I can debug things before I take my design to hardware. I could modify an existing model such as this one: https://www.doulos.com/knowhow/vhdl_designers_guide/models/simple_ram_model/ , but I'm not sure how to model the timing delay. Can I just add a wait for tRC ns on a read operation, and wait for tWR ns on a write operation? Thanks, Warren
  15. DoctorWkt

    Modelling SRAM in VHDL

    Now that I've got one CPU working using block RAM, my next project is to design a CPU which uses the SRAM to DDR component on the Nexys4 DDR board. I'd like to do some behavioral and timing simulation of the SRAM first, using GHDL and Vivado. Is there a VHDL model for this SRAM, or can somebody point me at a model which I could adapt? I did look on the Digilent VHDL components page https://www.digilentinc.com/classroom/VHDLcomponents/ but I didn't see it there. I have found several SRAM models, but none seem to deal with the timing delay or the upper/lower byte input. Slightly off-topic (because it is not Digilent specific). I need to supply a 200MHz clock to the component. I'm guessing I use a Vivado clock wizard to make this. Thanks in advance for any suggestions, pointers. Warren