AlGee

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  1. Hi JColvin, Thanks for getting back to me on this. I'm feeling a bit embarrassed now because I got around this issue last weekend without updating this forum. Sorry about that. I have now made great strides with the Arty/Vivado and the MicroBlaze. My project does not need the MicroBlaze so I'm doing everything with Verilog. I find Vivado very slow for checking Verilog code and have started using Icarus with GTKWave for debugging code and viewing wave-forms before loading into Vivado and onto the Arty-S7 Thanks again for your help, AlGee
  2. I did as Andrew suggested in his April 7th 2016 post. I was able to drag a Connector JA component into my block design but when I generate Bitstream I get this critical warning message: [IP_Flow 19-4965] IP pmod_bridge_0 was packaged with board value 'digilentinc.com:arty:part0:1.1'. Current project's board value is 'digilentinc.com:arty-s7-50:part0:1.0'. Please update the project settings to match the packaged IP. Any suggestions? Thanks Alistair
  3. Update: I have tried a Hello World tutorial through Vivado to SDK, compiled it and it works. My problems must therefor have originated from somewhere in the Vivado block diagram stage. Alistair
  4. Hi JColvin, In reply to your questions I reinstalled Vivado using 2019.1 and removed WinAVR from PATH and all environment variables still the same message?. Ran out of ideas so now trying to run Vivado under Ubuntu When compiling the 'c' code in the SDK I'm now getting: make: *** [zynq-gsg.elf] Error 1 recipe for target 'zynq-gsg.elf' failed Alistair
  5. Following this tutorial: https://reference.digilentinc.com/vivado/getting-started-with-ipi/start Get to step 7.6 Launch Vivado SDK - Name the new source file main.c, then click Finish then I get this pop-up: 'mb-gcc.exe - Application Error' The application was unable to start correctly (0xc0000142) I'm also getting the following in the bottom middle window of the SDK make: *** [subdir.mk:20: main.o] Error -1073741502 arty7 C/C++ Problem I found a similar post on this site from 2015 that suggested removing 'mingw' from my path. I've done this and still get the pop-up error I'm guessing the gcc is not installed correctly but what do I do? Any ideas out there?
  6. Thanks everyone. I've tried a few things out I got an error with the Tools > Launch Vitis menu option in Vivado. I reinstalled Vitis with no luck, installed 2019.1 - no luck so uninstalled all Xilinx stuff and deleted the Xilinx directory. I then installed 2018.3 and now have the 'File drop-down select Launch SDK' option. I'm now able to continue with the tutorial - problem solved. Thanks again, Alistair
  7. Please can anyone help me? Following this tutorial: https://reference.digilentinc.com/vivado/getting-started-with-ipi/start I get stuck at step 6. Launch Vivado SDK I've successfully done: Tutorial: "In the File drop-down, select Export then Export Hardware" ... I don't have 'launch SDK' option: Tutorial: "Just below Export in the File drop-down, select Launch SDK." No launch SDK anywhere? Tried: 'launch_sdk' from Tcl window but got this: WARNING: [Common 17-210] 'launch_sdk' is deprecated. INFO: [Vivado 12-393] Launching SDK... INFO: [Vivado 12-417] Running xsdk ERROR: [Common 17-70] Application Exception: Not found in path: xsdk I'm totally stuck? I'm running Vivado 2019.2
  8. Before anyone spends time on the last problem it is now solved Started up Administrator: Windows PowerShell, navigated to here: C:\Xilinx\Vivado\2018.2\data\xicom\cable_drivers\nt64 and entered this: install_drivers_wrapper.bat I now have a serial port connected to the Arty Success, kwilber's demo has uploaded and is doing things with the LEDs on the Arty. Time for a celebration cup of tea
  9. Now having problems with the Arty A7-35T's serial port Tried reinstalling, re-booting and tried this that I found online: C:\Xilinx\Vivado\2018.2\data\xicom\cable_drivers\nt64\digilent\install_digilent.exe All to no avail. The serial port was working Monday when I first powered up the card and ran the built in tests
  10. "And it contains one line: 'set_param board.repoPaths For some reason I can't past the full line in here? after repoPaths there is an open bracket the list "C:/Xilinx-work/vivado-boards/new/board_files"then a close bracket
  11. OK, I'll stick with Windows. I've followed the instructions that kwilber suggested... but still no luck I now have Vivado 2018.2 installed and working Board Files here: 'C:\Xilinx-work\vivado-boards\new\board_files' I've put 'Vivado_init.tcl' here: 'C:/Xilinx/Vivado' And it contains one line: 'set_param board.repoPaths ' I get as far as 'choose the target device'... but the Arty is not in the list?
  12. Hi Jpeyron or whoever can help, Might be best if I delete everything and start again. A few days ago I received a brand new Digilent ARTY Artix-7 35T Evaluation Kit (and tools voucher) What version of Vivado should I install? What tutorial Example Projects will work with it? Any suggestions ideas to get it do do something will be greatly appreciated, I have a dual boot PC with Windows 10 or Ubuntu 14.04 AlGee
  13. Hi Jpeyron Thank you for the reply. I'm following the tutorial on: https://reference.digilentinc.com/learn/programmable-logic/tutorials/github-demos/start I'm using Vivado 2018.3 - tutorial states: Vivado 2016.4 is used in this tutorial - is this a show stopper? I've now downloaded and installed Arty board files from here: https://reference.digilentinc.com/reference/software/vivado/board-files?redirect=1 and put them here: C:\Xilinx\Vivado\2018.3\data\boards\board_files I now get a lot further as far as: ## create_root_design "" ERROR: [BD 5-390] IP definition not found for VLNV: xilinx.com:ip:clk_wiz:5.2 ERROR: [Common 17-39] 'create_bd_cell' failed due to earlier errors. while executing "create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 clk_wiz_1 " (procedure "create_root_design" line 113) I'll try some of the other tutorials - see if I make any progress.... invoked from within "create_root_design """ (file "../src/bd/system.tcl" line 898) while executing "source $origin_dir/src/bd/system.tcl" (file "./create_project.tcl" line 103) update_compile_order -fileset sources_1 set_property location {1 170 140} [get_bd_cells axi_mem_intercon] So I guess I have other stuff that is missing. I really didn't think it was going to be this difficult just to get started.
  14. Just bought an Arty and have followed Digilent Github Demo instructions and get this: ERROR: [Board 49-71] The board_part definition was not found for digilentinc.com:arty:part0:1.1. The project's board_part property was not set, but the project's part property was set to xc7a35ticsg324-1L. Any thoughts?