wilfredk

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  1. Hi, I am fairly new to the creation of IPs using Vivado HLS. For the current project that I am working on I have been tinkering with a Linux OS that I installed on ZYBO Zynq Z-7010 AP Soc. The board has a very modest resources and compared to other high end boards. I have installed Xillinux an operating system that makes it possible to communicated using device files that are located in /dev/ folder named as xillybus_read_* and xillybus_write_* . I have created an IP using Vivado HLS that would carry a 2D convolution. When I run the c_simulation through Vivado hls it gives me the desired output but when I run the same through a program created on the host OS that is supposed to communicate with the PL it does not return a desired output or anywhere near it. I am attaching the IP core file, testbench file created in Vivado HLS and the C++ program running on the PS for communicating with the IP. Thank you in advance. core.cpp tb_core.cpp coprocessing.cpp
  2. Hi, I have been trying to install OpenCV on Xillinux on the Zybo Zynq 7000 board but the installations halts at 76%. Can anyone help me regarding the installation on xillinux so I can use the feature od coprocessing with xillybus. Thank you in advance.
  3. I have created a simple Zynq Processing project in Vivado 2018 SDK, for which I want to write a simple software (Hello World Application). I generated the bitstream and then exported it to Vivado SDK. Which generated the BSP files. The MIO was configured with ETH port, USB Port, SD port, UART etc. I then created a simple program (Hello World) in c. Which added all of header and source file "helloWorld.c". I then configured the system debugger and then click on Run as >> Launch on Hardware (System Debugger). After running on the hardware I get the following error. Please help me regarding the following issue. And the final error message.