pierre antony

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  1. Last Friday, during a univeristy lab, I have seen problems with the MIG for Nexy4 DDR. Pn the student computer, there was a read only issue with te Vivado project during synthesis/implementation. They've had to manually set the directory in not read only mode while Vivado runs to solve the problem. It is not a good solution because it requires a manual intervention and one never know when to do it. Are you aware of this of problem? Regards, Pierre
  2. Thanks, in fact I was misisng the step where we have to run the tcl script to extract the project Now I can open the project
  3. Hello, There are several example projects available at this Digilent link: https://reference.digilentinc.com/reference/programmable-logic/nexys-4-ddr/start Unfortunatly when I download the content of these project, I don't find any Vivado xpr file nor bd file. For example, the git repository for project Nexys 4 DDR GPIO Demo at this link https://github.com/Digilent/Nexys-4-DDR-GPIO or in the zip file https://github.com/Digilent/Nexys-4-DDR-GPIO/releases/download/v2016.4-1/Nexys-4-DDR-GPIO-2016.4-1.zip doesn't include any xpr or bd file as far as I can tell. Maybe I didn't download the right files? How can I find the Vivado project for this examples please?
  4. My mistake, I had not taken the mig.prj up to date. Now I can generate a bitstream. Thanks for your support. I now move to the SDK part of the project
  5. Hello Jon, With C1 Nexys4 DDR, it is worse. I get an error message at step 8.3 of the tutorial: https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-4-ddr-getting-started-with-microblaze/start The attached picture shows the error message. The MIG is not even connected with the board file changes... Also no improvement when I try to synthesize the project you've sent to me. [Synth 8-439] module 'design_1_mig_7series_0_0' not found ["C:/Nexys/Nexys4DDR_Vivavo2015_4_ref/Nexys4DDR_Vivavo2015_4_.srcs/sources_1/bd/design_1/hdl/design_1.v":573] [Synth 8-285] failed synthesizing module 'design_1' ["C:/Nexys/Nexys4DDR_Vivavo2015_4_ref/Nexys4DDR_Vivavo2015_4_.srcs/sources_1/bd/design_1/hdl/design_1.v":13] [Synth 8-285] failed synthesizing module 'design_1_wrapper' ["C:/Nexys/Nexys4DDR_Vivavo2015_4_ref/Nexys4DDR_Vivavo2015_4_.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v":12] [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details I am one step behind with C1 version of the board... What can I do?
  6. Ok Jon, Will try that. Should I keep the C.1 directory under nexys4_ddr? Before I had 1.1 thanks, Pierre
  7. HI Jon, Thanks for the hello world project. I have errors when I open the BD: [IP_Flow 19-479] 'UARTLITE_BOARD_INTERFACE--> UARTLITE_BOARD_INTERFACE' cyclic dependency found while setting value 'usb_uart' on parameter 'UARTLITE_BOARD_INTERFACE'. [IP_Flow 19-3461] Value 'usb_uart' is out of the range for parameter 'UARTLITE BOARD INTERFACE(UARTLITE_BOARD_INTERFACE)' for BD Cell '/axi_uartlite_0' . Valid values are - Custom, USB_Uart [IP_Flow 19-3461] Value 'usb_uart' is out of the range for parameter 'UARTLITE BOARD INTERFACE(UARTLITE_BOARD_INTERFACE)' for BD Cell '/axi_uartlite_0' . Valid values are - Custom, USB_Uart [IP_Flow 19-3439] Failed to restore IP '/axi_uartlite_0' customization to its previous valid configuration. This is what I get when I rerun validate design in the BD: [IP_Flow 19-3461] Value 'usb_uart' is out of the range for parameter 'UARTLITE BOARD INTERFACE(UARTLITE_BOARD_INTERFACE)' for BD Cell '/axi_uartlite_0' . Valid values are - Custom, USB_Uart [IP_Flow 19-3461] Value 'usb_uart' is out of the range for parameter 'UARTLITE BOARD INTERFACE(UARTLITE_BOARD_INTERFACE)' for BD Cell '/axi_uartlite_0' . Valid values are - Custom, USB_Uart [IP_Flow 19-3439] Failed to restore IP '/axi_uartlite_0' customization to its previous valid configuration. [IP_Flow 19-3461] Value 'usb_uart' is out of the range for parameter 'UARTLITE BOARD INTERFACE(UARTLITE_BOARD_INTERFACE)' for BD Cell '/axi_uartlite_0' . Valid values are - Custom, USB_Uart [IP_Flow 19-3461] Value 'usb_uart' is out of the range for parameter 'UARTLITE BOARD INTERFACE(UARTLITE_BOARD_INTERFACE)' for BD Cell '/axi_uartlite_0' . Valid values are - Custom, USB_Uart [IP_Flow 19-3439] Failed to restore IP '/axi_uartlite_0' customization to its previous valid configuration. If I remove AXI UART lite and out it back in the BD, then the errors go away. I have noticed the clock to the MIG is 100MHz. Now, when I synthesize this project, I have errors: [Synth 8-439] module 'design_1_mig_7series_0_0' not found ["C:/Nexys/Nexys4DDR_Vivavo2015_4_ref/Nexys4DDR_Vivavo2015_4_.srcs/sources_1/bd/design_1/hdl/design_1.v":573] [Synth 8-285] failed synthesizing module 'design_1' ["C:/Nexys/Nexys4DDR_Vivavo2015_4_ref/Nexys4DDR_Vivavo2015_4_.srcs/sources_1/bd/design_1/hdl/design_1.v":13] [Synth 8-285] failed synthesizing module 'design_1_wrapper' ["C:/Nexys/Nexys4DDR_Vivavo2015_4_ref/Nexys4DDR_Vivavo2015_4_.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v":12] [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details Concerning my project: 1) Here are the messages: [Synth 8-439] module 'uart_test_bd_mig_7series_0_0' not found ["C:/Nexys/uart_test/uart_test.srcs/sources_1/bd/uart_test_bd/hdl/uart_test_bd.v":1837] [Synth 8-285] failed synthesizing module 'uart_test_bd' ["C:/Nexys/uart_test/uart_test.srcs/sources_1/bd/uart_test_bd/hdl/uart_test_bd.v":1308] [Synth 8-285] failed synthesizing module 'uart_test_bd_wrapper' ["C:/Nexys/uart_test/uart_test.srcs/sources_1/bd/uart_test_bd/hdl/uart_test_bd_wrapper.v":12] [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details Good news is that both your project and mine have the same problem with the MIG 2) 16 for the cache as requested in the ref design: https://reference.digilentinc.com/_media/nexys4-ddr/nexys4ddr-mb_blockauto.png 3) No change in the microblaze other than what is asked in the link: https://reference.digilentinc.com/_media/nexys4-ddr/nexys4ddr-mb_blockauto.png 4) Yes I am using the digilent board file. I have attached what I use from this link: https://reference.digilentinc.com/reference/software/vivado/board-files?redirect=1 nexys4_ddr.zip
  8. Hi Jon, Thanks for your quick response. I have attached a screen shot of the block design. Best regards, Pierre
  9. Hello, I have built this reference design with Vivado 2015.4. https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-4-ddr-getting-started-with-microblaze/start Where creating the bitstream, I get the following error: Vivado Commands apply_bd_automation -rule xilinx.com:bd_rule:mig_7series -config {Board_Interface "DDR2_SDRAM" } [get_bd_cells mig_7series_0] launch_runs impl_1 [IP_Flow 19-1747] Failed to deliver file 'c:/Xilinx/Vivado/2015.4/data/ip/xilinx/mig_7series_v2_4/xit/vlog_synth_rpr.xit': error renaming "c:/Nexys/uart_test/uart_test.srcs/sources_1/bd/uart_test_bd/ip/uart_test_bd_mig_7series_0_0/_tmp/uart_test_bd_mig_7series_0_0" to "c:/Nexys/uart_test/uart_test.srcs/sources_1/bd/uart_test_bd/ip/uart_test_bd_mig_7series_0_0/uart_test_bd_mig_7series_0_0": permission denied [IP_Flow 19-167] Failed to deliver one or more file(s). [IP_Flow 19-3505] IP Generation error: Failed to generate IP 'uart_test_bd_mig_7series_0_0'. Failed to generate 'Verilog Synthesis Wrapper' outputs: [IP_Flow 19-98] Generation of the IP CORE failed. Failed to generate IP 'uart_test_bd_mig_7series_0_0'. Failed to generate 'Verilog Synthesis Wrapper' outputs: [BD 41-1030] Generation failed for the IP Integrator block mig_7series_0 thanks, Pierre