chrisdoe

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  1. That was valuable information. Maybe I could or should have figured that out by myself. Thanks a lot!
  2. P.S. For information. Maybe fixable. Sending a Byte over SPI every 60 us makes Waveforms hanging with no response almost instantly.
  3. hi Attila! thanks for the answer so far. Sure I will study the examples. Thank you. I am aware of the protocol analyzer, tried it in spy-mode but I did not receive anything useful. Tried it again just as you mentioned it and...well it seems to give data (in hex, maybe I'll should try to figure out if that can be set to an other base). pebkac I think. edit: Found the decimal setting. Interesstingly you can only set the frequency to 12.5 MHz, not 16 MHz. (beta 3.11.14) And why would a nominal frequency matter with spi in Three-wire mode when data is clocked in? I feel encouraged to explain, why my post sprang to mind. I was debugging a system that is dealing with mains-frequency i.e. there is a 10s to 100s of ms world. But during that the happens to be fast action. I have that SPI-port (running at 16 MHz) I mentiones and some digital lines whose timing is critical (some 10 ns). The maximum number of Samples I can set the logic analyzer to is 100000. That is only ms at a 100 MHz Rate.... Or am I missing something? Is there a better way for me? You see that evenmany samples start to look less comfortable when you try to monitor signals with a high rate for some time. That is what made me think about the "store the ns-timestamp for an edge" method, which would lead to literally unlimeted observation times with such sparse edges. Thank you. All of you do a great job
  4. dear fellows and Digilent staff, I don't know if ideas are welcome in this forum or where to post them. Feel free to move this thread to a different location or completely delete it. For the first time I am using the Digital Discovery for debugging and analyzing of a more complex embedded project instead of just playing with it. It is indeed helpful, although there are some points I would like to report. Imho points to make this tool even more helpful. I am aware that the following modifications will most likely involve the fpga design and therefore mean more work than changing waveforms only. However I see great potential and would like to communicate my ideas and wishes. 1) DDs memory is massive compared to the AD. Great! But often there is no need for zillions of data lines or complete memory bus, and one single SPI port in addition with some DIOs is enough. Do you see chances to implement a flexible memory layout? If I burst data on a high speed SPI port with relatively long periods of inactivity, monitoring a sufficiently long period soon gets impossible. 1.1) I remember that there was a protocol analyzer some (several) years ago that stored timestamps instead of sampled data of the DIO lines. The software reconstructed the lines from these timestamps. When expecting a sparse transistion pattern with periods of inactivity and relatively few edges... how cool would it be to switch from the traditional mode to such a timestamped mode! Imagine your memory limiting the number of edges instead of the number of samples! 2) If there are quite long periods of inactivity it is not possible to do proper Bus decoding in the logic analyzer sections. I like to send diagnostic data via SPI where several ms of inactivity is not uncommon - You just see that there is a bar on the SPI bus but no information about what has been sent cannot be identified. Extraction or a different visualisation could help. 3) scripting.... Can you give sources of inspiration and a place to get started and learn? If you know java script or are used to such things, the documentation under help maybe sufficiant. However I am a child from the last millenium and sadly it does not help me. thank you and best wishes
  5. Shame on me, I think I figured it out. In the Supplies Tab we have "DIN Pull" which can be set to up/down or middle. That, I guess, sets REF_H/L under the hood. At first I didn't pay much attention to that part, because I thought it was all about the IO-pins.
  6. hello everyone! we learn in the reference manual that DIN_VREF_H/DIN_VREF_L are used to generate VREFIO. Both signals are driven by FPGA pins which are located on a Bank that is powered by VCCIO_PROG. I believe VCCIO_PROG is just the voltage I can set under the supplies Tab as Voltage i.e. 1.2V to 3.3V. What I cannot find is where to configure the values for DIN_VREF_H/DIN_VREF_L. I would like to try the effect for noise immunity when I set woth low. thanks
  7. hello attila, Your pictures look like you are able to only slightly overcompensate your probes, right? So chances seem to be high that my probes are the root of my trouble and I should think about getting some of the 'official' probes. I tried two of my old ones which -seem- to have too little capacitance in them. thank you
  8. Hello everybody! I have a problem with my AD2/BNC combination. When I tried to compensate my probe I realized that obviously I cannot manage to do so. The AD2 itself has 43 pF input capacitance as stated in the tech manual. Does the BNC adapter add even more to that. The waveform always looks like undercompensated, so my guess was that the AD2 has so much input capacitance that my probe is always 'out of tune'. Do you have any ideas or could someone second my suspection? thank you!
  9. Thank you! Yes that helped a LOT! I had one of those rare moments of understanding and bingo. And why on earth didn't I get that 😉 Digilent should start publishing some textbooks - the explanation was a joy to read.
  10. Thank you for your support so far! I am eager to get things explained from attila.
  11. hello guys please be patient I am in the learning process and somewhat new to electronics. What I am struggling with is the clipping function of the DIO pins on the digital discovery. I cannot figure out how that is supposed to work. They say when there is no clipping Q3B is off and when there is clipping i.e. VU5V2_ESD > 5V2 then Q3B turns on and pulls this voltage down for safety. But how? If there is no voltage at all, Q3A,B's bases are pulled downd through R173 with 6V on Q3A's Emitter and 6V-0.2V on Q3B's Emitter. So why are they not ON? What is the purpose of C223? Can someone enlighten me and elaborate this piece of the schematic? second thing. On the digital inputs I see that input protection is done with a schottky diode from input to 3V3. Why don't we just clip the DIOs through D9 to 5V?