TestDeveloper

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  1. TestDeveloper

    How to generate another, faster clock (CMOD S7) ?

    Hi Dan, did it. reg [25:0] cnt = 0; always @(posedge clk100) cnt <= cnt + 1; assign led[0] = cnt[25]; ...shows, that clk100 runs wirh around 100 MHz. Thanks! Artur
  2. TestDeveloper

    XADC Simultaneous Sampling, synchronous at 1MSps

    Hi JColvin, I supposed something like that. Thanks for clarifying! Arthur
  3. TestDeveloper

    XADC Simultaneous Sampling, synchronous at 1MSps

    Hello Community, I'm working with the CMOD S7 development board, which contains a Spartan-7 FPGA, including XADC (Two ADCs, each capable for 1Msps) and two "breadboardable" external analog inputs. After extensively studying the 92 pages of the UG480 I suppose, that it is not possible, to run the CMOD S7 in simultaneous sampling mode (ADC A and ADC B, both together with 1MSps) by using both external analog inputs, because they are assigned to auxiliary analog inputs no. 5 and 12. Is that right? "Simultaneous Sampling Mode" (p. 60 on UG480) samples a combination of Ch 0 and 8, 1 and 9, 2 and 10, ... 4 and 12, 5 and 13, ... at the same time. To cover 5 and 12, it is necessary to select 4 and 12 and 5 and 13, what results in two sampling periods per sequence, what leads to 500 kSps. Is there a trick to enable 2x 1MSps anyway in that situation, for ADC channel 5 and 12 ? If not, why did Digilent choose ADC channel 5 and 12 as external inputs on the CMOD S7, what reduces the potential of that board...? Arthur
  4. TestDeveloper

    How to generate another, faster clock (CMOD S7) ?

    Hi xc6lx45, thanks for that very detailed and good description, how I could do it with the wizard. I'm sure, that will work. But, additionally, now I found a way to add the MMCME2_BASE just in my verilog code: wire mmcm2_clk_fb, locked_1, clk100; MMCME2_BASE #( .BANDWIDTH("OPTIMIZED"), .CLKFBOUT_MULT_F(50.0), .CLKFBOUT_PHASE(0.0), .CLKIN1_PERIOD(83.33), .CLKOUT0_DIVIDE_F(6.0), .CLKOUT0_DUTY_CYCLE(0.5), .CLKOUT0_PHASE(0.0), .DIVCLK_DIVIDE(1), .REF_JITTER1(0.0), .STARTUP_WAIT("FALSE") ) MMCME2_BASE_inst ( .CLKOUT0(clk100), .CLKFBOUT(mmcm2_clk_fb), .LOCKED(locked_1), .CLKIN1(clk), .PWRDWN(1'b0), .RST(1'b0), .CLKFBIN(mmcm2_clk_fb) ); what also works. I'm (still) not a friend of using that Vivando wizards and prefer the "good old text code" in my HDL file ;-). You'r right. I was totally wrong with the constraint file.
  5. TestDeveloper

    How to generate another, faster clock (CMOD S7) ?

    Hi jpeyron, The advice about the wizard was good, but I'm (still) not a friend of using that Vivando wizards. Unfortunately, DCM_CLKGEN doesn't work on a 7-Series FPGA (just up to 6). But, that brought me to another thread: https://forum.digilentinc.com/topic/5037-clockpll-for-cmod-a7solved/?_fromLogin=1 what bring me to the following solution, that works (12 MHz * 50 / 6 = 100 MHz): wire mmcm2_clk_fb, locked_1, clk100; MMCME2_BASE #( .BANDWIDTH("OPTIMIZED"), .CLKFBOUT_MULT_F(50.0), .CLKFBOUT_PHASE(0.0), .CLKIN1_PERIOD(83.33), .CLKOUT0_DIVIDE_F(6.0), .CLKOUT0_DUTY_CYCLE(0.5), .CLKOUT0_PHASE(0.0), .DIVCLK_DIVIDE(1), .REF_JITTER1(0.0), .STARTUP_WAIT("FALSE") ) MMCME2_BASE_inst ( .CLKOUT0(clk100), .CLKFBOUT(mmcm2_clk_fb), .LOCKED(locked_1), .CLKIN1(clk), .PWRDWN(1'b0), .RST(1'b0), .CLKFBIN(mmcm2_clk_fb) ); So, I was totally wrong with the constraint file. The MMCME2_BASE macro is the right one to use in my verilog file - easy! Thanks!
  6. TestDeveloper

    How to generate another, faster clock (CMOD S7) ?

    Hello community, i started to work with vivado some weeks ago and successfully created some verilog based projects for my Digilent CMOD S7 evaluation board. Now I want to use a faster clock then the board standard 12 MHz (CMOD S7 should work up to 450 MHz, i red in the reference paper). E.g. I tried to create a 100 MHz clock with the following lines (added the third line "create_generated_clock" to the default constraint file *.xdc): set_property -dict { PACKAGE_PIN M9 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L13P_T2_MRCC_14 Sch=gclk create_clock -add -name sys_clk_pin -period 83.33 -waveform {0 41.66} [get_ports { clk }]; create_generated_clock -name clk100 -source [get_ports { clk }] -multiply_by 25 -divide_by 3 [get_ports { clk100 }]; I added clk100 as additional input in my top verilog module. The project is a "plain" verilog HDL project without any IP. This does not work: - Synthesis runs fine. - Implementation creates one critical Warning: "Generated clock ... has no logical paths from master clock ..." - Generate Bitstream fails with an Error. Can anyone tell me a solution? Pleas e provide the correct Line I need to fill in in the constraint file (I think, it's just a very simple mistake). I looked for hours but could not find a clear explanation about this problem. Thanks for help in advance! Arthur
  7. TestDeveloper

    How to generate another, faster clock (CMOD S7) ?

    Hello community, i started to work with vivado some weeks ago and successfully created some verilog based projects for my Digilent CMOD S7 evaluation board. Now I want to use a faster clock then the board standard 12 MHz (CMOD S7 should work up to 450 MHz, i red in the reference paper). E.g. I tried to create a 100 MHz clock with the following lines (added the third line "create_generated_clock" to the default constraint file *.xdc): set_property -dict { PACKAGE_PIN M9 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L13P_T2_MRCC_14 Sch=gclk create_clock -add -name sys_clk_pin -period 83.33 -waveform {0 41.66} [get_ports { clk }]; create_generated_clock -name clk100 -source [get_ports { clk }] -multiply_by 25 -divide_by 3 [get_ports { clk100 }]; I added clk100 as additional input in my top verilog module. The project is a "plain" verilog HDL project without any IP. This does not work: - Synthesis runs fine. - Implementation creates one critical Warning: "Generated clock ... has no logical paths from master clock ..." - Generate Bitstream fails with an Error. Can anyone tell me a solution? Please provide the correct Line I need to fill in in the constraint file (I think, it's just a very simple mistake). I looked for hours but could not find a clear explanation about this problem. Thanks for help in advance! Arthur