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  1. 3 points
    Ciprian

    Digital Twin

    Hi @Kris Persyn, It depends on how you manage your resources, driving immersive visuals on a HDMI display can be done in multiple ways at different resolutions, some are PL taxing others are DDR taxing; you could generate entire frame buffers in PL or PS or you could find a optimal algorithm to change just the previous frame or you could allocate a high number of frame buffers and then run them in a loop. It also depends on how math lab synthesizes the IP you will need to add to your design. If you design your project properly and don't aim for a resolution higher more 720p( I'm being conservative, we managed to drive the HDMI at 1080p with processing filters without a problem) I think it should be enough for what you want to do, resource wise. My suggestion, download and install Vivado, download and install the board files, create and implement your project look at the resource consumption and then buy a board. - Ciprian
  2. 3 points
    In your constraint file, the ddc pins have lowercase "ddc_scl_io" and "ddc_sda_io". Your block design has the port in uppercase "DDC". The case must match. Try editing your constraint file to have "DDC_scl_io" and "DDC_sda_io".
  3. 3 points
    jpeyron

    pmod wifi

    Hi @harika, I believe the HTML web page error is related to the materials on the SD card. 1) Please attach a screen shot of the contents of the Sd card you are using. 2) Please follow the YouTube video here from about 6 minutes and 28 seconds on for how to set up the HTTP server project. Make sure to update the login an password for the router/modem you are using. thank you, Jon
  4. 3 points
    @thobie, the bare-metal purchase option for the Zybo was done to enable a lower price point for those who do not require the accessories. For the rest of our customers, adding the Accessory Kit is recommended during the purchase process. You are not the first and the last to complain about version compatibility. It is economically unfeasible for us to update all support projects, IP and support packages provided for free four times per year for each Vivado version. Instead we made a commitment to consider the last Vivado release in each year stable and do a once-a-year update cycle. In that regard, 2017.4 is the version we are upgrading projects to. There is a question whether OOB designs should be updated at all, or kept at the version which generated the binary image shipped with the board. The board presets are not versioned for Vivado (no version-specific releases in our git repo), because these should be forward-compatible with Vivado versions. The critical warning itself related to CK-to-DQS delays being negative appears starting with 2017.4. The negative values are due to CK trace being shorter than any of the four DQS traces. In the early days of Zynq board design negative values where listed as sub-optimal, but not erroneous. Tree topology instead of fly-by was also among the routing recommendations for DDR3 layouts. So the Zybo was designed with this sub-optimal layout due to space constraints. During Write Leveling calibration, 0 is used as an initial value instead of the negative preset delays. After calibration, if the skew is still too low, the clock is inverted. See ug585 pg 316 for more details. All Zybos shipped to customers are functionally tested and pass the DDR3 calibration process. Xilinx recommendations changed in the mean time, both in terms of routing topology and delay values. A trace of this can be found here: https://www.xilinx.com/support/answers/53039.html. The > 0ns requirement was introduced to be in line with non-Zynq MIG-based designs, where negative delays were never permitted. Since these delays are board-dependent, we would need to re-design the board to make the delay positive. This is impossible with the current form-factor. Another option would be modifying the board preset file and forcing a zero value instead of the actual delay. The tools seem to be using zero anyway for calibration. This will have to be thoroughly verified first.
  5. 3 points
    Hello, I've posted the next part in my FPGA graphics series using the Arty + VGA Pmod or Basys 3. It shows you how to make use of double buffering to animate sprites using simple Verilog. https://timetoexplore.net/blog/arty-fpga-vga-verilog-03 Feedback very welcome, Will PS. I'll add the source to GitHub shortly.
  6. 3 points
    attila

    WaveForms beta download

    3.11.7 digilent.waveforms_beta_v3.11.7_64bit.exe digilent.waveforms_beta_v3.11.7.dmg digilent.waveforms_beta_3.11.7_amd64.deb digilent.waveforms_beta_3.11.7.x86_64.rpm minor fixes and improvements 3.11.6 digilent.waveforms_beta_v3.11.6_64bit.exe digilent.waveforms_beta_v3.11.6.dmg digilent.waveforms_beta_3.11.6_amd64.deb digilent.waveforms_beta_3.11.6.x86_64.rpm Added: - Protocol - UART Spy - Max Lines option: log limit to prevent application slowdown - Line Wrap option - tooltips for UI controls listing Script access path - application and script Font options - dark theme support for Script 3.11.5 digilent.waveforms_beta_v3.11.5_64bit.exe Added: - Script open/save text file - application argument: -script myscript.txt/js Fixed: - warnings at low record rates 3.11.4 digilent.waveforms_beta_v3.11.4_64bit.exe Added: - Scope: - set/reset zero offset in each channel option - precision option for measurements Fixed: - Script: access to traces and channels from Instrument.Export - unit conversions V to Ṽ, A to à - I2S 32 bit data 3.11.3 digilent.waveforms_beta_v3.11.3_64bit.exe digilent.waveforms_beta_3.11.3_amd64.deb digilent.waveforms_beta_3.11.3.x86_64.rpm Fixes 3.11.2 digilent.waveforms_beta_v3.11.2_64bit.exe digilent.waveforms_beta_3.11.2_amd64.deb digilent.waveforms_beta_3.11.2.x86_64.rpm Added: - Spectrum, Network and Impedance Analyzer store time data when this view is open Fixed: - runscript argument - loading of docked views geometry 3.11.1 digilent.waveforms_beta_v3.11.1_64bit.exe digilent.waveforms_beta_3.11.1_amd64.deb digilent.waveforms_beta_3.11.1.x86_64.rpm Added: - Scope: out of range warning in measurements - Protocol/UART: - support up to 32bit/word - TX/RX format: text, binary, decimal, hex - Wheel Direction option - Logic Analyzer: option to swap previous/next events - Spectrum Analyzer: allowing higher number of BINs for CZT 3.10.7 digilent.waveforms_beta_v3.10.7_64bit.exe Added: - Spectrum: logarithmic magnitude scale for voltage units - Protocol: datetime stamp for SPI/I2C Spy Fixes 3.10.6 digilent.waveforms_beta_v3.10.6_64bit.exe Added: - Scope - access to digital channels from custom mathematic channels - digital measurements view Fixes 3.10.5 digilent.waveforms_beta_v3.10.5_64bit.exe digilent.waveforms_beta_3.10.5_amd64.deb digilent.waveforms_beta_3.10.5.x86_64.rpm Added: - Power Supplies for AD2: tracking, slider, min/max - Logic Analyzer: Measurements - Impedance Analyze: DC mode compensation - SDK VB wrapper, C# wrapper updated Fixed: - EExplorer Wavegen AM/FM index precision for sine 3.10.4 digilent.waveforms_beta_v3.10.4_64bit.exe Fixed: - decimal resolution in Export, Data and Event views 3.10.3 digilent.waveforms_beta_v3.10.3_64bit.exe digilent.waveforms_beta_v3.10.3.dmg digilent.waveforms_beta_3.10.3_amd64.deb digilent.waveforms_beta_3.10.3.x86_64.rpm Added: - UART format option (binary, decimal...) - SDK I2C without clock stretching - SDK examples: Digital_I2c_PmodAcl.py, Digital_I2c_PmodGyro.py - Spectrum Analyzer THDN measurement, THDp and THDNp in percentage units - Impedance Analyzer: - constant current, voltage, custom script for amplitude and resistance control - Option to disable mouse drag and wheel operations on plots - Impedance/Network Analyzer: averaging time - Wavegen: extended frequency option Changed: - special values (none, off) moved to end of the preset list 3.10.2 digilent.waveforms_beta_v3.10.2_64bit.exe digilent.waveforms_beta_v3.10.2_32bit.exe digilent.waveforms_beta_v3.10.2.dmg digilent.waveforms_beta_v3.10.2_mavericks.dmg digilent.waveforms_beta_3.10.2_amd64.deb digilent.waveforms_beta_3.10.2_i386.deb digilent.waveforms_beta_3.10.2.x86_64.rpm digilent.waveforms_beta_3.10.2.i686.rpm Added: - Impedance Analyzer - voltage, current and custom plots - edit Meter list - Resistance mode for Meter, Frequency DC option - step mode in Time view - Netowrk Analyzer - step mode in Time and FFT views - amplitude table and custom function Fixed: - Help minor fix - Protocol SPI and I2C Sensor rate improvement - StaticIO button lock 3.8.22 digilent.waveforms_beta_v3.8.22_64bit.exe digilent.waveforms_beta_v3.8.22_32bit.exe Added: - Impedance differential setup, W1-C1P-DUT-C1N-C2-R-GND 3.8.21 digilent.waveforms_beta_v3.8.21_64bit.exe digilent.waveforms_beta_v3.8.21_32bit.exe digilent.waveforms_beta_v3.8.21.dmg digilent.waveforms_beta_3.8.21_amd64.deb digilent.waveforms_beta_3.8.21_i386.deb digilent.waveforms_beta_3.8.21.x86_64.rpm digilent.waveforms_beta_3.8.21.i686.rpm Added: - data property for impedance/network channels. - Impedance.Resistor.reference property - instruments accessible without index in Script tool like Scope. Fixes... 3.8.20 digilent.waveforms_beta_v3.8.20_64bit.exe Added: - Logger function access to other channels value, average, min, max - Script access to Logger channel set data property, getting average, minimum, maximum Fixed: - Logger Show/Maximum - Script Protocol.I2C.Clear() function 3.8.18 digilent.waveforms_beta_v3.8.18_64bit.exe digilent.waveforms_beta_v3.8.18_32bit.exe digilent.waveforms_beta_v3.8.18.dmg Added: - Network Analyzer - logarithmic scale and percentage unit - spectrum measurements: Carrier, THD+N, THD, HD# - FFT view - Averaging option 3.8.17 digilent.waveforms_beta_v3.8.17_64bit.exe digilent.waveforms_beta_v3.8.17_32bit.exe digilent.waveforms_beta_v3.8.17.dmg digilent.waveforms_beta_3.8.17_amd64.deb digilent.waveforms_beta_3.8.17_i386.deb digilent.waveforms_beta_3.8.17.x86_64.rpm digilent.waveforms_beta_3.8.17.i686.rpm Added: - Scope - persistence support for smooth curve and min/max sampling - custom math - current value in custom math function, can be used for averaging - initialization code for integration purposes - examples - unit presets for: ohm, degree, VAC, AAC - Spectrum - Import/Export samples for Traces - trace information option - Range option to adjust all the scope input ranges - Network and Spectrum - Script support for set magnitude property - Step size and steps per decade settings - Network Analyzer - custom plots: THD, HD2, HD3 - Protocol - I2C/Spy glitch filter based on frequency setting - Device options - On Close: Run (keep running), Stop, Shutdown - USB Power: Always ON or Stop with AUX for AD2 - USB Limit: USB current limitation AD1,2 - Audio Output: AD1, 2 - WaveForms SDK FDwfParamSet/Get, FDwfDeviceParamSet/Get - DwfParamOnClose, DwfParamUsbPower, DwfParamLedBrightness, DwfParamAudioOut, DwfParamUsbLimit - Notes toolbar show/hide option - on/off icon for toggle buttons: supply enable, network analyzer reference... - show entire capture button Changed: - renewed mouse wheel, drag and key (left,right,up,down) operation on plots and axis Fixed: - EExplorer output glitch during first device connection - NI VI crash when initializing without device connected - Scope XY plot 3.8.11 digilent.waveforms_v3.8.11_64bit.exe digilent.waveforms_v3.8.11_32bit.exe digilent.waveforms_v3.8.11.dmg digilent.waveforms_3.8.11_amd64.deb digilent.waveforms_3.8.11_i386.deb digilent.waveforms_3.8.11.x86_64.rpm digilent.waveforms_3.8.11.i686.rpm Added: - Digital Discovery: - LED brightness option - Logic Analyzer - ASCII format for: Bus, SPI, I2C, I2S - Format option for I2C - Logic Analyzer and Patterns - Line Color option - Protocol - Format option for SPI and I2C: Hexadecimal, Decimal, Binary, ASCII - Plot Width option in application settings Changed: - drawing quality improvement for thicker lines - color dialog buttons renamed to Close and Reset 3.8.9 digilent.waveforms_v3.8.9_64bit.exe digilent.waveforms_v3.8.9_32bit.exe digilent.waveforms_v3.8.9.dmg digilent.waveforms_3.8.9_amd64.deb digilent.waveforms_3.8.9_i386.deb digilent.waveforms_3.8.9.x86_64.rpm digilent.waveforms_3.8.9.i686.rpm Added: - WF/Settings/Options: Locale with System or English US regional option, export and import options - SDK: FDwfParamSet/Get function - Scope: measurement resolution Fixed: - minor issues 3.8.8 digilent.waveforms_v3.8.8_64bit.exe digilent.waveforms_v3.8.8_32bit.exe digilent.waveforms_v3.8.8.dmg Added: - WF SDK: - examples updated to be Python v3 compatible - FDwfAnalogImpedance functions for impedance/network analysis - Protocol: CAN receiver filter by ID - Impedance: Export information about amplitude and offset Fixed: - WF SDK: FDwfDigitalSpi functions read MISO/RX 3.8.7 digilent.waveforms_v3.8.7_64bit.exe Fixed: - Scope: save/load of coefficients for custom Math channel filter 3.8.6 digilent.waveforms_v3.8.6_64bit.exe digilent.waveforms_3.8.6_amd64.deb Added: - Export: Wavegen and Supplies information added to Scope, Spectrum, Impedance, Network export comments Fixed: - Script Tool.exec timeout - CAN high polarity option in Protocol tool and WF SDK 3.8.5 digilent.waveforms_v3.8.5_64bit.exe Added - Script functions: getSaveFile, getOpenFile, getDirectory - Scope: multiple scales, zero offset - Notes view - Export options: notes, header as comment - Help tab: floating/undock option, find with highlight Fixed: - Impedance Analyzer frequency scale in export 3.7.22 digilent.waveforms_v3.7.22_64bit.exe digilent.waveforms_v3.7.22_32bit.exe digilent.waveforms_v3.7.22.dmg digilent.waveforms_3.7.22_amd64.deb digilent.waveforms_3.7.22_i386.deb digilent.waveforms_3.7.22.x86_64.rpm digilent.waveforms_3.7.22.i686.rpm Added - Scope/Logic View/Logging picture format - Script: - Export function for instruments - access to Protocol/UART/RX using Receiver, Receive and ReceiveArray functions, SendArray Fixed - Scope edge trigger position for all devices, when only one or two samples are above the threshold - other minor fixes 3.7.21 digilent.waveforms_v3.7.21_64bit.exe digilent.waveforms_v3.7.21_32bit.exe digilent.waveforms_3.7.21_amd64.deb digilent.waveforms_3.7.21_i386.deb digilent.waveforms_3.7.21.x86_64.rpm digilent.waveforms_3.7.21.i686.rpm Added - Wavegen dynamic configuration, adjustments without restarting the generator - SDK support for CAN bus TX, RX - more detail in Spectrum, Network and Impedance Analyzer export comments - import data orientation option Fixed - Network Analyzer Meter export and copy - Data Logger quick measurements - other fixes and optimizations 3.7.19 digilent.waveforms_v3.7.19-2_64bit.exe digilent.waveforms_v3.7.19-2_32bit.exe digilent.waveforms_v3.7.19.dmg digilent.waveforms_3.7.19-2_amd64.deb digilent.waveforms_3.7.19-2_i386.deb digilent.waveforms_3.7.19-2.x86_64.rpm digilent.waveforms_3.7.19-2.i686.rpm Added: - Logic I2S Show channel option - SDK functions for UART, SPI, I2C master and UART receiver Changed: - OS-X rollback to FTDI driver 1.2.2 Fixed: - Impedance Analyzer: save/load of views positions - other fixes and optimizations 3.7.15 digilent.waveforms_v3.7.15_64bit.exe digilent.waveforms_v3.7.15_32bit.exe Added: - Logic Analyzer: position (Nth word) option for SPI trigger on value - Impedance: Nyquist plot; settle time, minimum periods options - Wavegen, Network/Impedance Analyzer: external Amplification option - Tabbed/Docking window switching from main window Changed: - lower frequency limit for Scope, AWG, Network, Impedance Fixed: - 10ns delay in Logic Analyzer Sync and Protocol interface - Sound Card device CPU usage 3.7.14 digilent.waveforms_v3.7.14_64bit.exe digilent.waveforms_v3.7.14_32bit.exe Added: - Protocol I2C ACK/NAK last read byte option Changed: - Windows XP, Vista compatible FTDI driver in 32bit installer 3.7.13 digilent.waveforms_v3.7.13_64bit.exe digilent.waveforms_v3.7.13_32bit.exe digilent.waveforms_v3.7.13.dmg digilent.waveforms_3.7.13_amd64.deb digilent.waveforms_3.7.13_i386.deb digilent.waveforms_3.7.13.x86_64.rpm digilent.waveforms_3.7.13.i686.rpm Added: - Sound Card device of the computer can be used as Scope and Wavegen - Scope sampling clock for Electronics Explorer - Logic Analyzer data compression for recording, for Electronics Explorer - Scope and Wavegen support for 4th device configuration of Analog Discovery 1 & 2 - Scope Logging Repeat option - Scope Audio view: Stereo, Tempo options - MacOS option for application menu 3.7.12-2 digilent.waveforms_v3.7.12-2_64bit.exe Fixed: - Analog Discovery 2 configuration file descriptions 3.7.12 digilent.waveforms_v3.7.12_64bit.exe digilent.waveforms_v3.7.12_32bit.exe Added: - Scope sampling clock under time options, for Analog Discovery 1 & 2. The trigger IOs can be used as sample clock with delay and edge options. - Logic Analyzer data compression for recording, for Analog Discovery 1 & 2 Changed: - Windows installer: - embedded prerequisites: Windows Installer, Visual C++ Redistributable 9 32/64bit, 12 64bit - split installer for 32bit and 64bit WF applications, but the included WF runtime for custom applications support both architectures Fixed: - Logic Analyzer UART frame error threshold 3.7.10 digilent.waveforms_v3.7.10.exe Added: - Spectrum Analyzer Markers Fixed: - SDK Electronics Explorer enumeration - Scope Math channel unit presets 3.7.9 digilent.waveforms_v3.7.9.exe Fixing: - Logic Analyzer Event view double click for signals 3.7.8 digilent.waveforms_v3.7.8.exe Changed: - Impedance Analyzer: - view names - solid line for magnitude Fixed: - Impedance Analyzer admittance |Y| value 3.7.7 digilent.waveforms_v3.7.7.exe Added: - Scope and Logic trigger detector for trigger source Fixed: - warning message when connecting to EExplorer - Patterns trigger on Digital Discovery.
  7. 2 points
    xc6lx45

    Increasing the clock frequency to 260 MHz

    Hi, reading between the lines of your post, you're just "stepping up" one level in FPGA design. I don't do long answers but here's my pick on the "important stuff" - Before, take one step back from the timing report and fix asynchronous inputs and outputs (e.g. LEDs and switches). Throw in a bunch of extra registers, or even "false-path" them. The problem (assuming this "beginner mistake") is that the design tries to sample them at the high clock rate. Which creates a near-impossible problem. Don't move further before this is understood, fixed and verified. - speaking of "verified": Read the detailed timing analysis and understand it. It'll take a few working hours to make sense of it but this is where a large part of "serious" design work happens. - Once the obvious problems are fixed, I need to understand what is the so-called "critical path" in the design and improve it. For a feedforward-style design (no feedback loops) this can be systematically done by inserting delay registers. The output is generated e.g. one clock cycle later but the design is able to run at a higher clock so overall performance improves. - Don't worry about floorplanning yet (if ever) - this comes in when the "automatic" intelligence of the tools fails. But, they are very good. - Do not optimize on a P&R result that fails timing catastrophically (as in your example - there are almost 2000 paths that fail). It can lead into a "rabbit's hole" where you optimize non-critical paths (which is usually a bad idea for long-term maintenance) - You may adjust your coding style based on the observations, e.g. throw in extra registers where they will "probably" make sense (even if those paths don't show up in the timing analysis, the extra registers allow the tools to essentially disregard them in optimization to focus on what is important) - There are a few tricks like forcing redundant registers to remain separate. Example, I have a dozen identical blocks that run on a common, fast 32-bit system clock and are critical to timing. Step 1, I sample the clock into a 32-bit register at each block's input to relax timing, and step 2) I declare these register as DONT_TOUCH because the tools would otherwise notice they are logically equivalent and try to use one shared instance. This as an example. - For BRAMs and DSP blocks, check the documentation where extra registers are needed (that get absorbed into the BRAM or DSP using a dedicated hardware register). This is the only way to reach the device's specified memory or DSP performance. - Read the warnings. Many relate to timing, e.g. when the design forces a BRAM or DSP to bypass a hardware register. - Finally, 260 MHz on Artix is already much harder than 130 MHz (very generally speaking). Usually feasible but you need to pay attention to what you're doing and design for it (e.g. a Microblaze with the wrong settings will most likely not make it through timing). - You might also have a look at the options ("strategy") but don't expect any miracles on a bad design. Ooops, this almost qualifies as "long" answer ...
  8. 2 points
    bogdan.deac

    OpenCV and Pcam5-c

    Hi @Esti.A, SDx, which includes SDSoC (Software Defined System on Chip), is a development environment that allows you to develop a computer vision application, in your case, using C/C++ and OpenCV library. The target of SDx-built applications are Xilinx systems on chip (SoC) (Zynq-7000 or Zynq Ultrascale+). Xilinx SoC architecture has two main components: ARM processor (single or multi core) named Processing System (PS) and FPGA, named Programmable Logic (PL). Using SDx to build an application for SoC allows you to choose which functions from your algorithm are executed in PS and which ones are executed in PL. SDx will generate all data movers and dependencies that you need to move data between PS, DDR memory and PL. The PL is suitable for operations that can be easily executed in parallel. So if you are going to choose a median filter function to be executed in PL, instead of PS, you will obtain a better throughput from your system. As you said, you can use OpenCV to develop your application. You have to take into account that OpenCV library was developed with CPU architecture in mind. So the library was designed to obtain the best performance on some specific CPU architectures (x86-64, ARM, etc.). If you are trying to accelerate an OpenCV function in PL using SDx you will obtain a poor performance. To overcome this issue, Xilinx has developed xfopencv, which is a subset if OpenCV library functions. The functionalities of xfopecv functions and OpenCV functions are the same but the xfopencv functions are implemented having FPGA architecture in mind. xfopencv was developed in C/C++ following some coding guideline. When you are building a project, the C/C++ code is given as input to Xilinx HLS (High Level Synthesis) tool that will convert it to HDL (Hardware Description Language) that will be synthetized for FPGA. The above mentioned coding guideline provides information about how to write C/C++ code that will be implemented efficiently in FPGA. To have a better understanding on xfopencv consult this documentation. So SDx helps you to obtain a better performance by offloading PS and by taking advantage of parallel execution capabilities of PL. Have a look on SDSoC documentation. For more details check this. An SoC is a complex system composed by a Zynq (ARM + FPGA), DDR memory and many types of peripherals. Above those, one can run a Linux distribution (usually Petalinux, from Xilinx) and above the Linux distribution, the user application will run. The user application may access the DDR memory and different types of peripherals (PCam in your case). Also, it may accelerate some functions in FPGA to obtain a better performance. To simplify the development pipeline Xilinx provides an abstract way to interact with, named SDSoC platform. SDSoC platform has two components: Software Component and Hardware Component that describes the system from the hardware to the operating system. Your application will interact with this platform. You are not supposed to know all details about this platform. This was the idea, to abstract things. Usually, the SDSoC platforms are provided by the SoC development boards providers, like Digilent. All you have to do is to download the last SDSoC platform release from github. You have to use SDx 2017.4. You don't have to build your own SDSoC platform. This is a complex task. You can follow these steps in order to build your first project that will use PCam and Zybo Z7 board. The interaction between PCam and the user application is done in the following way: there is an IP in FPGA that acquires live video stream from the camera, the video stream is written into DDR memory. This pipeline is abstracted by the SDSoC platform. The user application can access the video frames by Video4Linux (V4L2). The Live I/O for PCam demo shows you how to do this. I suggest you to read the proposed documentation to obtain a basic knowledge needed for SDSoC projects development. Best regards, Bogdan D.
  9. 2 points
    @jpeyron @D@n I fixed the bug in my SPI Flash controller design. Now I can read from Flash memory.
  10. 2 points
    Hi @Blake, I was struggling with the same problem. In Adam's project is mistake which result is an FMC-HDMI module is not recognizable by other devices. The reason for that is not sending EDID at all. The cause of this situation is wrong initialized EDID map. In Adams example EDID is initialized by: but the correct way is: the body of iic_write2 is from LK example: By the way, in LucasKandle example initialization is done in same way as in Adam's example so is the reason why it not worked in your case. I hope it will helps. If you want I will post my working code for a ZedBoard with FMC-HDMI when I clean it because at the moment is kind of messy.
  11. 2 points
    True. Zygot believes that making you work for knowledge is kinder than giving you solutions that can be used to mindlessly resolve your problem of the hour.... it's just a different philosophical bent...
  12. 2 points
    kwilber

    Pmod DA3 clocking

    It looks to me like DA3_WriteSpi() was adapted from code for a different device and has vestigial and incorrect code. Reviewing the AD5541A datasheet, several things stand out There is only a single register in the chip so there is no need for the u8 reg parameter. There is no need for a"config byte" to be sent before the data. The transfer is always 16 bits so there is no need to allow for arbitrary length data quoting from the datasheet "Input data is framed by the chip select input, CS. After a high-to-low transition on CS, data is shifted synchronously and latched into the serial input register on the rising edge of the serial clock, SCLK. After 16 data bits have been loaded into the serial input register, a low-to-high transition on CS transfers the contents of the shift register to the DAC register if LDAC is held low". Reviewing the PmodDA3 schematic, the ~LDAC signal is softly pulled to ground with a 10K resistor. So there is no need to explicitly toggle ~LDAC. What all this means is DA3_WriteSpi could be simplified to something like void DA3_WriteSpi(PmodDA3 *InstancePtr, u16 wData) { u8 bytearray[2]; bytearray[0] = ((wData & 0xFF00) >> 8); bytearray[1] = (wData & 0xFF); XSpi_Transfer(&InstancePtr->DA3Spi, bytearray, 0, sizeof(bytearray)); } You would then call it passing in just the instance pointer and the value you want to write to the DAC. u16 dacValue = 1234; DA3_WriteSpi(&myDevice, dacValue); I do not have a PmodDA3 on my bench so I cannot verify the function works, You can give it a try and let us know how it goes.
  13. 2 points
    kwilber

    Pmod DA3 clocking

    It seems to me the AXI Quad SPI block is sending address + data. Looking at the .xci file again, I see C_SPI_MEM_ADDR_BITS set to 24 bits. So 24 bits of address and 16 bits of data would yield 40 bits.
  14. 2 points
    kwilber

    Pmod DA3 Pinout

    That is one of the conventions commonly used to indicate an Active Low signal. So in this case, you pull Chip Select low when you want to access the chip. After you have toggled in all the data bits on the DIN line, you pull LDAC low. The Pmod DA3 reference manual has a link to the D/A chip's datasheet. That is the best first place to look for information on the device's function. The required signal timings are on page 5 of the datasheet.
  15. 2 points
    @Ahmed Alfadhel If you installed Vivado then you also installed the Xilinx Document Navigator. If you are serious about developing with FPGA devices you need to know how to find and access the plethora of documents that your vendor provides in order to use their devices properly. Check the box for 7 Series devices to see the list of reference manuals, User's Guides, Datasheets etc. From there you can add all relevant documents to your search and keep up to date. Do the same for ISE or Vivado tools. This is where everyone needs to start their Xilinx FPGA journey. Xilinx makes it easier than other FPGA vendors to obtain knowledge.
  16. 2 points
    The hot plug detect should be on the rx side. The source will see that and will then initiate the DDC conversation.
  17. 2 points
    The answer is yes, that fixed it! Thank you so much! The odd thing is that I tried this in one of my attempts and put it back to QSPI as it didnt work. Regardless thank you so very much for walking me through this. all looks good now:
  18. 2 points
    So the picture that you post of a (relatively) gigantic scope probe clip resting on a fairly small FPGA device in a BGA package is a way of making a statement. It might also be viewed as a picture that might be making a statement to you. I routinely use an LED to verify that my design is at least being clocked properly. Make a 32-bit counter and connect bit 26 or so to an obuf driving one of the boards LEDs. You can get an approximation of a 1 blink/s LED rate with a little math depending on the clock rate and the chosen counter bit. For me the clock rate of interest isn't the external clock coming into the FPGA but some clock output of an MMCM or PLL that I'm using for my design. If the LED is blinking then I at least know that something is alive in my design. You've got to be careful with those large scope probe grabbers around fine pitch components. I prefer to bring out a few debug versions of particular signals of interest to a PMOD and connect that to a scope probe ( the PMOD has DGND pin(s) ). You still have to exercise some caution with the ground clip on your scope probe as it's easy to short an adjacent pin to ground and ruin your day. It would be very useful if Digilent provided GND test points, or at least holes for test points, in an area of their boards for scope probing. The safest thing might be to stick a pin into the GND receptacle of one PMOD connector and probe on signals in another. Insulation stripped off suitably sized wires can help as well to keep ground clips from accidents. It's really easy to have that ground clip pop off whatever it's connect to and bounce around on exposed parts of your board; nothing good will come of that. I limit scope probing to when it's necessary. There are usually safer ways to evaluate signals in your FPGA design. Lastly, you should understand that its very easy to get a false impression of what a signal looks like, especially with normal scope probe ground clips. Think Heisenberg.
  19. 2 points
    Ciprian

    Hdmi out from zybo

    Try adding this: &i2c0 { clock-frequency = <100000>; status = "okay"; }; Here: <petalinux_project>/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi -Ciprian
  20. 2 points
    xc6lx45

    Cmod S6 - Multilayer?

    You might go to Texas Instruments' site (or AD or both) and find documentation for some $500 high frequency ADC or DAC eval board as example to study.. There's nothing wrong with copper planes, generally. Free-standing structures (such as non-connected filler polygons) can be bad, if they resonate. So are loops if the driving wire spans an area together with the GND return wire (for which the ground plane is an obvious solution). The worst resonators have high quality factor meaning loose coupling meaning it can be surprising how the energy managed to couple in. There's no such thing as too many ground vias... Note, your ground plane can do very interesting things in combination with the metal box it's in (resonant cavity) but that's a different story.
  21. 2 points
    The warning you pasted is benign and simply means there are no ILAs present in your design. The real issue could be your clock. You should review the datasheet for the dvi2rgb.Table 1 in section 5 specifies RefClk is supposed to be 200Mhz. Also, your constraint should follow the recommendation in section 6.1 for a 720p design. Finally, @elodg gives some great troubleshooting information in this thread.
  22. 2 points
    And.... I have this sense that if you keep describing what you did you will answer your own question. I don't have enough information yet to help. [I confess that I haven't bothered to read through your code] Verbalizing problems, if you go into enough detail, is often a fairly reliably way to resolve them. Sometimes it helps to have someone throw in a good question or two.
  23. 2 points
    zygot

    Cmod S6 - Multilayer?

    Consider that the FPGA on your module has 196 balls. The A7 versions have 236. You can answer your own question by thinking about how one gets all of those surface mount pads to ground, voltage and signal traces.
  24. 2 points
    Hi, Abdul, Here are my notes/recommendations: 1. Open your block diagram in Vivado where you created BRAM configuration and then check the address editor. You should see whether the BRAM address was assigned. If you find assigned see axi_bram_ctrl_0 OffsetAdress and the Range then the BRAM was created and mapped to the memory. 2. Writing and reading from BRAM requires a clock signal. Check Xilinx templates for BRAM which you can access inside the Vivado. I am not sure that the code you've used to write into BRAM does anything. 3. You don't use an absolute address in your HDL when BRAM created in Vivado. Vivado maps the address 0x4000_0000 to 0. So you can start from the address 0 and it will be the lowest address of the BRAM. If your don't use Vivado then you will need to define your block in HDL and include addresses, and many other parameters. 4. The C-code in SDK should use BRAM address from the file parameters.h. You just need to use XPAR_AXI_BRAM_CTRL_0_S_AXI_BASEADDR as the begining of the BRAM address space. 5. You can treat BRAM as RAM meaning that all read/write operators are the same. For example you can copy BRAM content into the RAM: for(i = 0 ; i < BRAM_SIZE ; i++) *(destination + i) = *(source + i); where source = XPAR_AXI_BRAM_CTRL_0_S_AXI_BASEADDR Disclaimer: always read documentation, whatever you find on Internet might not be correct. Good luck!
  25. 2 points
    Hi @akhilahmed, In the mentioned video tutorial, the leds are controlled using "xgpio.h" library but the application is standalone. If you want to use a linux based application you have to use linux drivers for controlling. In the current Petalinux build, which is used in SDSoC platform, UIO driver is the best approach. Steps: 1. Vivado project generation: - Extract .dsa archive from /path_to_sdsoc_platform/zybo_z7_20/hw/zybo_z7_20.dsa - Launch Vivado - In Tcl Console: cd /path_to_extracted_dsa/prj - In Tcl Console: source rebuild.tcl - In this point you should have the vivado project which is the hardware component of SDSoC platform. Open Block Design. Change to Address Editor Tab. Here you will find the address for axi_gpio_led IP: 0x4122_0000 2. Petalinux UIO driver: - Launch SDx - Import zybo-z7-20 SDSoC platform - Create a new SDx linux based project using a sample application (e.g. array_zero_copy) - Build the project - Copy the files from /Dubug/sd_card to SD card - Plug the SD card in Zybo Z7. Make sure that the JP5 is set in SD position. Turn on the baord - Use your favorite serial terminal to interact with the board (115200, 8 data bits, 2 stop bits, none parity) - cd to /sys/class/uio - if you run ls you will get something like: uio0 uio1 uio2 uio3 uio4 uio5 - Now you have to iterate through all these directories and to search for the above mentioned axi_gpio_led address: 0x4122_0000 - For example: cat uio0/maps/map0/addr will output: 0x41220000, which means that the axi_gpio_led can be accessed using linux uio driver through uio0 device. - Code: #include <stdio.h> #include <stdlib.h> #include <sys/ioctl.h> #include <sys/mman.h> #include <stdint.h> #include <unistd.h> #include <fcntl.h> #define UIO_MEM_SIZE 65536 #define UIO_LED_PATH "/dev/uio0" void UioWrite32(uint8_t *uioMem, unsigned int offset, uint32_t data) { *((uint32_t*) (uioMem+offset)) = data; } uint32_t UioRead32(uint8_t *uioMem, unsigned int offset) { return *((uint32_t*) (uioMem+offset)); } void led_count_down(uint8_t *ledMem) { uint8_t count = 0xF; uint8_t index = 0; for (index = 0; index < 5; index++) { UioWrite32(ledMem, 0, count); count = count >> 1; sleep(1); } } int main() { // Set Leds as output int led_fd = open(UIO_LED_PATH, O_RDWR); uint8_t *ledMem = (uint8_t *) mmap( 0, UIO_MEM_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, led_fd, (off_t)0); UioWrite32(ledMem, 4, 0x0); // Set all leds as output while(1) { // Start led count-down led_count_down(ledMem); } return 0; } - Build the project and copy the content of Debug/sd_card on SD sd_card - Power on the board and connect to it using a serial terminal - run the following commands: mount mmcblk0p1 /mnt cd /mnt ./project_name.elf - Result: A countdown should be displayed on leds.
  26. 2 points
    You're welcome! I am glad it is working. Yes, this thread should help others trying to run the Pcam 5C demo on Zybo Z7. Best Regards, Ionut.
  27. 2 points
    attila

    AD2 over voltage :-(

    Hi @peter taylor This was a ferrite between the Analog Discovery and USB ground. Supposed to filter noise from USB cable/PC which acted as a fuse... You can solder a simple short instead this ferrite. Hopefully only this was damaged. Be careful. The devices and circuits should have the same ground. The AD ground is connected to the PC ground over the USB cable.
  28. 2 points
    Flux

    VGA Pmod Tutorials

    The VGA tutorials have been updated with support for the Basys 3 and Nexys Video as well as Arty: https://timetoexplore.net/blog/arty-fpga-vga-verilog-01 I'm currently adding SVGA (800x600) support as well as working on more advanced effects. All the Verilog is available under the MIT license on GitHub: github.com/WillGreen/timetoexplore I look forward to sharing more projects with the community soon. Will
  29. 2 points
    elodg

    Nexys Video "Feet"

    https://www.fastenal.com/products/details/0146057 https://www.fastenal.com/products/details/28783
  30. 2 points
    Ciprian

    Zynq book - tutorial 5 Zybo Z7

    Hi @n3wbie, Th working project is attached. what you have to take in to account when using this audio codecs with Digilent products is that you need to configure the codec (using I2C) as well as receive the samples using I2S IP core. Basically one is for the control of the codec and the other one is to receive the samples. I have written a small driver for both the I2S core and the I2C SSM2603 which is in the source files of the SDK project (in the sdk folder) which configures the registers for the codec and I2S IP core; the documentation for the codec can be found here. The IP core has not yet been documented which is the main reason we have not added it to the Digilent vivado-ip library, but it needs a 100MHz input for it to be able to synthesize the 12.228 MHz MCLK and the subsequent clocks for the I2S protocol. The demo project reads the buttons and based on the ones you press it will: BTN0 - Record 1s BTN1 - Set Mic input BTN2 - Set Line In input BTN3 - Playback 1s The project is not really optimized so it uses a variable "RecSamples", allocated to the stack memory which holds the recorded samples(48000 samples representing 1s at a 48KHz sampling rate) and it is also used fro play back, so don't press play back before record. The rest should be easily traceable from the comments in the driver and the main source code. If you have any other questions feel fr to ask. Ciprian ZyboZ7Audio.zip
  31. 2 points
    xc6lx45

    Diving in

    ... a slightly longer answer, if anybody is interested (analog mixing with square wave LO): One way is to look at the Fourier series of the square wave as a sum of sines at frequencies f, 3f, 5f, 7f, ... and to a lesser extent 2f, 4f, 6f from implementation imperfections. Then think of the mixer as linear multiplier, and use superposition (the distributive property of multiplication) for a*(b3+b5+b7+...) = a*b3+a*b5+a*b7+... Hint, if anybody wants to formally go through the math, it gets much less messy with cos(x) = (exp(ix)+exp(-ix))/2 aka DeMoivre. So you really get multiple frequency translations instead of one. What remains to be done is to manage the input signal energy at those frequencies I don't want, with a filter or narrow-band antenna. In the digital world, you'd always use a sine wave.
  32. 2 points
    Hi @JColvin, I'll write a detailed article on our website during next month (with more screenshots/video). Below some more details: - OpenScopes are connected to a BeagleBone via a powered hub. On the same board there's a service that connects to the 3 scopes and exposes them via a REST API. The service basically forwards commands (Digilent Instrumentation Protocol) to the scope via USB and sends back the responses, making sure valid responses are sent/received before forwarding. The REST API also offers some control commands (e.g. check status). The idea is similar to the "Digilent Agent", but it it is multidevice and it is written all in Python. aiohttp (asyncio) is used for the server code. The firmware has been slightly adapted so that trigger from device 1 is sent to LA of device 2 and 3, the trigger from device 2 to 1 and 3, etc. This allows to configure any device analog channel as a trigger source for all devices. - The desktop application interacts with the REST API (also via aiohttp), but offering a unified experience so that the user feels there's a single device with 6 channels. It is written in Python, using PyQt/PySide for the GUI part. It offers two functionalities, the "scope view" (screenshot above) and the "recorder view" (we're still polishing the last bits of it). It also has a dark/light theme and it's multilanguage. Best regards, Gerard
  33. 2 points
    Hi @NYSD It is under development.
  34. 2 points
    attila

    Math on FFT traces

    Hi @lab!fyi The Script/Spectrum is added to the Help of beta version. Please use the Help of the application since this is the most up to date resource. https://forum.digilentinc.com/topic/8908-waveforms-beta-download/ You could use Ctrl+Space, code completion: https://forum.digilentinc.com/topic/15433-more-meta-data-wanted/?do=findComment&amp;comment=37724 Beside this the code is JavaScript: http://www.ecma-international.org/publications/standards/Ecma-262.htm https://www.w3schools.com/jsref/jsref_obj_math.asp For next software version added support to set trace data from script.
  35. 2 points
    JColvin

    Zedboard 3.3V Aux

    Hi @JeffL, For the Rev D version of the board, this pin (D32 on the FMC) will also be a VCC 3.3V supply, much like it is for @zygot's Rev C. From the specification for VITA 57.1, this pin is "a 3.3V auxiliary power supple available for IO Mezzanine module use and is not intended to provide primary power to the module but rather to accommodate system management functionality which might need to operate even if the onboard power conversion circuitry fails." Based on rule 5.101 though, we (Digilent) have chosen to service this pin by using the main 3.3V line. So, the short answer to your question is that the pin specifically on the Zedboard is a 3.3V source, though from my understanding this auxiliary supply should not be connected with any 3.3V primary paths on the mezzanine side. Thank you, JColvin
  36. 2 points
    awang735

    PMOD DA1 to zedboard

    Nevermind, i downloaded the digilent board files from https://reference.digilentinc.com/learn/software/tutorials/vivado-board-files/start?redirect=1 and was able to connect the pmod ip via the board tab in ip integrator like it says in the walkthrough
  37. 2 points
    D@n

    Default Power-up Value of Registers

    @Foisal Ahmed, I'm not sure you understand what you are asking. Uninitialized logic values in Xilinx designs are already 1'b1's. This has caused me no end of grief in the past. Simulations treat initial values differently. Most simulations will treat an uninitialized value as an unknown until it is set. This is industry practice. I know Verilator tries to set unconstrained initial values to be random numbers. This is an exception to the industry practice that is done for performance reasons. The discrepancy between Verilator and Xilinx has been the root of much grief--since uninitialized things that work in Verilator don't always work in Xilinx. Depending upon a default initial value for registers within a design, however, is poor practice. The better approach is to force registers that need initial values to whatever initial value they should have. In Verilog, this is done using an 'initial' statement. In VHDL this can be done in the declaration statement, where the register is declared in the first place. Xilinx FPGA's by design will not release your design from its initial state unless all of your registers have their declared initial values. Were you to force all LUTs in a design to be 1'b1 initially, you would break any vendor supplied IP (i.e. DDR3SDRAM core, etc) you might be working with. Can you explain more of what you are trying to accomplish? Perhaps there's a better solution for what you wish to do. Dan
  38. 2 points
    BogdanVanca

    programming guide of zynq

    Hello @Ram, Please check this link : https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-getting-started-with-zynq-server/start "This guide will provide a step by step walk-through of creating a Zynq based hardware design using the Vivado IP Integrator that will build over the Getting Started with Zynqguide by making use of the on-board Ethernet port and GPIOs for the Zybo FPGA board.". You can start from here, and use the same hardware logic but different type of application for uart, spi etc. Best Regards, Bogdan Vanca
  39. 2 points
    jpeyron

    Zedboard Zynq 7000 XADC Header

    Hi @farhanazneen, I used the Analog Discovery 2 which has the 2x15 Flywires: Signal Cable Assembly for the Analog Discovery without issue. Each signal wire is 260mm± 20. thank you, Jon
  40. 2 points
    Notarobot

    How to read from SD card on ZYBO

    Hi shahbaz, If you are Ok using micro SD card adapter embedded in Zybo I would recommend to use it with the driver xsdps provided by Xilinx. Please note that it is connected and intended for use by PS not PL. The driver is located in Vivado library \embeddedsw\XilinxProcessorIPLib\drivers\sdps In Vivado the only thing is needed is enabling SD card in the processing system. Everything else is done in SDK. There you will need to add library xilffs to the BSP. File system and functions are described in here Good luck!
  41. 2 points
    BogdanVanca

    Where download 2015.4

    Hello @Bien, Please check this link : https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/sdx-development-environments/archive.html. Best Regards, Bogdan Vanca
  42. 2 points
    D@n

    XADC and the FFT

    @farhanazneen, I don't have @mohamed shffat's code, nor have I seen it. Therefore, I would struggle to answer your question regarding how he accomplished (or didn't accomplish) this task. As I recall, I've posted all of the details of my own solution on zipcpu.com, although several of the components were spread across multiple different blog posts. I think I've already linked to these above, though, so if you are missing some part of my own solution, please speak up. By the way, my solution is done in completely in Verilog. I haven't used the XADC (yet). It's also highly dependent upon what I call a debugging bus: a concept explored (and built) on my blog as well. Dan
  43. 2 points
    Ram

    vivado 2017.4

    Thank-you melisha ,,it is working Ram
  44. 2 points
    zygot

    Beginner DSP Projects

    Yes Dan he certainly would agree with your advice. Test, verify, test, verify. Let it be your mantra. Test and verify the main result that you are looking for. Test and verify all of the component parts ( particularly in logic ) in case you want to reuse any modules or components. Test and verify corner cases. Test and verify consistency of results between all of the implementations. For the logic implementation there will be more subtle and complicated aspects to consider and test for. Assume nothing. If all of this doesn't sound like fun ( I'm taking the long view by using that word) ... perhaps consider a different way to spend your free time. Oh, and I forgot to mention the most important part. Don't do it for self-defense. You can learn a lot more during the test and verification stages... you know, the part where most people have gone on to other things assuming that everything works, than you can learn during the basic design processes. Testing and verification generally requires another level of awareness to issues not obvious in the original conceptual stages. That's my experience.
  45. 2 points
    zygot

    Zybo serial port in Ubuntu

    @jacobfeder, Here's some handy tips for using serial ports in Linux Open a terminal window in Linux Find out what USB devices have been enumerated: Enter the command 'lsusb' to see a list of enumerated devices. You can get more information by adding -v or -vv command line arguments Find out what Serial port devices are available: Enter the command 'dmesg | grep tty' to see what serial ports are available and what name to use. If you are not sure what device is what try using the dmesg command with the USB UART disconnected and again with it connected. If you run Putty and hit the open button you will either get the screen that you mention if Putty successfully connects to an available device with the specifications you assigned to the current Putty session. Otherwise you get an error message and Putty exits. Now that you have a connection all that's left is to have a conversation between the computer and whatever is connected on the other end,. If what's connected on the other end is listening, try typing into the Putty terminal window and hit enter. If the connected device is able to transmit you should get some sort of reply back. Of course if Putty is connected to the wrong serial port that's a problem. Here is an edited example session telling me to use Putty with ttyUSB0: lsusb Bus 005 Device 003: ID 067b:2303 Prolific Technology, Inc. PL2303 Serial Port dmesg | grep tty console [tty0] enabled serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A 00:0b: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A usb 5-2.1: pl2303 converter now attached to ttyUSB0 happy communicating!
  46. 2 points
    Nope, 32b is not supported by the Xilinx tools. But you are right what matters is not the architecture of the host but rather the guest, I messed that up 😕 You'll need this one.
  47. 2 points
    attila

    Analog Discovery 2 vs Raspberry Pi 3

    Hi @Phil_D @rprr The problem is that the USB IN packets/bytes are randomly lost/altered. I tried various kernel options, limiting the USB transfer rates but had no luck. The data corruption reduced from one in 1-60 seconds to one in 10-60 minutes, which it is still not good... It seems that the root of the problem is in the low level FTDI library, kernel or USB modules, or between them... The Analog Discovery is working fine with other SOCs but not with the RPi. I also notice issue with the USB keyboard I use with the RPi, time to time key presses are not received. You can find many similar RPi issues on the net: https://www.raspberrypi.org/forums/viewtopic.php?f=28&amp;t=5249&amp;sid=8839659cb92b7475fa196b2fad775d9f&amp;start=250 http://www.ftdicommunity.com/index.php?topic=40.0
  48. 2 points
    mohammadhgh

    Zybo z7-20 Zynq Presets

    Hi @Mahesh, As @jpeyron said in the post marked as accepted solution, the Zynq processing system will be configured with the board presets when you first add the Zynq processing system IP core to the block design and run the block automation task from the green message that appears! Just remember to keep the Apply Board Preset option checked as shown in he picture. So this means if you are using the pre-built block design from the example project, a possible solution can be to remove the existing Zynq processing system block and adding a new one!
  49. 2 points
    attila

    Analog Discovery 2 vs Raspberry Pi 3

    FTDI USBs like AD, AD2, DD are not working with RPI model B (1,2,3) data packets/bytes are randomly lost. The EExplorer with different USB controller is working fine on these. All devices are working with other embeddeds: Zed, Zybo, BeagleBone… According reports AD is working with the original RPI model A and probably Zero because it has similar chipset/USB. The problem seems to be with FTDI or RPI B USB, library or hardware. You can find such comments regarding RPI problems with other devices too. Unfortunately we couldn't remediate this problem.
  50. 2 points
    hamster

    MMCM dynamic clocking

    Hey, something else I just saw when reading the clocking guide was: MMCM Counter Cascading The CLKOUT6 divider (counter) can be cascaded with the CLKOUT4 divider. This provides a capability to have an output divider that is larger than 128. CLKOUT6 feeds the input of the CLKOUT4 divider. There is a static phase offset between the output of the cascaded divider and all other output dividers. And: CLKOUT4_CASCADE : Cascades the output divider (counter) CLKOUT6 into the input of the CLKOUT4 divider for an output clock divider that is greater than 128, effectively providing a total divide value of 16,384. So that can divide a 600 MHz VCO down to 36.6 kHz.