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  1. attila

    WaveForms beta download

    3.15.5 digilent.waveforms_beta_v3.15.5_64bit.exe - Scope, Zoom view zoom options - more progress dialogs - recording for LabView VIs, go to MSO Read Block Diagram and increase the analog and digital array size as needed 3.15.4 digilent.waveforms_beta_v3.15.4_64bit.exe Added: - import support for Multisim CSV export: Transient to Scope, AC to Network Analyzer - time/data interpolation for import samples (Scope, Spectrum) - Scope/FFT graphics speedup for large number of BINs - Scope quick measure for large number of samples Fixing: - last word was not marked when: the SP
    4 points
  2. For anyone else out there who's struggling with DDR3 SDRAM on the Arty A7, here's a project for Vivado 2019.2 that builds out-of-box and successfully reads / writes (via the MIG user interface) to / from memory. Hopefully this'll save someone the pain I went through figuring out how to interface with the DDR-SDRAM via Verilog. Arty-SDRAM.zip
    3 points
  3. Hello @WillTx, 1. There is an IP for Pmod MTDS with the drivers you need to make your Pmod MTDS working. It also contains 10 demos from which you can learn a lot. You can find it here : https://github.com/Digilent/vivado-library/tree/master/ip/Pmods/PmodMTDS_v1_0. You need to download the entire vivado-library (from here) then follow the tutorial for using Pmod IP cores in Vivado. 2. Your block design after adding the Pmod MTDS IP: 3. You can use the board flow to automatically connect to JB Pmod connector without a XDC constrain file (as it shows in the tutorial at
    3 points
  4. Hi, as a simple (oversimplified?) answer, designing for higher clock speed requires higher effort (possibly "much" higher effort), and the resulting optimizations make the code harder to work with. Using the clocking wizard to generate a 500 MHz PLL is easy (try it). But writing logic at those frequencies is a different story (e.g. try to implement a conventional counter that divides down to 1 Hz. Why do all those XYX_CARRY signals show up in the timing report already at synthesis?). You also need to distinguish between what is feasible in plain logic fabric, and what can be done wit
    2 points
  5. I'm not competent to lecture on software best practices but this topic merits discussion. Perhaps a few comments will kick one off and lure people better qualified than me to participate. There are ways of accessing hardware from software applications in just about anyway you choose. That doesn't mean that hey are all ideal or even acceptable. As a rule, using well worn libraries are preferred. In general they are not the fastest or the easiest or most simple way to interact with hardware. For safety, consistency, and orderliness they are better than reference by address. One concept is
    2 points
  6. I do have to say that I was concerned when I initially clicked on this thread...but I think I'll let it stay. šŸ˜‰ Please let us know if you have any questions about using the products! Thanks, JColvin P.S. I definitely sent this forum thread to our Scopes and Instruments product manager with minimal context to see what her reaction is.
    2 points
  7. It's been too long ago but I do remember taking the scenic side journey into investigating performance of floating point on Intel processors. Mostly what I remember is that it was interesting, informing, had unexpected surprises and was a valuable exercise. Just recommending the excursion to anyone interested in 'bit exactness'.
    2 points
  8. I've just posted my holiday project to Github - Rudi-RV32I - https://github.com/hamsternz/Rudi-RV32I It is a 32-bit CPU, memory and peripherals for a simple RISC-V microcontroller-sized system for use in an FPGA. A very compact implementation and can use under 750 LUTs and as little as two block RAMs - < 10% of an Artix-7 15T. All instructions can run in a single cycle, at around 50MHz to 75MHz. Actual performance currently depends on the complexity of system bus. It has full support for the RISC-V RV32I instructions, and has supporting files that allow you to use the R
    2 points
  9. @Vishnuk Here's a tutorial that discusses how to build both UARTs and FIFOs. Dan
    2 points
  10. I've spent some time since my first post trying to figure out what's in store for users with Vitis. With Vivado 2019.2 + Vitis you still need a Linux host to develop Petalinux applications. It was a chore, but I did manage to install Petalinux 2019.1 onto a Ubuntu 18.04 VM running in HyperV on my Win10 Pro box. This PC has 32 GB ram so I can allocate 8 GB to the VM. I haven't as yet actually created a project with the Petalinux tool this way yet. My plan is to wait and see how well Xilinx develops the tools with the next release before moving to 2019.2 and the new paradigm. Note that Viva
    2 points
  11. Hello Frankly and welcome to our forum. Here are 2 patches that can be applied on top of a Petalinux 2019.1 project to allow reading the OTP MAC and configure it to do so. You can try applying them on 2018.2. Message us back if you have any issues. Cosmin 0001-Z7-20-allow-reading-MAC-address-from-OTP.patch 0002-Z7-20-use-OTP-MAC.patch
    2 points
  12. Hello @Bryan_S, Here is a demo project for Cmod S6 from https://reference.digilentinc.com/reference/programmable-logic/cmod-s6/start. I looked into the source files and there is clk_gen_50MHz.vhd. You can see in the top.vhd file how the clk_gen_50MHz is instantiated and used. I don't know what is the clk16x in your code, but here are some source files for serial port serialport_v3.zip The sources are for Nexys4 DDR which has a 100 MHz system clock. But in your case, if you use the clk_gen_50MHz, you'll have a 50 MHz clock instead of 100 MHz, 9600 baud rate, as shown in
    2 points
  13. Hello @bitslip, Things are a little bit more complicated. Indeed, for changing the resolution you have to rewrite some registers. But you also need to make sure that the Video Trimming controller ip generates the required constants for you resolution. I wouldn't recommend to write all the needed registers from the control interface (it would be agonising) Instead I would go with the existent logic for changing the resolution, which is adding a new structure with all the register values. As an example, you can check the OV5640.H file. I much simple and quicker solution would be to use our
    2 points
  14. Hi @attila Thank you again for all the support you've provided me for the past weeks. I am now capable of receiving more than 409 characters using the Wrapper I created base from your example. It uses the Record acquisition mode and I set the buffer size to 3 million for now. I'll increase it when the need arises. I used 1 UART controller and branched out its Tx pin to 2 DIO pins of the AD2 (DIO #0 & 1). I transmitted 500 characters: (If Record mode is not the acquisition mode, the received result will be blank) For DIO # 0, it received: with a length of:
    2 points
  15. I own three of FMC equipped boards that you mention and frequently use at least one on a regular basis. Just for arguments sake; lets say that I want to design my own FMC mezzanine card using all of those differential pairs. Where do I find the trace routing report letting me know what the trace lengths are for the Genesys2, Nexys Video and Zedboard?
    2 points
  16. Hi all, Quick update here. I've got binaries built for Mac and Linux (Ubuntu) and have updated the documentation to link to them. You may also download the Windows, Mac or Linux binaries by following the links I just gave you. If you encounter any issues whatsoever, submit in issue on the GitHub page and I'll set to fixing them straight away. Regards, AndrewHolzer
    2 points
  17. Hey Paolo, I'm glad you found my videos helpful! I've been working on other projects, but if you have any other ideas for videos that you would find helpful let me know. Kaitlyn
    2 points
  18. Yes, that cable is suitable from connection perspective. Still, there are functionality issues that you must be concerned. Most of the Pmods communicate using protocols like SPI, I2C, etc. This is specified on the Pmod datasheet. This means that the pins corresponding on the maching connector (on the system board) must implement that specific functionality. Normally using a FPGA board will be easier to configure Pmod pins to the needed functionality. Still, as you use a microcontroller board, this might be more difficult or even impossible. Please check if the pins associated
    2 points
  19. attila

    SDK and measurements

    Hi @Zebel http://www.radioradar.net/en/measurements_technics/oscilloscope_measurement_fundamentals.html
    1 point
  20. Thank you! The trigger is the key point to detach the plug!
    1 point
  21. JuanCar

    Triggering the mains failure

    dear @attila, I followed your recommendations and now is working perfectly. I can measure the mains with my home made 1000V isolated probe. You can see the result. Thanks a lot...
    1 point
  22. Hi @mjk.kirschner Thank you for the observation. It will be fixed for the next software release. - To overcome this you can add two SPI interpreters, one for MOSI and one for MISO. - You could also change the Format for MISO from Script, by running: Logic.Channels.SPIMISO.Format.text = "Decimal" As mentioned in the installer the driver is only required for older macOS versions. Such warning/info is given by the WF application when no device is detected:
    1 point
  23. Hi @jowell88 I have not see such issue so far. Which software version are you using? Try opening WF in safe mode. This will open the app without loading the last settings, file history...
    1 point
  24. I've developed a few audio and video example designs for the Nexys Video in VHDL and posted them here: https://github.com/amb5l/tyto_project I am planning to expand on the HDMI IP to make it more general purpose, and add DisplayPort eventually. There is more stuff in the pipeline.
    1 point
  25. Had a hack at it... tested working on BASYS3 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity msg_repeater is Port ( clk : in STD_LOGIC; btn : in STD_LOGIC; tx : out STD_LOGIC; led : out STD_LOGIC_VECTOR (3 DOWNTO 0)); end msg_repeater; architecture Behavioral of msg_repeater is constant char_t : std_logic_vector (7 downto 0) := "01010100"; constant char_e : std_logic_vector (7 downto 0) := "01000101"; constant char_s : std_logic_vector (7 downto 0) := "01010011"; constant char_space : std_
    1 point
  26. @attila, @MarceloNotThePLCguy was unable to check on this during the last few days because we were operating. He's currently out of the office for a bit. We will have an opportunity in the coming weeks to try some of your recommendations. Thanks for your help! We'll keep you posted.
    1 point
  27. Hello @ahmetnc, It is not possible because on the JTAG-SMT3 the BDBUS4 connection is missing. The 2 ports are not the same, you cannot use UART for JTAG.
    1 point
  28. Please take a look on this forum topic, it might help you:
    1 point
  29. @Bobby29999, Ahm, no, that's not a "physical reality". Pseudorandom was an understood input to the algorithm, if you had wanted true randomness that would've been a topic in and of itself. By "physical reality" I'm referencing something physical--something that you can see, touch, and either measure or interact with in the real world--not in the computer algorithm world. The "physical reality" should define your data rate requirement and the number of bits you need both in terms of inputs and outputs. The "physical reality" would also explain why you are using an FPGA in the first
    1 point
  30. pascalSarto

    CAN bus protocol

    Great! With this, your tool is even more awesome. Thank you so much.
    1 point
  31. you can single-step through the FSBL, so that's probably a "yes". Note that documentation may become an issue (regardless of webpack or paying license): The ARM core is Xilinx-customized, so the ARM documentation helps only to a point. For example, non-standard use of the cache controller is such a topic. If you do want to use Xilinx libraries (but no OS) then forget everything I've written. It's a straightforward design flow => click through the menus to generate a new e.g. "Hello World" SDK project in standalone mode. Use an unmodified FSBL that loads your application. It's the
    1 point
  32. rfx

    Arty-Z7-20-base-linux Build

    And why dont you add a documentation for the display shield. I think that the spi_ss should be assigned to the default location (J6 SPI Connector). someone who uses the display-shieled can alter his board-files. the change to spi_ss is not documented (well) and took me a day to find out. the J6 connector is the documented SPI interface of the board and with the problem of the interchanged pins it simply does not work.
    1 point
  33. zygot

    Cmod A7 massive GND noise

    @steddyman Measuring ground noise is not trivial but let's assume that your measurements are correct. You don't provide a lot of details about your prototype. Are you using a custom PCB with headers for plugging in your CMOD? Are you using a lot of the CMOD IO? There were a lot of design choices made for the CMODs that aren't optimal for prototyping, which is odd as this is clearly what the modules are intended for. Having a single GND and Vcc pin is one of those choices that are unfortunate. This doesn't make the modules a bad product but might well limit what kinds of things t
    1 point
  34. Seen the problem. You need to define both o1[0] and o1[1] in your constraints, as o1 is a vector of two signals. At the moment you are trying to attach both signals to the same pin, hence the error. Ditto for o2, o3 and o4.
    1 point
  35. JColvin

    PMODs - Spec 1.2.0

    Hi @andresb, I apologize for the delay. The best way to determine if they are complaint with specification 1.2.0 is by looking at their respect Resource Center (such as the Pmod AD1). On the right-hand side under Electrical, you will see the Specification version that the Pmod is currently compliant with. The Pmod Interface Specification 1.2.0 is available directly here: https://reference.digilentinc.com/_media/reference/pmod/pmod-interface-specification-1_2_0.pdf. Let me know if you have any questions about this. Thanks, JColvin
    1 point
  36. Hey All, We recently posted a new version of WaveForms Live which ads some new features. This blog post lists all the changes in the update.
    1 point
  37. Hi @sgrobler, I think it's entirely possible to include a timestamp in a log header when starting a session from a connected host. I'll put this on my list of additions & fixes, put some thought into a proper solution and get to work on it. I'll personally message you once I've made the changes (and you'll probably see a blog post about them as well). Regards, AndrewHolzer
    1 point
  38. Hi @Takashi "The Yaka mein", I apologize for the delay. I am not certain why that particular power supply is not included for the Japan export version of the kit that Xilinx makes. Your guess that it could be a certification issue would make sense, though I do not know this for certain since that particular power supply isn't sold directly on our website as per this forum thread here. I will ask and find out if somebody at Digilent happens to know the reason the power supply would be excluded from the Japan export version, though it may be better to reach out to Xilinx as they are the one
    1 point
  39. Hi @Lesiastas No. You should leave it as it is. From your question I thought you are using the WF application. To reduce the device connection/opening latency use the on-close param. To 'intelligently' stop the recording process you could analyzer the received data chunks (samples) and when there is no UART activity on the lines for X time (N samples). This depends on you project...
    1 point
  40. Hi @Lesiastas As initialization when you application starts, before calling open set the following option to 0/Run: dwf.FDwfParamSet(DwfParamOnClose, c_int(0)) # 0 = run, 1 = stop, 2 = shutdown 2 - open always takes 'long' time (~300ms) since the device is powered down on close and reprogrammed on each opening 1 - device remains powered but the outputs are stopped on close, this takes a few ms on open/close * 0 - device continues the output after close (waveform, pattern generation, supplies), the open/close are fast * *The first open after power up will take 'long' time sinc
    1 point
  41. Bianca

    Evaluation boards

    Hi @mariushvn, There is no difference between them. The original was Artix-7 35T Arty FPGA Evaluation Kit and then we re-branded the Arty category by sticking to the same form factor but with different FPGAs (artix, spartan, zynq). To make sure there won't be confusion between the products, the original Arty is called now Arty A7. The new thing is that it can be found now also with a bigger FPGA, the 100T not only with the 35T how it was the original. Best regards, Bianca
    1 point
  42. Hi @Takashi "The Yaka mein", We have a 3D model of the Pmod RS485 available in it's Resource Center on the right hand side under Documentation. Let me know if you have any questions. Thanks, JColvin
    1 point
  43. Hi @Phil_D You can use the RangeSet function to select the gain and the RangeGet function to get the calibrated value, full swing. All the Set/Get function in the API behave like this. Normally it is not recommended to go with full swing input signal since clipping can occur. Like when the scale top is 5.561V and the input signal reaches 5.562V dwf.FDwfAnalogInChannelEnableSet(hdwf, c_int(-1), c_bool(True)) dwf.FDwfAnalogInChannelRangeSet(hdwf, c_int(-1), c_double(5.0)) dwf.FDwfAnalogInConfigure(hdwf, c_int(1), c_int(1)) range1 = c_double() range2 = c_double() offset1 = c_double(
    1 point
  44. @rivermoon, Go for it, and good luck! I've found that wireshark was very useful when debugging network interactions. Let me take a moment and suggest you look into it and try it out. Also, I'd love to hear back from you regarding your success when everything works like it should. So often these forum posts only discuss problems and we never hear successes here. That said, it's your call what you want to share. Dan
    1 point
  45. Thanks for pointing that out. That does make it pretty confusing. I'll contact the forum developers to see if there are options we can tweak to turn that off.
    1 point
  46. @ManserDimor Here's a general rule of thumb. Differential traces, whether laid out as differential or not must be length matched as best as possible. High speed bussed signals are usually length matched but normally this isn't nearly as critical as differential signalling; and this is usually done with a maximum data rate in mind. Everything else is usually assigned to the auto-router. Hand tuning traces is expensive and time consuming and usually there are a limited number that can be optimised with high ball count FPGA footprints. Usually, the focus is on external memory like DDR.
    1 point
  47. JColvin

    UART echo code in vhdl

    Hi @Vishnuk, This sounds a bit like a class project, so while I won't be just providing the code, I can try to answer specific questions that you may have. In the mean time, I would recommend taking a look at this thread where the user worked through receiving signals from a UART input to modify the LEDs present on the Basys 3. A quick internet search also brought up a VHDL UART echo project, though it was designed for a different board and probably different UART settings than you want. Thanks, JColvin
    1 point
  48. Hi, Do you have BSP support for petalinux 18.03 or later? BR, Paul Grant
    1 point
  49. Hello! Welcome to the Digilent Forums! All of us here, both Digilent Staff and our incredible community members, are excited to be able to help you out with your project. That being said, we are not the ultimate experts on Embedded Linux. A couple of us have a decent amount of experience, but unfortunately we cannot guarantee that we can identify the issue and have the solution to your problem for your exact distro, drivers, board, and application. We will try to help out the best that we can, but it may take some additional time to provide feedback on any questions that you may hav
    1 point
  50. Hello @RBS, The problem with the spaces on the path is well known for Vivado. Also the SDK won't work if the path is too long. If you store your project in a work directory that has more than one or two sub folders, won't work. The best and safest way is to work on desktop. You are not the only one who encountered this problem so don't worry. Best regards, Bianca
    1 point