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  1. 4 points

    WaveForms beta download

    3.13.21 digilent.waveforms_beta_v3.13.21_64bit.exe Added: - Logic Analyzer Export All Events - AD2 7th device configuration Fixed: - Script plot with high offset/range ratio 3.13.20 Windows: digilent.waveforms_beta_v3.13.20-2_64bit.exe digilent.waveforms_beta_v3.13.20-2_32bit.exe MacOS: digilent.waveforms_beta_v3.13.20.dmg Linux 64bit: digilent.waveforms_beta_3.13.20_amd64.deb digilent.waveforms_beta_3.13.20.x86_64.rpm Linux ARM 64bit: digilent.waveforms_beta_3.13.20_arm64.deb digilent.waveforms_beta_3.13.20.aarch64.rpm Linux ARM 32bit: digilent.waveforms_beta_3.13.20_armhf.deb digilent.waveforms_beta_3.13.20.armhf.rpm Patch for RaspberryPi4B ERC 2 with Digital Discovery and Analog Discovery 1/2 with 2nd device configuration. Replace frequency/bandwidth limits option with warning. Fixing cleanup process, random WF app crash. 3.13.19 Windows: digilent.waveforms_beta_v3.13.19_64bit.exe digilent.waveforms_beta_v3.13.19_32bit.exe MacOS: digilent.waveforms_beta_v3.13.19.dmg Linux 64bit: digilent.waveforms_beta_3.13.19_amd64.deb digilent.waveforms_beta_3.13.19.x86_64.rpm Linux ARM 64bit: digilent.waveforms_beta_3.13.19_arm64.deb digilent.waveforms_beta_3.13.19.aarch64.rpm Linux ARM 32bit: digilent.waveforms_beta_3.13.19_armhf.deb digilent.waveforms_beta_3.13.19.armhf.rpm Fixing ERC 0x2 Linux and Raspberry Pi 4 B with AD, AD2, DD 3.13.18 digilent.waveforms_beta_v3.13.18_64bit.exe digilent.waveforms_beta_v3.13.18.dmg digilent.waveforms_beta_3.13.18_amd64.deb digilent.waveforms_beta_3.13.18.x86_64.rpm - Logic Analyzer - I2C interpreter remove restart, stop timing requirement - name option for Add Signal dialog - fixing analog curve in idle state and signed representation - fixing first value alignment - Select option for Event view - Cursors view: - name field - positioning plot on cursor row selection - Workspace: - multiple file selection for Extract - Compare tool based on capture device serial number 3.13.17 digilent.waveforms_beta_v3.13.17_64bit.exe Fixing know bugs 3.13.16 digilent.waveforms_beta_v3.13.16_64bit.exe Changed: - Network Analyzer rate improvement, Custom offset sweep - Logic Analyzer allowing large single captures Fixing know bugs 3.13.14 digilent.waveforms_beta_v3.13.14_64bit.exe Changed: - Saving workspace/project to temporary file first - Impedance Analyzer rate improvement Fixing known bugs 3.13.13 digilent.waveforms_beta_v3.13.13_64bit.exe Adding: - Logic Analyzer Import Binary, Script Logic.AddTab Fixing known bugs 3.13.12 digilent.waveforms_beta_v3.13.12_64bit.exe digilent.waveforms_beta_v3.13.12.dmg digilent.waveforms_beta_3.13.12_amd64.deb digilent.waveforms_beta_3.13.12.x86_64.rpm digilent.waveforms_beta_3.13.12_armhf.deb Fixing known bugs - Digital Discovery Logic Analyzer - application arguments 3.13.11 digilent.waveforms_beta_v3.13.11_64bit.exe Added: - FDwfDigitalSpiIdleSet Fixing known bugs 3.13.10 digilent.waveforms_beta_v3.13.10_64bit.exe digilent.waveforms_beta_v3.13.10.dmg digilent.waveforms_beta_3.13.10_amd64.deb digilent.waveforms_beta_3.13.10.x86_64.rpm Added: - Logic Analyzer: - Manchester interpreter - Trigger on CAN data Fixing known bugs 3.13.8 digilent.waveforms_beta_v3.13.8_64bit.exe digilent.waveforms_beta_3.13.8_amd64.deb digilent.waveforms_beta_3.13.8.x86_64.rpm Fixed: - Digital Discovery jitter 3.13.6 digilent.waveforms_beta_v3.13.6_64bit.exe digilent.waveforms_beta_v3.13.6.dmg digilent.waveforms_beta_3.13.6_amd64.deb digilent.waveforms_beta_3.13.6.x86_64.rpm ARM64: digilent.waveforms_beta_3.13.6_arm64.deb digilent.adept.runtime_2.20.0-arm64.deb digilent.adept.utilities_2.3.0-arm64.deb Fixing known bugs 3.13.1 digilent.waveforms_beta_v3.13.1_64bit.exe digilent.waveforms_beta_v3.13.1.dmg Added: - Play mode for Digital Discovery in Logic Analyzer - Protocol/UART Save Raw data Fixed: - Pattern Generator preview 3.11.34 digilent.waveforms_beta_v3.11.34_64bit.exe digilent.waveforms_beta_v3.11.34.dmg digilent.waveforms_beta_3.11.34_amd64.deb digilent.waveforms_beta_3.11.34.x86_64.rpm Fixing known bugs. 3.11.33 digilent.waveforms_beta_v3.11.33_64bit.exe digilent.waveforms_beta_v3.11.33.dmg digilent.waveforms_beta_3.11.33_amd64.deb digilent.waveforms_beta_3.11.33.x86_64.rpm Added: - Protocol: - SPI/I2C frequency filter option - SpiFlash (P5Q, M25P16) interpreter option for Spy - Network: - Radian unit for phase plot Fixing known bugs. 3.11.32 digilent.waveforms_beta_v3.11.32_64bit.exe digilent.waveforms_beta_3.11.32_amd64.deb digilent.waveforms_beta_3.11.32.x86_64.rpm Changed: - Protocol: CAN RX re-synchronization for rate tolerance, +/-10% Fixing known bugs. 3.11.31 digilent.waveforms_beta_v3.11.31_64bit.exe digilent.waveforms_beta_v3.11.31.dmg digilent.waveforms_beta_3.11.31_amd64.deb digilent.waveforms_beta_3.11.31.x86_64.rpm Added: - Script: access to windows, like Scope.window.size = [600, 400] Changed: - Logic: - CAN interpreter re-synchronization to increase rate tolerance - CAN trigger ignore substitute remote request bit - Protocol: using Digital Discovery system frequency adjustment Fixes: - Patterns: preview 3.11.30 digilent.waveforms_beta_v3.11.30_64bit.exe digilent.waveforms_beta_v3.11.30.dmg digilent.waveforms_beta_3.11.30_amd64.deb digilent.waveforms_beta_3.11.30.x86_64.rpm Fixing known bugs 3.11.29 digilent.waveforms_beta_v3.11.29_64bit.exe digilent.waveforms_beta_v3.11.29_32bit.exe digilent.waveforms_beta_v3.11.29.dmg digilent.waveforms_beta_3.11.29_amd64.deb digilent.waveforms_beta_3.11.29.x86_64.rpm Fixing known bugs 3.11.28 digilent.waveforms_beta_v3.11.28_64bit.exe digilent.waveforms_beta_3.11.28_amd64.deb digilent.waveforms_beta_3.11.28.x86_64.rpm Added: - Script: - find and replace - clear output button and function - Ctrl+Tab - Save All, Open multiple files 3.11.27 digilent.waveforms_beta_v3.11.27_64bit.exe digilent.waveforms_beta_v3.11.27.dmg digilent.waveforms_beta_3.11.27_amd64.deb digilent.waveforms_beta_3.11.27.x86_64.rpm Fixes and Help update 3.11.26 digilent.waveforms_beta_v3.11.26_64bit.exe digilent.waveforms_beta_v3.11.26.dmg digilent.waveforms_beta_3.11.26_amd64.deb digilent.waveforms_beta_3.11.26.x86_64.rpm Added: - Script: - multiple files for individual scripts or optional include Fixed: - Logic Analyzer: - keep order in Bus signals 3.11.25 digilent.waveforms_beta_v3.11.25_64bit.exe digilent.waveforms_beta_3.11.25_amd64.deb digilent.waveforms_beta_3.11.25.x86_64.rpm Fixed: - Protocol I2C Read with Script 3.11.24 digilent.waveforms_beta_v3.11.24_64bit.exe digilent.waveforms_beta_v3.11.24.dmg digilent.waveforms_beta_3.11.24_amd64.deb digilent.waveforms_beta_3.11.24.x86_64.rpm Added: - Wavegen: - period setting next to frequency Changed: - Protocol: - AVR programmer speed, functions, script access Fixed: - Network Analyzer: - phase averaging 3.11.22 digilent.waveforms_beta_v3.11.22_64bit.exe digilent.waveforms_beta_v3.11.22.dmg (not certified) digilent.waveforms_beta_3.11.22_amd64.deb digilent.waveforms_beta_3.11.22.x86_64.rpm Added: - Logic Analyzer: - SPI interpreter with MOSI/MOSI - HDMI CEC interpreter, trigger on: start, source, destination - Portocol: - AVR programmed: Flash, EEPROM, Fuse, Lock, Calibration - Scope/Logic remembers as default option: Show Attenuation, Acquire Noise, Multiple Scale - Pattern Generator negative delay option Changed: - Pattern Generator: - clock duty round up 3.11.21 digilent.waveforms_beta_v3.11.21_64bit.exe Fixed: - Patterns preview 3.11.20 digilent.waveforms_beta_v3.11.20_64bit.exe Added: - shared workspace list when running multiple applications Fixed: - Digital Discovery trigger position - Patterns preview for pulse - other minor fixes 3.11.19 digilent.waveforms_beta_v3.11.19_64bit.exe Added: - Patterns Delay option for signal/bus Fixed: - Digital Discovery system frequency adjustment 3.11.18 digilent.waveforms_beta_v3.11.18_64bit.exe Fixed: - Supplies for EExplorer and Analog Discovery 1 - Logic Analyzer Inputs for Digital Discovery 3.11.17 digilent.waveforms_beta_v3.11.17_64bit.exe Added: - Spectrum Units: V/vHz, dBm, dBm/vHz, dBm/vMHz - Digital Discovery: - system frequency (Pattern Generator and Logic Analyzer) fine adjustment from Supplies window 3.11.16 digilent.waveforms_beta_v3.11.16_64bit.exe Added: - Spectrum: - Units: dBm, dBmHz, dBmMHz Fixed: - Wavegen: Sync option 3.11.15 digilent.waveforms_beta_v3.11.15_64bit.exe Added: - SDK: - VB/C# ushort and uinteger modes for FDwfDigitalInStatusData/2/Noise/2 - replacing BOOL and BYTE types - manual update - Logic Analyzer: - 100 MHz limit option for Digital Discovery Fixed: - Spectrum: Persistence view axis labels for log scales - SDK: VB/C# wrappers FDwfAnalogInStatusData16 3.11.14 digilent.waveforms_beta_v3.11.14_64bit.exe digilent.waveforms_beta_3.11.14_amd64.deb digilent.waveforms_beta_3.11.14.x86_64.rpm Added: - Script access to Logic Analyzer measurements - System Monitor in Supplies window for AD1, AD2, DD Fixed: - SDK DwfParamOnClose continue running after re-open 3.11.13 digilent.waveforms_beta_v3.11.13_64bit.exe Added: - Network/Impedance Analyzer usage with constant frequency, start=stop - quick measure, cursors, horizontal axis as percentage 3.11.12 digilent.waveforms_beta_v3.11.12_64bit.exe digilent.waveforms_beta_3.11.12_amd64.deb digilent.waveforms_beta_3.11.12.x86_64.rpm Added: - Import data from file option for Spectrum, Network and Impedance Analyzer - trace toolbar width setting for Impedance Analyzer - AnalogOutIn_PlayRecord.py example playing mono and recording to stereo WAV file - FDwfAnalogImpedanceStatusInput phase normalization Fixed: - Analog Discovery 2 USB power monitor false 1A readings - wrong default reference for dBV in Spectrum Analyzer 3.11.11 digilent.waveforms_beta_v3.11.11_64bit.exe Added: - Logic Analyzer Bus interpreter: - either Clock edge option - sampling delay relative to edge - Events view lists sample for each edge when Clock signal is selected 3.11.10 digilent.waveforms_beta_v3.11.10_64bit.exe Added: - Scope scale for XYZ and Spectrogram 3D views - Export EPS image format - support for multiple transfers in Protocol/I2C/Sensor loop function 3.11.9 digilent.waveforms_beta_v3.11.9_64bit.exe Added: - Scope Spectrogram 3D surface view, for 64bit Windows 3.11.8 digilent.waveforms_beta_v3.11.8_64bit.exe digilent.waveforms_beta_v3.11.8.dmg digilent.waveforms_beta_3.11.8_amd64.deb digilent.waveforms_beta_3.11.8.x86_64.rpm Added: - horizontal cursors for Scope/FFT, Spectrum and Impedance Analyzer - cursor delta as decade for logarithmic scales - Scope: - simple Math channel operations: RMS, ATan - LockIn amplifier as Math channel - XYZ 3D graph, for 64bit Windows Fixed: - Scope/Audio/Tempo option 3.11.7 digilent.waveforms_beta_v3.11.7_64bit.exe digilent.waveforms_beta_v3.11.7.dmg digilent.waveforms_beta_3.11.7_amd64.deb digilent.waveforms_beta_3.11.7.x86_64.rpm minor fixes and improvements 3.11.6 digilent.waveforms_beta_v3.11.6_64bit.exe digilent.waveforms_beta_v3.11.6.dmg digilent.waveforms_beta_3.11.6_amd64.deb digilent.waveforms_beta_3.11.6.x86_64.rpm Added: - Protocol - UART Spy - Max Lines option: log limit to prevent application slowdown - Line Wrap option - tooltips for UI controls listing Script access path - application and script Font options - dark theme support for Script 3.11.5 digilent.waveforms_beta_v3.11.5_64bit.exe Added: - Script open/save text file - application argument: -script myscript.txt/js Fixed: - warnings at low record rates 3.11.4 digilent.waveforms_beta_v3.11.4_64bit.exe Added: - Scope: - set/reset zero offset in each channel option - precision option for measurements Fixed: - Script: access to traces and channels from Instrument.Export - unit conversions V to Ṽ, A to à - I2S 32 bit data 3.11.3 digilent.waveforms_beta_v3.11.3_64bit.exe digilent.waveforms_beta_3.11.3_amd64.deb digilent.waveforms_beta_3.11.3.x86_64.rpm Fixes 3.11.2 digilent.waveforms_beta_v3.11.2_64bit.exe digilent.waveforms_beta_3.11.2_amd64.deb digilent.waveforms_beta_3.11.2.x86_64.rpm Added: - Spectrum, Network and Impedance Analyzer store time data when this view is open Fixed: - runscript argument - loading of docked views geometry 3.11.1 digilent.waveforms_beta_v3.11.1_64bit.exe digilent.waveforms_beta_3.11.1_amd64.deb digilent.waveforms_beta_3.11.1.x86_64.rpm Added: - Scope: out of range warning in measurements - Protocol/UART: - support up to 32bit/word - TX/RX format: text, binary, decimal, hex - Wheel Direction option - Logic Analyzer: option to swap previous/next events - Spectrum Analyzer: allowing higher number of BINs for CZT 3.10.7 digilent.waveforms_beta_v3.10.7_64bit.exe Added: - Spectrum: logarithmic magnitude scale for voltage units - Protocol: datetime stamp for SPI/I2C Spy Fixes 3.10.6 digilent.waveforms_beta_v3.10.6_64bit.exe Added: - Scope - access to digital channels from custom math channels - digital measurements view Fixes 3.10.5 digilent.waveforms_beta_v3.10.5_64bit.exe digilent.waveforms_beta_3.10.5_amd64.deb digilent.waveforms_beta_3.10.5.x86_64.rpm Added: - Power Supplies for AD2: tracking, slider, min/max - Logic Analyzer: Measurements - Impedance Analyze: DC mode compensation - SDK VB wrapper, C# wrapper updated Fixed: - EExplorer Wavegen AM/FM index precision for sine 3.10.4 digilent.waveforms_beta_v3.10.4_64bit.exe Fixed: - decimal resolution in Export, Data and Event views 3.10.3 digilent.waveforms_beta_v3.10.3_64bit.exe digilent.waveforms_beta_v3.10.3.dmg digilent.waveforms_beta_3.10.3_amd64.deb digilent.waveforms_beta_3.10.3.x86_64.rpm Added: - UART format option (binary, decimal...) - SDK I2C without clock stretching - SDK examples: Digital_I2c_PmodAcl.py, Digital_I2c_PmodGyro.py - Spectrum Analyzer THDN measurement, THDp and THDNp in percentage units - Impedance Analyzer: - constant current, voltage, custom script for amplitude and resistance control - Option to disable mouse drag and wheel operations on plots - Impedance/Network Analyzer: averaging time - Wavegen: extended frequency option Changed: - special values (none, off) moved to end of the preset list 3.10.2 digilent.waveforms_beta_v3.10.2_64bit.exe digilent.waveforms_beta_v3.10.2_32bit.exe digilent.waveforms_beta_v3.10.2.dmg digilent.waveforms_beta_v3.10.2_mavericks.dmg digilent.waveforms_beta_3.10.2_amd64.deb digilent.waveforms_beta_3.10.2_i386.deb digilent.waveforms_beta_3.10.2.x86_64.rpm digilent.waveforms_beta_3.10.2.i686.rpm Added: - Impedance Analyzer - voltage, current and custom plots - edit Meter list - Resistance mode for Meter, Frequency DC option - step mode in Time view - Network Analyzer - step mode in Time and FFT views - amplitude table and custom function Fixed: - Help minor fix - Protocol SPI and I2C Sensor rate improvement - StaticIO button lock 3.8.22 digilent.waveforms_beta_v3.8.22_64bit.exe digilent.waveforms_beta_v3.8.22_32bit.exe Added: - Impedance differential setup, W1-C1P-DUT-C1N-C2-R-GND 3.8.21 digilent.waveforms_beta_v3.8.21_64bit.exe digilent.waveforms_beta_v3.8.21_32bit.exe digilent.waveforms_beta_v3.8.21.dmg digilent.waveforms_beta_3.8.21_amd64.deb digilent.waveforms_beta_3.8.21_i386.deb digilent.waveforms_beta_3.8.21.x86_64.rpm digilent.waveforms_beta_3.8.21.i686.rpm Added: - data property for impedance/network channels. - Impedance.Resistor.reference property - instruments accessible without index in Script tool like Scope. Fixes... 3.8.20 digilent.waveforms_beta_v3.8.20_64bit.exe Added: - Logger function access to other channels value, average, min, max - Script access to Logger channel set data property, getting average, minimum, maximum Fixed: - Logger Show/Maximum - Script Protocol.I2C.Clear() function 3.8.18 digilent.waveforms_beta_v3.8.18_64bit.exe digilent.waveforms_beta_v3.8.18_32bit.exe digilent.waveforms_beta_v3.8.18.dmg Added: - Network Analyzer - logarithmic scale and percentage unit - spectrum measurements: Carrier, THD+N, THD, HD# - FFT view - Averaging option 3.8.17 digilent.waveforms_beta_v3.8.17_64bit.exe digilent.waveforms_beta_v3.8.17_32bit.exe digilent.waveforms_beta_v3.8.17.dmg digilent.waveforms_beta_3.8.17_amd64.deb digilent.waveforms_beta_3.8.17_i386.deb digilent.waveforms_beta_3.8.17.x86_64.rpm digilent.waveforms_beta_3.8.17.i686.rpm Added: - Scope - persistence support for smooth curve and min/max sampling - custom math - current value in custom math function, can be used for averaging - initialization code for integration purposes - examples - unit presets for: ohm, degree, VAC, AAC - Spectrum - Import/Export samples for Traces - trace information option - Range option to adjust all the scope input ranges - Network and Spectrum - Script support for set magnitude property - Step size and steps per decade settings - Network Analyzer - custom plots: THD, HD2, HD3 - Protocol - I2C/Spy glitch filter based on frequency setting - Device options - On Close: Run (keep running), Stop, Shutdown - USB Power: Always ON or Stop with AUX for AD2 - USB Limit: USB current limitation AD1,2 - Audio Output: AD1, 2 - WaveForms SDK FDwfParamSet/Get, FDwfDeviceParamSet/Get - DwfParamOnClose, DwfParamUsbPower, DwfParamLedBrightness, DwfParamAudioOut, DwfParamUsbLimit - Notes toolbar show/hide option - on/off icon for toggle buttons: supply enable, network analyzer reference... - show entire capture button Changed: - renewed mouse wheel, drag and key (left,right,up,down) operation on plots and axis Fixed: - EExplorer output glitch during first device connection - NI VI crash when initializing without device connected - Scope XY plot 3.8.11 digilent.waveforms_v3.8.11_64bit.exe digilent.waveforms_v3.8.11_32bit.exe digilent.waveforms_v3.8.11.dmg digilent.waveforms_3.8.11_amd64.deb digilent.waveforms_3.8.11_i386.deb digilent.waveforms_3.8.11.x86_64.rpm digilent.waveforms_3.8.11.i686.rpm Added: - Digital Discovery: - LED brightness option - Logic Analyzer - ASCII format for: Bus, SPI, I2C, I2S - Format option for I2C - Logic Analyzer and Patterns - Line Color option - Protocol - Format option for SPI and I2C: Hexadecimal, Decimal, Binary, ASCII - Plot Width option in application settings Changed: - drawing quality improvement for thicker lines - color dialog buttons renamed to Close and Reset 3.8.9 digilent.waveforms_v3.8.9_64bit.exe digilent.waveforms_v3.8.9_32bit.exe digilent.waveforms_v3.8.9.dmg digilent.waveforms_3.8.9_amd64.deb digilent.waveforms_3.8.9_i386.deb digilent.waveforms_3.8.9.x86_64.rpm digilent.waveforms_3.8.9.i686.rpm Added: - WF/Settings/Options: Locale with System or English US regional option, export and import options - SDK: FDwfParamSet/Get function - Scope: measurement resolution Fixed: - minor issues 3.8.8 digilent.waveforms_v3.8.8_64bit.exe digilent.waveforms_v3.8.8_32bit.exe digilent.waveforms_v3.8.8.dmg Added: - WF SDK: - examples updated to be Python v3 compatible - FDwfAnalogImpedance functions for impedance/network analysis - Protocol: CAN receiver filter by ID - Impedance: Export information about amplitude and offset Fixed: - WF SDK: FDwfDigitalSpi functions read MISO/RX 3.8.7 digilent.waveforms_v3.8.7_64bit.exe Fixed: - Scope: save/load of coefficients for custom Math channel filter 3.8.6 digilent.waveforms_v3.8.6_64bit.exe digilent.waveforms_3.8.6_amd64.deb Added: - Export: Wavegen and Supplies information added to Scope, Spectrum, Impedance, Network export comments Fixed: - Script Tool.exec timeout - CAN high polarity option in Protocol tool and WF SDK 3.8.5 digilent.waveforms_v3.8.5_64bit.exe Added - Script functions: getSaveFile, getOpenFile, getDirectory - Scope: multiple scales, zero offset - Notes view - Export options: notes, header as comment - Help tab: floating/undock option, find with highlight Fixed: - Impedance Analyzer frequency scale in export 3.7.22 digilent.waveforms_v3.7.22_64bit.exe digilent.waveforms_v3.7.22_32bit.exe digilent.waveforms_v3.7.22.dmg digilent.waveforms_3.7.22_amd64.deb digilent.waveforms_3.7.22_i386.deb digilent.waveforms_3.7.22.x86_64.rpm digilent.waveforms_3.7.22.i686.rpm Added - Scope/Logic View/Logging picture format - Script: - Export function for instruments - access to Protocol/UART/RX using Receiver, Receive and ReceiveArray functions, SendArray Fixed - Scope edge trigger position for all devices, when only one or two samples are above the threshold - other minor fixes 3.7.21 digilent.waveforms_v3.7.21_64bit.exe digilent.waveforms_v3.7.21_32bit.exe digilent.waveforms_3.7.21_amd64.deb digilent.waveforms_3.7.21_i386.deb digilent.waveforms_3.7.21.x86_64.rpm digilent.waveforms_3.7.21.i686.rpm Added - Wavegen dynamic configuration, adjustments without restarting the generator - SDK support for CAN bus TX, RX - more detail in Spectrum, Network and Impedance Analyzer export comments - import data orientation option Fixed - Network Analyzer Meter export and copy - Data Logger quick measurements - other fixes and optimizations 3.7.19 digilent.waveforms_v3.7.19-2_64bit.exe digilent.waveforms_v3.7.19-2_32bit.exe digilent.waveforms_v3.7.19.dmg digilent.waveforms_3.7.19-2_amd64.deb digilent.waveforms_3.7.19-2_i386.deb digilent.waveforms_3.7.19-2.x86_64.rpm digilent.waveforms_3.7.19-2.i686.rpm Added: - Logic I2S Show channel option - SDK functions for UART, SPI, I2C master and UART receiver Changed: - OS-X rollback to FTDI driver 1.2.2 Fixed: - Impedance Analyzer: save/load of views positions - other fixes and optimizations 3.7.15 digilent.waveforms_v3.7.15_64bit.exe digilent.waveforms_v3.7.15_32bit.exe Added: - Logic Analyzer: position (Nth word) option for SPI trigger on value - Impedance: Nyquist plot; settle time, minimum periods options - Wavegen, Network/Impedance Analyzer: external Amplification option - Tabbed/Docking window switching from main window Changed: - lower frequency limit for Scope, AWG, Network, Impedance Fixed: - 10ns delay in Logic Analyzer Sync and Protocol interface - Sound Card device CPU usage 3.7.14 digilent.waveforms_v3.7.14_64bit.exe digilent.waveforms_v3.7.14_32bit.exe Added: - Protocol I2C ACK/NAK last read byte option Changed: - Windows XP, Vista compatible FTDI driver in 32bit installer 3.7.13 digilent.waveforms_v3.7.13_64bit.exe digilent.waveforms_v3.7.13_32bit.exe digilent.waveforms_v3.7.13.dmg digilent.waveforms_3.7.13_amd64.deb digilent.waveforms_3.7.13_i386.deb digilent.waveforms_3.7.13.x86_64.rpm digilent.waveforms_3.7.13.i686.rpm Added: - Sound Card device of the computer can be used as Scope and Wavegen - Scope sampling clock for Electronics Explorer - Logic Analyzer data compression for recording, for Electronics Explorer - Scope and Wavegen support for 4th device configuration of Analog Discovery 1 & 2 - Scope Logging Repeat option - Scope Audio view: Stereo, Tempo options - MacOS option for application menu 3.7.12-2 digilent.waveforms_v3.7.12-2_64bit.exe Fixed: - Analog Discovery 2 configuration file descriptions 3.7.12 digilent.waveforms_v3.7.12_64bit.exe digilent.waveforms_v3.7.12_32bit.exe Added: - Scope sampling clock under time options, for Analog Discovery 1 & 2. The trigger IOs can be used as sample clock with delay and edge options. - Logic Analyzer data compression for recording, for Analog Discovery 1 & 2 Changed: - Windows installer: - embedded prerequisites: Windows Installer, Visual C++ Redistributable 9 32/64bit, 12 64bit - split installer for 32bit and 64bit WF applications, but the included WF runtime for custom applications support both architectures Fixed: - Logic Analyzer UART frame error threshold 3.7.10 digilent.waveforms_v3.7.10.exe Added: - Spectrum Analyzer Markers Fixed: - SDK Electronics Explorer enumeration - Scope Math channel unit presets 3.7.9 digilent.waveforms_v3.7.9.exe Fixing: - Logic Analyzer Event view double click for signals 3.7.8 digilent.waveforms_v3.7.8.exe Changed: - Impedance Analyzer: - view names - solid line for magnitude Fixed: - Impedance Analyzer admittance |Y| value 3.7.7 digilent.waveforms_v3.7.7.exe Added: - Scope and Logic trigger detector for trigger source Fixed: - warning message when connecting to EExplorer - Patterns trigger on Digital Discovery.
  2. 3 points
    For anyone else out there who's struggling with DDR3 SDRAM on the Arty A7, here's a project for Vivado 2019.2 that builds out-of-box and successfully reads / writes (via the MIG user interface) to / from memory. Hopefully this'll save someone the pain I went through figuring out how to interface with the DDR-SDRAM via Verilog. Arty-SDRAM.zip
  3. 3 points
    Hi everyone, LINX can be installed on the Raspberry Pi 4. The LINX 3.0 Target Manual Install Process (https://www.labviewmakerhub.com/doku.php?id=learn:libraries:linx:misc:target-manual-install) did not work due to changes in the latest version of Raspbian. Here is the procedure that I used to install LINX. The procedure also works on the Raspberry Pi 2B, Pi 3A+, Pi 3B and Pi 3B+ running Raspbian Buster. 1. Setup the Raspberry Pi using the latest Raspbian Buster Image. 2. Change the default password for the Pi account on the Raspberry Pi. 3. Setup a WiFi or Ethernet connection from the Raspberry Pi to your router. 4. Enable SSH on the Raspberry Pi. 5. SSH into the Raspberry Pi or open a terminal window on the Raspberry Pi desktop. 6. Check that the Raspberry Pi can access the Internet by entering the command ping -c 4 raspberrypi.org 7. Enter the commands shown in bold below. Note: The text may wrap due to the web browser window size. I recommend copying the text into a text editor to see the original formatting. The commands are in the attached file linx_install_commands.txt # Enable i2c and spi sudo raspi-config nonint do_i2c 0 sudo raspi-config nonint do_spi 0 # Update Raspbian sudo apt-get update sudo apt-get dist-upgrade -y # Install LINX sudo sh -c 'echo "deb [trusted=yes] http://feeds.labviewmakerhub.com/debian/ binary/" >> /etc/apt/sources.list' sudo apt-get update sudo apt-get install -y lvrt-schroot # Move the nisysserver.service and labview.service files to the systemctl folder sudo mv /etc/systemd/system/multi-user.target.wants/nisysserver.service /lib/systemd/system sudo mv /etc/systemd/system/multi-user.target.wants/labview.service /lib/systemd/system # link liblinxdevice.so to the Raspberry PI device driver file liblinxdevice_rpi2.so sudo schroot -c labview -d /usr/lib -- ln -s liblinxdevice_rpi2.so liblinxdevice.so # Enable the nisysserver.service and labview.service to start on boot sudo systemctl enable nisysserver.service sudo systemctl enable labview.service # Start the nisysserver.service and labview.service sudo systemctl start nisysserver.service sudo systemctl start labview.service You should now be able to connect to the Raspberry Pi from the LabVIEW Project Explorer. Cheers, Andy. linx_install_commands.txt
  4. 3 points
    Ana-Maria Balas

    MTDS PMOD Connection issue

    Hello @WillTx, 1. There is an IP for Pmod MTDS with the drivers you need to make your Pmod MTDS working. It also contains 10 demos from which you can learn a lot. You can find it here : https://github.com/Digilent/vivado-library/tree/master/ip/Pmods/PmodMTDS_v1_0. You need to download the entire vivado-library (from here) then follow the tutorial for using Pmod IP cores in Vivado. 2. Your block design after adding the Pmod MTDS IP: 3. You can use the board flow to automatically connect to JB Pmod connector without a XDC constrain file (as it shows in the tutorial at step 3). You need to install the board files first. If you want to use the Cora-Z7-07S-Master.xdc constraint file, below are the lines corresponding to JB Pmod connector : 4. Please follow the REAME.txt found in drivers/PmodMTDS_v1_0/examples/ Cheers, Ana-Maria
  5. 2 points
    Hi, as a simple (oversimplified?) answer, designing for higher clock speed requires higher effort (possibly "much" higher effort), and the resulting optimizations make the code harder to work with. Using the clocking wizard to generate a 500 MHz PLL is easy (try it). But writing logic at those frequencies is a different story (e.g. try to implement a conventional counter that divides down to 1 Hz. Why do all those XYX_CARRY signals show up in the timing report already at synthesis?). You also need to distinguish between what is feasible in plain logic fabric, and what can be done with dedicated "hard-macro" IP blocks such as SERDES.
  6. 2 points

    Access to the GPIO with the API

    I'm not competent to lecture on software best practices but this topic merits discussion. Perhaps a few comments will kick one off and lure people better qualified than me to participate. There are ways of accessing hardware from software applications in just about anyway you choose. That doesn't mean that hey are all ideal or even acceptable. As a rule, using well worn libraries are preferred. In general they are not the fastest or the easiest or most simple way to interact with hardware. For safety, consistency, and orderliness they are better than reference by address. One concept is hard to argue against. If there is a possibility that another application or process has access to the same hardware then direct manipulation of hardware is a very dangerous thing to do. For some embedded projects you are guaranteed that only your code is running. This doesn't mean that direct access is a wise choice, especially if you have levels of interrupts running. For embedded systems that have an OS or RTOS where hardware is specifically isolated from end user applications by design, direct access of hardware is rather foolish because you have no control over what code the processor(s) is running a any given instant. Worse yet direct manipulation of hardware creates a situation in which neither you nor your OS can know what the state of your hardware is at any given moment. You can always alter your OS by adding kernel mode drivers if the standard ones don't fit your needs. The bottom line is understand the consequences for your design choices and code safely. You are guaranteed to pay for bad choices. For software development a general rule of thumb is that if what you are doing is direct and simple then it's likely a bad idea.
  7. 2 points

    Let me tell you why I HATE Digilent

    I do have to say that I was concerned when I initially clicked on this thread...but I think I'll let it stay. 😉 Please let us know if you have any questions about using the products! Thanks, JColvin P.S. I definitely sent this forum thread to our Scopes and Instruments product manager with minimal context to see what her reaction is.
  8. 2 points
    It's been too long ago but I do remember taking the scenic side journey into investigating performance of floating point on Intel processors. Mostly what I remember is that it was interesting, informing, had unexpected surprises and was a valuable exercise. Just recommending the excursion to anyone interested in 'bit exactness'.
  9. 2 points

    RISC-V RV32I CPU/controller

    I've just posted my holiday project to Github - Rudi-RV32I - https://github.com/hamsternz/Rudi-RV32I It is a 32-bit CPU, memory and peripherals for a simple RISC-V microcontroller-sized system for use in an FPGA. A very compact implementation and can use under 750 LUTs and as little as two block RAMs - < 10% of an Artix-7 15T. All instructions can run in a single cycle, at around 50MHz to 75MHz. Actual performance currently depends on the complexity of system bus. It has full support for the RISC-V RV32I instructions, and has supporting files that allow you to use the RISC-V GNU toolchain (i.e. standard GCC C compiler) to compile programs and run them on your FPGA board. Here is an example of the sort of code I'm running on it - a simple echo test:, that counts characters on the GPIO port that I have connected to the LEDs. // These match the address of the peripherals on the system bus. volatile char *serial_tx = (char *)0xE0000000; volatile char *serial_tx_full = (char *)0xE0000004; volatile char *serial_rx = (char *)0xE0000008; volatile char *serial_rx_empty = (char *)0xE000000C; volatile int *gpio_value = (int *)0xE0000010; volatile int *gpio_direction = (int *)0xE0000014; int getchar(void) { // Wait until status is zero while(*serial_rx_empty) { } // Output character return *serial_rx; } int putchar(int c) { // Wait until status is zero while(*serial_tx_full) { } // Output character *serial_tx = c; return c; } int puts(char *s) { int n = 0; while(*s) { putchar(*s); s++; n++; } return n; } int test_program(void) { puts("System restart\r\n"); /* Run a serial port echo */ *gpio_direction = 0xFFFF; while(1) { putchar(getchar()); *gpio_value = *gpio_value + 1; } return 0; } As it doesn't have interrupts it isn't really a general purpose CPU, but somebody might find it useful for command and control of a larger FPGA project (converting button presses or serial data into control signals). It is released under the MIT license, so you can do pretty much whatever you want with it. Oh, all resources are inferred, so it is easily ported to different vendor FPGAs (unlike vendor IP controllers)
  10. 2 points
    @Vishnuk Here's a tutorial that discusses how to build both UARTs and FIFOs. Dan
  11. 2 points
    I've spent some time since my first post trying to figure out what's in store for users with Vitis. With Vivado 2019.2 + Vitis you still need a Linux host to develop Petalinux applications. It was a chore, but I did manage to install Petalinux 2019.1 onto a Ubuntu 18.04 VM running in HyperV on my Win10 Pro box. This PC has 32 GB ram so I can allocate 8 GB to the VM. I haven't as yet actually created a project with the Petalinux tool this way yet. My plan is to wait and see how well Xilinx develops the tools with the next release before moving to 2019.2 and the new paradigm. Note that Vivado 2019.2 also breaks even Xilinx IP created in previous versions. For now I'm sticking with VIvado 2019.1 and Petalinux 2019.1. In 2019.2 tools Vivado and Vitis are not integrated. You still have to export hardware but you can't launch Vitis from Vivado. I'm assuming that at some point in the future users will start off in Vitis and launch Vivado from within that IDE. ** It's been my experience that overall performance with Linux VMs in WIn10 is poor unless you start with one of the 'optimized' quick start images from Msoft. Unfortunately, there is no way to change the default disk size of 12 GB, which is way too small do doing anything useful... like even install Petalinux. You can resize the VM disk size after creating the VM but you still need to install a disk management tool like Gparted onto your VM to re-size the Unbuntu partition to make use of the expanded disk size. Needless to say all of this should be done before completely setting up and updating the VM. The whole process of installing Petalinux was rather messy and time consuming. And HyperV is... well Msoft, so get used to frustration, pain and misery.
  12. 2 points
    Hello Frankly and welcome to our forum. Here are 2 patches that can be applied on top of a Petalinux 2019.1 project to allow reading the OTP MAC and configure it to do so. You can try applying them on 2018.2. Message us back if you have any issues. Cosmin 0001-Z7-20-allow-reading-MAC-address-from-OTP.patch 0002-Z7-20-use-OTP-MAC.patch
  13. 2 points
    Hello @Bryan_S, Here is a demo project for Cmod S6 from https://reference.digilentinc.com/reference/programmable-logic/cmod-s6/start. I looked into the source files and there is clk_gen_50MHz.vhd. You can see in the top.vhd file how the clk_gen_50MHz is instantiated and used. I don't know what is the clk16x in your code, but here are some source files for serial port serialport_v3.zip The sources are for Nexys4 DDR which has a 100 MHz system clock. But in your case, if you use the clk_gen_50MHz, you'll have a 50 MHz clock instead of 100 MHz, 9600 baud rate, as shown in the UART_RX_CTRL.vhd file. The same for UART_TX_CTRL.vhd. I don't know if you'll use the sources from above, but I hope it helps. Best regards, Ana-Maria Balas
  14. 2 points
    Hello @bitslip, Things are a little bit more complicated. Indeed, for changing the resolution you have to rewrite some registers. But you also need to make sure that the Video Trimming controller ip generates the required constants for you resolution. I wouldn't recommend to write all the needed registers from the control interface (it would be agonising) Instead I would go with the existent logic for changing the resolution, which is adding a new structure with all the register values. As an example, you can check the OV5640.H file. I much simple and quicker solution would be to use our video scaller ip. This ip was written in HLS and it was used in the fmc pcam adapter demo for re-scalling the video at a 640x480 resolution. You can check the design in here: https://reference.digilentinc.com/learn/programmable-logic/tutorials/zedboard-fmc-pcam-adapter-demo/start Best Regards, Bogdan Vanca
  15. 2 points
    Hi @attila Thank you again for all the support you've provided me for the past weeks. I am now capable of receiving more than 409 characters using the Wrapper I created base from your example. It uses the Record acquisition mode and I set the buffer size to 3 million for now. I'll increase it when the need arises. I used 1 UART controller and branched out its Tx pin to 2 DIO pins of the AD2 (DIO #0 & 1). I transmitted 500 characters: (If Record mode is not the acquisition mode, the received result will be blank) For DIO # 0, it received: with a length of: For DIO #1, it received: with a length of: I could not have done it without your guidance, thank you again and more power to you and Digilent Best regards, Lesiastas
  16. 2 points
    I own three of FMC equipped boards that you mention and frequently use at least one on a regular basis. Just for arguments sake; lets say that I want to design my own FMC mezzanine card using all of those differential pairs. Where do I find the trace routing report letting me know what the trace lengths are for the Genesys2, Nexys Video and Zedboard?
  17. 2 points
    Hi all, Quick update here. I've got binaries built for Mac and Linux (Ubuntu) and have updated the documentation to link to them. You may also download the Windows, Mac or Linux binaries by following the links I just gave you. If you encounter any issues whatsoever, submit in issue on the GitHub page and I'll set to fixing them straight away. Regards, AndrewHolzer
  18. 2 points
    Hey Paolo, I'm glad you found my videos helpful! I've been working on other projects, but if you have any other ideas for videos that you would find helpful let me know. Kaitlyn
  19. 2 points
    Yes, that cable is suitable from connection perspective. Still, there are functionality issues that you must be concerned. Most of the Pmods communicate using protocols like SPI, I2C, etc. This is specified on the Pmod datasheet. This means that the pins corresponding on the maching connector (on the system board) must implement that specific functionality. Normally using a FPGA board will be easier to configure Pmod pins to the needed functionality. Still, as you use a microcontroller board, this might be more difficult or even impossible. Please check if the pins associated to the Pmod rows correspond with the associated function on the Pmod. Another possibility is to re-configure the pins if your microcontroller allows pins reconfiguration. Please check (in the board schematic) which microcontroller pins are connected to the Pmod connector, and then check (in the microcontroller datasheet) the functions for these pins. Good luck.
  20. 2 points

    FAT32 with Zybo Z7

    @sgandhi, Welcome to data processing. The sad reality is that text files aren't good for this kind of thing. It's not an FPGA particular thing, but rather a basic reality. 1) Text files tend to take up too much space, and 2) they require processing to get the data into a format usable by an algorithm. One way to solve this problem, which I've done in the past with great success, is to rearrange the file so that's it's a binary file containing a large homogeneous area of elements all of the same type. In my case, I wanted a file that could be easily ingested (or produced) by MATLAB. I chose a binary format that had a header, followed by an NxM dimensional matrix of all single-precision floats. (You can choose whatever base type you want, but single-precision floats were useful for my application.) The header started with three fields: 1) First, there was a short marker to declare that this was the file type. I used 4-capital text letters for this marker. That was then followed by the 2) number of columns in the table, and then 3) the offset to the start of the table. This allowed me to place information about the data in further header fields, while still allowing the processor to skip directly from the beginning header to the data in question. Further, because the data was all of the same type, I could just about copy it directly into memory without doing any transformations, and to then operate on it there. It did help that the data was produced on a system with the same endianness as the system it was read from ... Dan
  21. 2 points

    Zybo Z7 Pcam 5C Demo - Warnings

    To add a little bit to what Jon said, these warnings appear to be ignorable. They all relate to design choices made when connecting custom IP in the block design. Typically, even when designing with Xilinx IP, many warnings are seen in the project. These messages are there to help get information on why something may be causing bigger problems later (errors, critical warnings, something not working in actual hardware). Note that even some critical warnings may be ignored. -Arthur
  22. 2 points
    There is no code to draw any shape as you observed since it was/is a work in progress. Thus it was excluded by default from `rootfs`. However it was mentioned by mistake in the first link you mentioned. https://reference.digilentinc.com/reference/software/petalinux/start The issue has been corrected.
  23. 2 points
    Hi, Sorry to barge in, but if anybody can point me to the Hibbert Transformer info I would be very grateful. However, here is an FPGA friendly way to calculate mag = sqrt(x*x+y*y), with about a 99% accuracy. You can easily see the pattern to get whatever accuracy you need. #include <math.h> #include <stdio.h> #define M_SCALE (16) /* Scaling for the magnitude calc */ void cordic_mag(int x,int y, int *mag) { int tx, ty; x *= M_SCALE; y *= M_SCALE; /* This step makes the CORDIC gain about 2 */ if(y < 0) { x = -(x+x/4-x/32-x/256); y = -(y+y/4-y/32-y/256); } else { x = (x+x/4-x/32-x/256); y = (y+y/4-y/32-y/256); } tx = x; ty = y; if(x > 0) { x += -ty/1; y += tx/1;} else { x += ty/1; y += -tx/1;} tx = x; ty = y; if(x > 0) { x += -ty/2; y += tx/2;} else { x += ty/2; y += -tx/2;} tx = x; ty = y; if(x > 0) { x += -ty/4; y += tx/4;} else { x += ty/4; y += -tx/4;} tx = x; ty = y; if(x > 0) { x += -ty/8; y += tx/8;} else { x += ty/8; y += -tx/8;} tx = x; ty = y; if(x > 0) { x += -ty/16; y += tx/16;} else { x += ty/16; y += -tx/16;} *mag = ty/M_SCALE/2; /* the 2 is to remove the CORDIC gain */ } int main(int argc, char *argv[]) { int i; int cases = 300; printf("Irput Calculated CORDIC Error\n"); for(i = 0; i < cases; i++) { float angle = 2*M_PI*i/cases; int x = sin(angle)*20000; int y = cos(angle)*20000; int mag, a_mag = (int)sqrt(x*x+y*y); cordic_mag(x,y, &mag); printf("%6i %6i = %6i vs %6i %4i\n", x, y, a_mag, mag, mag-a_mag); } } Oh, here is the output with a couple more iterations added. Irput Calculated CORDIC Error 0 20000 = 20000 vs 19999 -1 418 19995 = 19999 vs 19995 -4 837 19982 = 19999 vs 20001 2 1255 19960 = 19999 vs 19998 -1 1673 19929 = 19999 vs 19995 -4 2090 19890 = 19999 vs 20001 2 2506 19842 = 19999 vs 19998 -1 2921 19785 = 19999 vs 19996 -3 3335 19719 = 19999 vs 20001 2 3747 19645 = 19999 vs 19998 -1 4158 19562 = 19999 vs 19996 -3 4567 19471 = 19999 vs 20001 2 4973 19371 = 19999 vs 19997 -2 5378 19263 = 19999 vs 19996 -3 5780 19146 = 19999 vs 20001 2 6180 19021 = 19999 vs 19998 -1 6577 18887 = 19999 vs 19999 0 6971 18745 = 19999 vs 20001 2 7362 18595 = 19999 vs 19993 -6
  24. 2 points

    Enevlope Detection using FPGA board

    Well yes and no. The question I'd ask is, can you use a local oscillator somewhere in your signal path with a 90 degree offset replica. In many cases this is trivially easy ("trivially" because I can e.g. divide digitally from double frequency or somewhat less trivially, use, say, a polyphase filter. In any way, it's probably easier on the LO than on the information signal because it's a single discrete frequency at a time, where the Hilbert transform approach needs to deal with the information signal bandwidth). If so, downconvert with sine and cosine ("direct conversion") and the result will be just the same. After lowpass filtering, square, add, take square-root, there's your envelope . When throughput / cost matters (think "Envelope tracking" on cellphones) it is not uncommon to design RTL in square-of-envelope units to avoid the square root operation. Or if accuracy is not that critical, consider a nonlinear bit level approximation see "root of less evil, R. Lyons". Of course, Hilbert transform is a viable alternative, just a FIR filter (if complex-valued). In case you can't tell the answer right away, I recommend you do the experiment in the design tools what happens if you try to reach 0 Hz (hint, "Time-bandwidth product, Mr. Heisenberg". Eventually it boils down to fractional bandwidth and phase-shifting DC remains an unsolved problem...).
  25. 2 points
    Hi @Lesiastas In the SDK the digital-in functions provides raw data, this needs to be interpreted in the custom application or script. See the SDK/ samples/ py/ DigitalIn_Spi_Spy.py An example UART interpreter can be found in the WF application/ Logic Analyzer/ Custom
  26. 2 points
    Hey guys, I've made some experiments that could be interesting for your as well. I put tap water into my ceramic container, I heated it to different temperatures and measured the impedance every 5 degrees. You can see the values between 60 ° Celsius (140 ° Fahrenheit) and 5 ° Celsius (41 ° Fahrenheit). Red is 60 Celsius, blue is 5 Celsius and there are 10 steps between them.
  27. 2 points
    Thanks for the update @JColvin; obviously not what we'd like to hear in so far as lack of resources behind the product but the communications is appreciated. TBH, the dlog-utils code is... not great. The majority of the code is in type conversion and formatting (i.e. not germane to the actual processing of the data); I'm not surprised to hear it's problematic in updating it for OpenLogger as hard-coded assumptions on the data header abound (e.g. endianness; I presume the author is banking on that never changing, which may well be the case but it is in the format spec). As a reference implementation it hides the important data structure information in amongst language-specific type gymnastics. In contrast the Kaitai Struct approach removes all of that, and puts the data format front and centre, is trivially extensible (you update the struct definition and rebuild the library, done), and works "everywhere". If it were my decision I'd dump the current dlog-utils and start again based on Kaitai Struct, the result would be: a proper definition of the data format (rather than users having to reverse engineer the cpp code and troll the forums) a couple of dozen of lines of code for the reference Digilent implementation and most importantly would be useful/portable in any language/environment that Kaitai Struct supports (C++/STL, C#, Go, Java, JavaScript, Lua, Perl, PHP, Python, Ruby) As an example, what is implemented in nearly 180 LOC dlog-utils.cpp is under a dozen lines in the dlog-utils-portable Python example (`dlog = Dlog.from_file(args.inputfile)` followed by a `write_csv`), with far greater flexibility in terms of handling future variations on data formats, and better output formatting 🙂 Given that Digilent have very limited resources for this project it's important they're used wisely, switching to Kaitai Struct is easily the best bang for buck we can ask for. (BTW, it might sound like I'm a shill for Kaitai Struct - nope, I'm just a satisfied user and first discovered it when writing dlog-utils-portable... I once wrote code to process structured binary data in the same way as dlog-utils, but I've now seen the light 🙂
  28. 2 points
    Chris Burrows

    Embedded Project Oberon OS

    We have just released v7.0 of Astrobe for RISC5. The initial release supports both the Artix-7 and Spartan-7 FPGA devices as used on the Digilent Arty development boards. New hardware capabilities include Arduino shield-compatible SPI and I2C interfaces and support for up to 32 GPIO pins. See the announcement on the Astrobe forum for links to a full summary of What’s New and information on how to obtain a free copy:
  29. 2 points

    Analog Discovery 2 vs Raspberry Pi 3

    Szia and Attila I got a Raspberry Pi 4 last week on release day (got the 2GB version as they sold out of 4GB in half a day) . Just got it plugged into the Analog Discovery and it works! Not really tried it for long but it seems to work reliably, but only well on USB3. On USB3 port, first time it wasn't recognised, but tried again after swapping devices around a then it was detected. Maybe it clashed with my wireless mouse dongle When I tried USB2 port, it connected immediately but I found that every few minutes (max 5-10mins) it would throw a device error window and I would have to clear and reconnect. Maybe RPi foundation kept the FTDI chipset for USB2 and used a new one for USB3 (Pi datasheet only says there is one chipset and it's not FTDI). I will try and soak test tomorrow, but looking good on USB3. So far it has been running 23mins with no apparent glitches, and Chromium tabs open. Waveforms taking 13-20% of CPU in task manager.
  30. 1 point

    Microblaze issues for a beginner

    Hi, >> but I feel like lost in documents Welcome to FPGAs. This is pretty much the name of the game (but it also makes the struggle worthwhile - if it were easy, everybody would do it 🙂 ). As a general direction, a solid (basic) tutorial is good but don't expect to be led by the hand all the way. The constant version changes make this quite difficult (good news: it means there is technological progress ... well at least in theory but the guys from the marketing department said so and they'll surely know ...). More specific directions: Have a look at Microblaze MCS. It's fairly simple - set up the most basic system with some BRAM (=memory "internal" to the FPGA fabric) and one UART. Once you've got that printing "Hello World" - which is mostly a question of baud rates and not mixing Tx/Rx pins, you can add features one by one and the sky is the limit. Well, at least until the little girl next door pulls out her Raspberry Pi, running four cores at 10x the clock frequency - don't complain no one told you: by absolute standards, the performance of any softcore CPU is pathetic, compared to a regular ASIC CPU on the same technology node. So eventually you'll have to move into FPGA territory, or it makes little sense except as a learning exercise.
  31. 1 point
    Hi @Wayne Chen The data is Two's complement.
  32. 1 point
    For FTDI devices supporting 245 Synchronous FIFO mode there are three requirements to use this mode: Modification of the eeprom configuration data Switching to 245 mode in the software application that uses it. Using the D2XX driver instead of the default VCP driver. Also, you need to use the 60 MHz clock that is generated in the device after all of the requirements are met. I heartily recommend anyone interested in experimenting with the FTDI devices to study the excellent busbridge3 demo. For boards supporting the Adept DPTI mode this is a far easier way to achieve reasonably good data rates between the busbridge3 demo and 245 Synchronous FIFO mode.
  33. 1 point
    Getting decent dynamic range for converting numbers to a natural log using lookup tables is problematic. I've done pipelined log generators for 32-bit integers using a combination of lookup and Taylor Series having about 15+ bits of fractional precision. The Taylor series is nice in that it's trivial to get a log to any base like 2, e, or 10 from any other base. Fixed point binary math is pretty much a matter of bookkeeping. If you can constrain your log values things are easier. As to verifying the 'randomness' of your end results I'll leave that to you and whoever reviews your work. Generating truly random numbers digitally has been tried many times by many people. I suppose someone can figure it out.
  34. 1 point
    JColvin, Thanks for your quick reply. I have since removed ISE 14.7 and switched to Vivado, problem solved. Perhaps you should put a note on the resource page that the .ucf file for the Nexys 4 DDR is the same for the Nexys A7. Sincerely
  35. 1 point
    Yes, I followed the directions in the post you suggested and bypassed IC20.
  36. 1 point

    Storing Atlys PLB project to SPI/Flash

    Sweet, I'm glad to hear the design has been exported; I hope the bootloader side of things in SDK works as well.
  37. 1 point

    high speed ADC aquisition

    Hi @voltagesurge, My understanding is that it should be 500 kS/s for the SD card; I suspect this is an error on the WaveFormsLive side of things, though I have asked @AndrewHolzer for clarification on this. Thanks, JColvin
  38. 1 point

    Zedboard - how to run ramdisk FS in ram

    @m3atwad You can find this option by issuing: petaliux-config Then go to Image Packing Configuration -> Root filesystem type (???????) ---> INITRAMFS.
  39. 1 point

    Running AD2 on Raspberry pi 3 B

    Hi @jody The Analog Discovery is working with Raspberry PI 4 B and many other single board ARM computers. It is not working with Raspberry PI 1, 2, 3 B It looks like there is incompatibility between USB controller and this.
  40. 1 point

    PMODs - Spec 1.2.0

    Hi @andresb, I apologize for the delay. The best way to determine if they are complaint with specification 1.2.0 is by looking at their respect Resource Center (such as the Pmod AD1). On the right-hand side under Electrical, you will see the Specification version that the Pmod is currently compliant with. The Pmod Interface Specification 1.2.0 is available directly here: https://reference.digilentinc.com/_media/reference/pmod/pmod-interface-specification-1_2_0.pdf. Let me know if you have any questions about this. Thanks, JColvin
  41. 1 point
    Hi @svet-am, This solution works just for the Digilent boards. Please contact Xilinx for support in order to fix your KCU1500 board. Best regards, Bianca
  42. 1 point

    Pmod RS485 size

    Hi @Takashi "The Yaka mein", We have a 3D model of the Pmod RS485 available in it's Resource Center on the right hand side under Documentation. Let me know if you have any questions. Thanks, JColvin
  43. 1 point
    Hi @Lesiastas In case you are using the default device configuration, you have 1k (1024) custom digital-out (pattern generator) bit buffer per channel available. With this you can send 102 uart characters at once, 1024/(1+8+1). You could use the 4rd device configuration to have 16k bit available, 1638 uart chars. See the attached post below. You should take care to pass at most the buffer size for FDwfDigitalOutDataSet. In case you want to send more data split the string and transfer sequentially. You can also use the FDwfDigitalUartTx function which splits the string sending depending on the available device buffer.
  44. 1 point
    Hi @sgrobler, I've build a 64-bit executable for Windows, which you can download from here. Save that into a location you're likely to remember. Refer to the repository README for instructions on how to use the executable. Regards, AndrewHolzer
  45. 1 point
    Hi @Lesiastas The Logic Analyzer interface captures raw time domain samples and decodes the protocol in software, like it is in the above example. The Protocol tool is similar to the FdwfDigitalUart/Spi/I2c operation. The encoding/decoding takes place in the device, storing only the relevant samples for the protocol, like on SPI clock rising or falling edge, or detects UART starts and stores the required ~9 samples-bits. In the above example you can decode multiple UART lines from the same captured data, like: Dim rg0 = decodeUart(rgData, cSamplePerBit, 0) 'DIO-0 Dim rg1 = decodeUart(rgData, cSamplePerBit, 1) 'DIO-1 Dim rg2 = decodeUart(rgData, cSamplePerBit, 2) 'DIO-2 ... The cSamplePerBit should be Double.
  46. 1 point
    Hi @m72 The preview is further fixed. I hope there are no more issues with this: https://forum.digilentinc.com/topic/8908-waveforms-beta-download/ Here you have the project: EMU_2CH_EACH_V10 (2).dwf3work
  47. 1 point

    Accessing GPIO through PS

    Hi @HasanWAVE Pin 14 won't work with the Arty Z7, as it corresponds to MIO 14, which is connected to the UART on the Arty Z7, rather than a button or switch. The Arty Z7 doesn't have any switches/buttons/LEDs connected to the Zynq's MIO pins. This means that to use the PS GPIO, you need to enable GPIO EMIO (extended MIO), which routes its signals through the PL. This allows you to connect and constrain the EMIO GPIO pins as you would any other GPIO interface in the IP Integrator. Unfortunately the EMIO can't be connected to the components in the board files, however, you can still make the EMIO GPIO bus external and constrain its pins with an XDC file. The EMIO GPIO is enabled through the Peripheral I/O Pins screen when re-customizing the Zynq block. You can then set the width of the bus through the MIO Configuration screen, under I/O Peripherals / GPIO. For SDK, the xgpiops pin numbers associated with the EMIO pins are assigned in ascending order above all of the MIO pin numbers - so, in the case of having only an EMIO GPIO interface with a width of 4, the pin numbers are 54, 55, 56, and 57. Note that the first 32 EMIO pins use the bank number 2, and that the way that the interrupt example creates the interrupt enable bit mask passed to XGpioPs_IntrEnable doesn't work with pin numbers greater than 31. I've attached a modified version of xgpiops_intr_example.c in the spoiler below that works with button 0 of the 4-button GPIO EMIO as described above. If you want more depth, there's some more information and references to Xilinx documentation in this thread from the Xilinx forums. Thanks for the question! -Arthur
  48. 1 point
    Hello @jpeyron, thanks for the responses. I'll try that the next day as I'm away from the desktop now and will report whether it works or not. 😀
  49. 1 point

    WaveForms Live Math Function Not Working

    Hi @Bogdan50, I have asked our firmware engineer about this; I was also not able to get the math function to work with the OpenLogger. Thanks, JColvin
  50. 1 point

    Genesys 2 FMC trace length

    Hi Natsfr, Here is the length for each GTX lane. DP0_C2M_N, Signal Layers Only, 88.4738mm DP0_C2M_P, Signal Layers Only, 88.4374mm DP0_M2C_N, Signal Layers Only, 85.3115mm DP0_M2C_P, Signal Layers Only, 85.2439mm DP1_C2M_N, Signal Layers Only, 83.6574mm DP1_C2M_P, Signal Layers Only, 83.6685mm DP1_M2C_N, Signal Layers Only, 84.467mm DP1_M2C_P, Signal Layers Only, 84.4307mm DP2_C2M_N, Signal Layers Only, 87.9247mm DP2_C2M_P, Signal Layers Only, 87.7015mm DP2_M2C_N, Signal Layers Only, 83.7533mm DP2_M2C_P, Signal Layers Only, 83.717mm DP3_C2M_N, Signal Layers Only, 88.5627mm DP3_C2M_P, Signal Layers Only, 88.5627mm DP3_M2C_N, Signal Layers Only, 88.0048mm DP3_M2C_P, Signal Layers Only, 87.8988mm DP4_C2M_N, Signal Layers Only, 85.605mm DP4_C2M_P, Signal Layers Only, 85.5874mm DP4_M2C_N, Signal Layers Only, 88.6059mm DP4_M2C_P, Signal Layers Only, 88.4302mm DP5_C2M_N, Signal Layers Only, 85.8485mm DP5_C2M_P, Signal Layers Only, 85.8844mm DP5_M2C_N, Signal Layers Only, 87.0384mm DP5_M2C_P, Signal Layers Only, 86.9516mm DP6_C2M_N, Signal Layers Only, 88.4989mm DP6_C2M_P, Signal Layers Only, 88.494mm DP6_M2C_N, Signal Layers Only, 85.889mm DP6_M2C_P, Signal Layers Only, 85.7132mm DP7_C2M_N, Signal Layers Only, 87.3225mm DP7_C2M_P, Signal Layers Only, 87.3225mm DP7_M2C_N, Signal Layers Only, 87.5185mm DP7_M2C_P, Signal Layers Only, 87.3185mm DP8_C2M_N, Signal Layers Only, 88.7324mm DP8_C2M_P, Signal Layers Only, 88.7324mm DP8_M2C_N, Signal Layers Only, 86.5751mm DP8_M2C_P, Signal Layers Only, 86.4853mm DP9_C2M_N, Signal Layers Only, 86.7981mm DP9_C2M_P, Signal Layers Only, 86.7981mm DP9_M2C_N, Signal Layers Only, 87.3832mm DP9_M2C_P, Signal Layers Only, 87.3832mm and all of the pins on the FMC are differentially paired. cheers, Jon