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Showing content with the highest reputation since 02/13/19 in all areas

  1. 3 points
    In your constraint file, the ddc pins have lowercase "ddc_scl_io" and "ddc_sda_io". Your block design has the port in uppercase "DDC". The case must match. Try editing your constraint file to have "DDC_scl_io" and "DDC_sda_io".
  2. 1 point

    Vivado Bitstream Generation

    I should mention that the Zynq is a whole different (more complicated) deal than regular FPGA devices. The Zynq has an ARM that has to be tied off if not being used. You can find information about this on the internet. The tool flow is more complicated. I suggest that you target a different board/device once you've had success creating a configuration bitstream from the original sources. Don't worry the objective isn't to run your code in hardware yet. As much as I like the FPGA devices with a hard ARM processor core subsystem I would never recommend using that platform for beginners to FPGA development. Even if I assume that someone has some knowledge and skill with an HDL a lot of the battle involves getting to understand the tools ( a particular version of the tools ). Find a cheap plain old FPGA board to figure all of this out using only HDL sources. I use HDL only until I absolutely have to have a programmable processor and then turn to my ARM based devices. Back in the days design tools involved pencils, quadril paper, and lot's of cranial heating. The software based tools weren't perfect but they were generally reliable once you figured out their peccadilloes. In this century doing anything useful involves a little mental preparation, some skill and ingenuity and wrestling with belligerent tools that change with every version release and bugs that come and go. Fighting the tools can be 60% or your effort. Don't add complications that aren't necessary. To paraphrase a quote from Einstein: "Everything should be as simple as possible; but no simpler". This advice works on every level of human endeavor.
  3. 1 point

    Vivado Bitstream Generation

    Hi @Hunaina I do not have much experience migrating ISE IP Cores to be usable in Vivado. Here is the master xdc for the Zedboard. Here is the ISE to Vivado Design Suite Migration Guide. Edit: Here is a forum thread that might be helpful for your project. thank you, Jon
  4. 1 point
    Hi @Deskarano, Thank you for the information; the voltage all look pretty good to me as well aside from the 5V. How are you powering your board? If you are powering it via USB (direct to PC or USB hub?), could you test that voltage? You can access it by measuring between the underside of J13 (the regulator vs USB power jumper) and J11 (an unloaded single pin next to the Ethernet port); this value should be pretty close to 5V (mine is 4.98V). Also, did you get the opportunity to try a different USB cable or computer (to see if that affects power delivery)? Thanks, JColvin
  5. 1 point

    How to install and use djtgcfg?

    Hi @aeon20, I have responded to your other thread. Lets continue using just the one thread here. thank you, Jon
  6. 1 point
    WOW ! WaveFoms Beta 3.10.2 is out, and has almost all the features I asked for (and much more) 😀 Impedance Analyzer: - voltage, current and custom plots - edit Meter list - Resistance mode for Meter, Frequency DC option - step mode in Time view Netowrk Analyzer: - step mode in Time and FFT views - amplitude table and custom function Thank you very, very much attila. WaveForms is a great software and Digilent is a very good company that cares about the customer
  7. 1 point

    Vivado and SDSoC with purchase

    Hi @kwilber, In addition to the device family limitations @kwilber listed I also believe that the Webpack edition does not support the Kintex device family as well(Genesys 2). Its my understanding that with the paid editions some additional IP Cores become free to use. thank you, Jon
  8. 1 point

    XADC tutorial missing files

    I just now downloaded the project from here. The zip file has the .xpr file in the vivado_proj directory as shown below
  9. 1 point

    sdsoc_opencv error

    The errors are generated because: 1. You try to use VideoCapture function. As I mentioned here, you cannot use that function and you don't need it. Remove it. Modify the algorithm to use a simple cv::Mat as input. 2. no member named 'imshow' in namespace 'cv' and no member named 'waitKey' in namespace 'cv' were solved here. Make the needed changes.
  10. 1 point

    Vivado and SDSoC with purchase

    The webpack version limits the allowed devices. For example the webpack does not support the virtex-7 device family. It also restricts the zynq family to the smaller devices. Xilinx lists the supported devices here.
  11. 1 point


    Okk Thank you for this guidance..will definitely refer this link
  12. 1 point
    Thanks this solve my problem. By VH
  13. 1 point
    Nianyu Jiang

    PmodIA Extension

    https://www.researchgate.net/publication/236037769_A_four-electrode_low_frequency_impedance_spectroscopy_measurement_system_using_the_AD5933_measurement_chipt this is the paper I am talking about. Thanks for the further explaination, I start understanding the working principle and trying to combine everything. Will go back to you once I have more question. Nianyu Jiang
  14. 1 point
    I see where your question comes from... the Arty Z7-20 board file does not define the hdmi ports so they are not available in the Board window. In that case, you can use "Make External". For example, once you place the rgb2dvi IP on the block design, you can right click on its TMDS port and select "Make External" from the context menu. Vivado will add the port and assign a default name. To rename the port, left click on it and in the "External Interface Properties" window, type hdmi_out. The block design will update with the updated name. You can follow the same process to add the dvi2rgb IP and create the hdmi_in and hdmi_in_ddc ports. Your project will need a constraints file with the pin names set to match those in the block design.
  15. 1 point
    Hi @Deskarano, I apologize for the delay; I thought I had sent this off, but apparently not. In the meantime I relooked at this and realized that we inquired about capacitors that are for a newer revision of the Arty, rather than the Rev C board. The newer revisions have some additional protection and capacitors for the DDR memory, so a lot of the numbering system was shifted around, while the board between revisions functionally remained the same. The correct schematic for the Arty Rev C is available here: https://reference.digilentinc.com/_media/reference/programmable-logic/arty/arty_sch.pdf. With that, here are the correct capacitors that line up with the voltage rails we were intending to have you measure: C143 (should be 5V): C64 (should be 0.95V): C162 (should be DDR 1.35V): C159 (should be 1.8V): C152 (should be 3.3V): I have attached a picture for your convenience showing the location of C143, C162, C159, and C152. C64 is on the back of the Arty underneath the letter 'N' in the "Xilinx" silkscreen label. I apologize for the confusion and let me know what you find. Thanks, JColvin
  16. 1 point
    @askhunter, Are you asking how I created and named the hdmi_in and hdmi_out ports in the block design for my Zybo-Z7 project? If so, once I started a new project selecting the Zybo-Z7-20, I created an empty block design. I then selected the "Board" window. The Zybo-Z7-20 and its available components were listed. Under the HDMI branch, I double clicked on the "HDMI in" component and clicked on OK in the dialog that popped up. The DVI to RGB IP block was added to my block design along with the appropriate ports. I did the same thing for the "HDMI out" component. I did the same thing for the system clock component. Then I ran block automation to add the reset line then added connections between the blocks as necessary and ended up with this.
  17. 1 point
    Hi @askhunter, Both the Zybo-Z7 and the Arty-Z7 have an HDMI IN and a HDMI OUT port that are not bi-directional. The Arty-Z7 and the Zybo-Z7 only have the physical hardware to provide the described function I.E. HDMI In and HDMI out. So as an example, you would not be able to use the HDMI IN port as an HDMI OUT port instead. The original Zybo has a HDMI I/O. The HDMI I/O can be used for either hdmi input or hdmi output but not both input and output at the same time. thank you, Jon
  18. 1 point

    Vivado and SDSoC with purchase

    Hi @Sduru, Welcome to the Digilent Forums. The list that comes with Vivado currently does not come with Digilent's board files included. You will need to install the board files as @kwilber describes above. thank you, Jon
  19. 1 point

    Vivado and SDSoC with purchase

    To add Digilent boards to the list of boards in Vivado, you will need to download and install the Digilent board files as described here.
  20. 1 point
    Hi @contraption, You'll actually be in SPI Mode 1 (clock idles low and the data is sampled on the falling edge of the clock) since that's what the IC for the DA2 needs. This is what I used on the ICSP header for an Arduino Uno (I don't have a Leonardo available). Let me know if you have any questions. Thanks, JColvin
  21. 1 point

    PmodIA Extension

    Hi @Nianyu Jiang, 1. I believe this is high pass filter to move the offset. -- That is correct. 2. I believe this is Op-Amp, but why do we need this? -- This op-amp is arranged as a voltage follower, to help further stabilize the signal. 3. I think this is a switch or multiplexer, but why do we need this here? & 4. Same as part 2. -- This is part of the feedback amplifier that goes from the received signal (after passing through the device under test) to internal ADC, detailed further on page 15 of the AD5933 datasheet and shown again in Figure 24 on page 18. As this user mentions in their post, driving SEL to ground sets the feedback resistor (what the mux/switch is selecting) to 100 kOhms and setting SEL to Vdd sets the feedback resistor to 20 Ohms. The choice in the feedback resistors (as well as the gain factor and output excitation voltage range selected in the Control Register) affects the result which needs to stay within the internal ADC input range of 0V to Vdd. To figure out if the gain through the system is within the ADC voltage input range, follow the calculation presented on page 18: You'll note that this inherently limits what can be reliably measured with regards to the unknown impedance depending on what settings you have chosen, which is also noted in the user post I linked to earlier. Let me know if you have any questions. Thanks, JColvin
  22. 1 point
    And.... I have this sense that if you keep describing what you did you will answer your own question. I don't have enough information yet to help. [I confess that I haven't bothered to read through your code] Verbalizing problems, if you go into enough detail, is often a fairly reliably way to resolve them. Sometimes it helps to have someone throw in a good question or two.
  23. 1 point

    Cmod S6 - Multilayer?

    Consider that the FPGA on your module has 196 balls. The A7 versions have 236. You can answer your own question by thinking about how one gets all of those surface mount pads to ground, voltage and signal traces.
  24. 1 point

    Cmod S6 - Multilayer?

    Hey @TireV What your are referring to is called the stack-up and refers to the layers of non-conductive prepeg material and copper plating that makes the planes and signal traces. You are correct that as a user of the CMODS6 ( or any small form module for that matter ) has an interest in this part of the board. The thickness of the module is not necessarily proportional to the number of layers. What is important is how much and how thick the copper on the prepeg layers is because large ground or voltage planes thermally connected to the IC substrate are the only route for thermal energy to be 'wicked' away from the active devices on the module. More layers is not necessarily better. PC motherboard manufactures for a while there saved cost by using 2 layer boards but there is a lot of engineering and expensive tools required to do this right. I responded to your question because it's not just a good question but a nice segue into this comment that you brought to mind. FPGA timing performance is temperature dependent. There are industries that like miniaturized high performance modules and take extreme efforts to minimize and or manage heat. These are very expensive. These modules also [should] come with very detailed testing results that indicate what the upper level of performance the modules can handle and how much heat it dissipates into the system. When someone offers you a very cheap and tiny module you can assume that thermal issues are something to keep in mind when you use it. It's not just performance that heat has on and FPGA but longevity as well. I happen to very much like and uses the CMOD-A7 modules, as well as other modules from other vendors. I also keep in mind that it's possible to run into thermal problems if I expect too much out of them. But, like a speciality tool; when you need it it's nice to have around. I have no expectation that a vendor of cheap modules tests much less would specify in their advertising performance, environmental, or thermal information. If I was buying a $100K module with an FPGA then I would insist on this information. So I offered a narrow slice of a proper reply to your question. I do encourage you to lean more... the information is out there, often as documentation on EVMs that will supply all of the PCB design information as well as the guidelines that were followed in making them.
  25. 1 point

    please help me

    Hi @Asmaa_as, I have not used labview with the EE board. With that being said here is the WaveForms Toolkit for LabVIEW by Digilent. thank you, Jon