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    @elodg Thanks for your reply! I tried with Antivirus (Avira) turning off and other networks (Wi-Fi) and doing the same by generating new bsp and project. Fortunately, it is successful and I could open it up with telnet also. I repeat the whole with turning on the antivirus and Wi-Fi, but it gives the below result. Thanks for your support. I guess that the regenerating of bsp and project made it right. Thanks again. If I am not wrong I think I need to modify echo.c for adapting the code for my own applications.
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    Indeed, the project included in the workspace does not work. But if you create a new "lwip echo server" example project in SDK along with a new BSP, that works. Make sure any software firewall is off or allows ping packets.
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    To add to my comments on possible performance problems: Running this masking algorithm in the Zynq PS will likely be inherently slower than running it in the PL. Adding a stage to the output pipeline in hardware is likely going to be a better approach, with the caveat that it would be a significant amount more work. This stage would likely need to be created as a custom IP core that either: 1. Takes in an AXI stream and outputs an AXI stream, probably placed near the AXI stream converter IP in the pipeline (if I am remembering things correctly, I don't have access to Vivado at the moment). There may be a xilinx provided IP that does something like this, but I am unsure. 2. Takes in VGA signals and outputs VGA signals, placed directly before the output port. This approach would require more work in detecting the pixel position and resolution of the data stream, but would avoid the complexity of AXI. For the time being though, it is still worth trying to make the algorithm work in the PS, this is just a hypothetical for if the performance of the PS design is unacceptable. Thanks, Arthur
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    @Shuvo Sarkar Are you selecting the output frame using the serial interface to the demo? I assume that what is currently being displayed on stream is a single captured frame with the masking applied? If this is the case, it is likely possible to modify the demo further so that it runs the "copy, scale, and mask" algorithm repeatedly. By this I basically just mean placing the modified DemoScaleFrame function inside of a while loop. Caveat: I not certain what the performance cost of doing this would look like, so it may be worth looking into how quickly the algorithm runs (perhaps a little outside of the scope of the current discussion). Thanks, Arthur
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    Hi @flexible111, Changing the font size will be far more difficult. Currently the OLEDrgb libraries are using a pre-generated file that defines the 8x8 pixel area for each printable character and the functions printing individual characters all all based off working with that size. With that in mind, there are four options to change the font size available: - Change the pixel pattern file that the Pmod OLEDrgb uses (called CharFont0.h) - Create the custom characters that you need and individually print those custom characters - Individually draw them pixel by pixel - recreate the functions to print each character with a large pixel area Unfortunately, Digilent won't be able be to offer much help in this particular customized endeavor though. Let us know if you have any more questions. Thanks, JColvin
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    Hi @flexible111, I am glad that you were able to get it working. You would have to alter the chrfont0.h here as well as the drivers themselves and how they index the struct in chrfont0. Changing the preset font size would not be an easy task. thank you, Jon
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    Hi @Jay Sngh, There is no license provided with the Basys 3 board. We would suggest using Vivado's design edition which can be downloaded and used on a non-design edition target such as the Basys 3 without a license. If you are concerned with Vivado's size and are not going to use a virtex or kintex fpga you can also uncheck these boxes in the initial download options. cheers, Jon
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    What are you talking about? I opened 10.Anvyl_Ethernet_Demo in XPS 14.7, and upgraded the project to the latest version along with IPs. There are no IPs missing, but there is an error message upon bitstream generation that is answered here: https://www.xilinx.com/support/answers/62380.html Just double-click on axi_ethernetlite_0 and uncheck Include PHY I/O constraints, as described in the AR. Then, the bitstream gets generated successfully. Exporting to SDK works, but BSP needs to be regenerated to upgrade to the latest library version. Then the application compiles as well. I don't have a board at hand, but you can try it yourself using the upgraded project I attached. 10.Anvyl_Ethernet_Demo.zip
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    Last night I measured the speed of RF waves in a generic 10m TV coax using the AD2, a socket and two resistors Why?: I'm trying to build a cheap colinear antenna for receiving 1090MHz plane broadcasts. To do this I need to know the "velocity factor" of a cable. The setup: Connect the AD2 wave output and the input of the first scope channel (the reference channel) to one end of a 330 ohm resistor, Connect the other end of the 330 Ohm resistor, the second scope channel, and one end of the 100 Ohm resistor to the center pin on the socket. Connect the other end of the 100 Ohm resistor plus the AD2's ground connection to the shell/ground connection of the socket. Running the test: Without the cable plugged into the connector, run the Network Analyzer, from 1 MHz to 10 Mhz - it should be a pretty much flat line. Then connect the cable and test again. There will be a 'dip' somewhere 5 or 6 MHz. What is going on: The 330Ohm+100Ohm resistor acts as a signal divider, and has an AC impedance of about 75 ohm, matching that of the Coax cable. Because the cable has an open end, it is acting as an 'open stub' and any signal that is injected into the cable reaches the end of the cable and is reflected. The source and reflected signal interfere with each other, and where the signal is destructively interferes with the source signal the "dip" is seen. The bottom of this dip is when the cable is 1/4th the wavelength of the RF signal - so if the driving signal is at 90 degrees, the reflection is at 270 degrees, making the measured signal much weaker. Results: For a 10m (30 ft?) cable the dip was at 5.634MHz. That makes a full wavelength 40m long. That gives a speed of propagation of 5.634MHz * 40m = 225,360,000 m/second - about 75% the speed of light in a vacuum.
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    Hi @smarano, I reached out to our design engineer and found that access to the VBAT pin on the Cmod A7 is impossible. There’s no way to attach a coin cell to just the VBAT pin because it’s hard tied to the VCC1V8 rail and the trace that connects the FPGA ball to the via that goes straight to the VCC1V8 polygon is underneath the FPGA. Therefore a cut and jump is not possible. We didn’t have space for an auxiliary JTAG connector on the CmodA7, which means that the JTAG signals aren’t routed out to a header. That will make attaching an external program very difficult, if not impossible. thank you, Jon
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    Hi @amkichu, The only thing I have been able to find is Here is the Anvyl Demo Project Suite. I have reached out to my co-works to see if we have an OOB demo that contains all peripheral interfacing. thank you, Jon
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    Could you try using Tera Term instead? I am unfortunately not super familiar with the SDK console, and have had trouble using it in the past.
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    Using posedge on fabric logic can have a few issues. If the fabric-generated clock doesn't come directly from a register -- eg if you have c = ( a == b ) -- then you can generate glitches. It might be that as new values of a,b are being propagated to the logic the condition is met one or more times within a normal cycle. This can generate short pulses which might trigger some registers but not others. This is also true for async set/reset logic. When a fabric generated clock comes from a register or doesn't have glitches, the clock might be ok to use. There are still some issues. First, this design style is more prone to generating a larger number of clocks, which might exaust the clock routing for a given clock region. Second, the clock might will have routing delays that change from build to build as well as over temperature. This means the clock must be treated as asynchronous to other clocks in the design. These are not insurmountable issues -- you can create directed routing constraints (DiRt) to ensure the same routing is used each build. You can ensure safe clock-domain-crossing logic. However, this requires extra effort in design/sim/constraints. This is another issue -- that the fabric clocks appear easier to use. Add to this that they often work fine and they teach novice bad practices. The fabric generated clocks also can have additional jitter, duty-cycle distortion, etc... This generally isn't an issue as these clocks tend to be run at Fmax/10 or lower. For the original post, the synthesis tool generally is allowed to optimize the circuit. It is possible the tools will decide to share adder logic or other logic when it can detect mutual exclusion. The tools might opt to place the majority of the ALU into a DSP48 slice for example.
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    @gcp Yes. BRAM is located within the FPGA fabric (PL), rather than on the PS. Further, most FPGA's have BRAM's within them as well, Dan
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    Hi @yassin, This can be helpfull for you Petalinux quick guide See you!