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  1. 2 likes
    Hi @jeffjackson, Here is the Statement of Volatility Arty A7-35T , Statement of Volatility Arty_Z7_10 and the Statement of Volatility Arty_Z7_20. thank you, Jon
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    Hello, I've been having a lot of fun with the VGA Pmod. I thought other forum members might appreciate a couple of tutorials I've produced with it. Part 1: Intro to VGA and basic animation: https://timetoexplore.net/blog/arty-fpga-vga-verilog-01 Part 2: Bitmap display using your own image: https://timetoexplore.net/blog/arty-fpga-vga-verilog-02 Both are written in pure Verilog, so it's (hopefully) easy to understand what's going on and adapt for your own projects. Feedback welcome, Will
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    Finally working! Brief description: On right monitor is ssh session from my devel PC to Zyboz7-20 where I start Qt applications (framebuffer and sysinfo on attached picture). Front monitor is connected to ZyboZ7-20 HDMI output port. Monitor resolution is SXGA (1280x1024@60fps). FPGA: - Build with Vivado 2016.4 - Data path for HDMI output: /dev/fb0 DDR image buffer --> Zynq AXI HP port --> AXI Protocol Converter IP (AXI3 to AXI4) --> VDMA IP (mm2s only) --> AXI4 Stream to Video IP --> Digilent RGB to DVI IP --> HDMI connector Video control signals are from Video Timing Controller IP (1280x1024p, Pixel clock is 108MHz). On SD card: - Boot image containing: FSBL, U-boot (Xilinx git tag xilinx-v2017.3), LX 4.6 kernel (configured and build from Xilinx git tag xilinx-v2016.4) and Buildroot-2017.08.1 - Modified Simple FrameBuffer driver. - Xilinx DMA driver. - My custom driver to control FPGA modules (VTC, Xilinx Performance monitor and some others I have in design). - Cross compiled Qt-4.8.6 examples (analogclock, framebuffer) and Qwt-6.1.3 examples (sysinfo, cpuplot). TODOs: - Simple FrameBuffer driver does not starts Xilinx DMA driver transfers, so I have to configure VDMA IP registers manually. But this is good enough for my first run and proof of concept. I will switch to and continue with DRM device driver. - Inputs (mouse and keyboard) to control Qt application.
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    Thank you for info. In the meantime I managed to make it work with ADI AXI HDMI DRM driver by modifying it and combining it with Digilent encoder code. I use/build all involved drivers as loadable (insmod/rmmod) modules, so I was able to trace down all needed changes. Now it works perfectly with Xilinx VDMA with all other features (Plug-able EDID monitor detect, handling DPMS modes, ...). My GUI needs on ZyboZy-20 are satisfied with Qt and frame buffer (no need to extend to X infrastructure). Attached is device tree. zyboz7-20.devicetree.zip
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    Vivado is not fast, but it's a big improvement over its predecessor (Xilinx ISE). I found Altera Quartus to be quite slow also. You can enable reuse of place and route results when you make small changes to the design and that will save some time during development. It still has to do synth_design and opt_design before reusing placement/routing results, but it does save time. Build times increase with design size, but they increase faster if the toolchain has to work hard to try to meet timing constraints.
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    Hi Jon, Thank you very much for putting these together. This is very helpful and greatly appreciated! Cheers, Jeff
  7. 1 like
    Hi @Elect_GD, You will need to use an embedded linux platform to use the OTG USB on the Zedboard. I believe that you can also accomplish your desired verification using an embedded linux platform. The Zedboard comes with a sd card having a basic embedded linux platform on it. Here and here are some tutorials and projects with petalinux for the zedboard. Here is a wiki/tutorial for petalinux as well. thank you, Jon
  8. 1 like
    Hi @spri The constant is generated specifying zero low/high counts. Setting start with low, low-count zero and high to a non-zero, when running after the divider init expires it will change to and remain at high value.
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    Hi @flexible111, I apologize, I was out of the office the last couple of days and did not have access to a Nexys 4DDR. I will get to this as soon as I can. I am sorry for the inconvenience. It may be a couple of days due to activity on the forums. thank you, Jon
  10. 1 like
    Hi @Bryce, We do not have a 3D CAD model for the Right angle header at this point in time. I have asked the appropriate engineer to see if they can create one or find out the appropriate dimensions for you. Thanks, JColvin
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    Hi @elico, The webpack edition is free. It covers what most users will want to do with their fpga's. Here is a comparison table for the different editions of Vivado. cheers, Jon
  12. 1 like
    Hi @brandt1930, Unfortunately, we (Digilent) do not have any example code of our own for the Pmod RF2. I did find a couple of libraries designed for it though: one here that appears to be Arduino based and another one here that looks like it was created in an older version of MPLAB (8.83). I haven't tested either one of those libraries though, so I can't speak to their functionality. Thank you, JColvin
  13. 1 like
    Hi @jeffjackson, We are creating the Statement of Volatility for the Arty Z7 and Arty A7 for you. This will take a couple of days. Our boards come with the OOB demo loaded in the flash. For the Arty it is the General I/O demo on the resource center. I have attached the boot.bin for the OOB demo on the Arty-Z7. Here is a xilinx forum thread that discusses erasing the flash. thank you, Jon BOOT.bin
  14. 1 like
    Hi @spri The digital-out/Patterns controls all the lines a the same time with trigger-wait-run-repeat. You could use the FDwfDigitalOutDividerInitSet and FDwfDigitalOutCounterInitSet to have delay between lines like this:
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    Hi @ATIF JAVED, From what I know, none of our FPGA boards have a built-in DAC, but we do have a Pmod DA3 which should meet your output sample rate that you need. Alternatively, the Pmod R2R will accept 8-bits in parallel up to 25 MHz. As for the ADCs, I believe that all of our FGPAs have an XADC that will support a 500 kHz bandwidth at 1 MSPS as per XADC section of the Xilinx 7-Series Overview documentation. Additionally, the Pmod AD1 and Pmod AD2 both have a full power bandwidth at 3 dB greater than 10 MHz as per the datasheets for the embedded chip. Let me know if you have any questions. Thank you, JColvin
  16. 1 like
    Bits are arriving at the much faster bclk rate. Entire samples are arriving at the lrclk rate. (lrclk rate == sample rate). Latency through the FPGA is going to be on the order of four or five samples—closer to 1/10 ms.
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    Hi @kraiskil I suspect the ferrites (50mOhm/1A BK2125HS470-T) on USB GND and VCC got damaged or weekend on your board. These are below the USB plug, on the edge of the bottom side, and are intended for noise filtering, but also act as a fuse to protect the computer beside D28, in case of connecting the device ground to high external voltage. https://reference.digilentinc.com/reference/instrumentation/analog-discovery-2/reference-manual#usb_power_control
  18. 1 like
    This Verilog I wrote last year works with the CODEC on the original Zybo board. It implements both transmit and receive I2S interfaces running at 8kHz from a single 12.288MHz clock input. https://github.com/bikerglen/zombie-containment-unit/blob/master/zcu-prop-control/rtl/dtmf/i2s_8kHz_i2s_format.sv
  19. 1 like
    Hi @flexible111, Using the board file along with the JA, JB... ports should not effect the use of the flash. Here is the Vivado Version 2015.1 and Later Board File Installation tutorial. To clarify you have the mode jumper JP1 set to spi flash? I left the jumper set to spi flash to program the Nexys 4 DDR and left it set to spi flash when powering on the board. Can you share your project so i can try get your working from the flash? thank you, Jon
  20. 1 like
    @ATIF JAVED, So .... your issue with the output of the FIR compiled decimator is that it doesn't remove the runup? Why not just remove it yourself? Either within your own logic or after you bring the filter's results back to your PC to examine? In many if not most of the signal processing applications I've dealt with, the signal is an infinite stream of numbers and the transient just washes out quickly--enough so that it's not really relevant. It seems like the FIR filter produced this type of result. There are other applications where the DSP is applied to a finite data set. It's just that these have been the exception rather than the rule in my humble experience. In these examples, the transient response becomes relevant. For testing a filter, knowing when/where the transient begins can be a difficulty. For testing a decimator, it can become even more of a challenge, as the test harness must now also know the phase of the decimator. Dan
  21. 1 like
    Here's a link to a post that discusses more about what is required to debug an FFT component on an FPGA, and specifically to what I was trying to describe above. Dan