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  1. 2 likes
    @Riteshkakkar, That's a much longer topic, and well beyond the bounds of this forum. While you may find some folks here who have worked on satellites built for radio communication, the full topic of how to do so is ... typically beyond the ability of any one individual. You should also know that the space environment isn't very friendly to computer chips. Unlike the earth where items can be electrically connected to ground, satellites in space have no solid ground. The space environment is known for accumulating charged particles on satellites until they experience "lightning" from one side of the satellite to the other. It's also known for tiny particles of radioactive energy that can enter into a circuit and toggle bits within an algorithm. Building chips and algorithms to operate successfully in this environment is a study in and of itself. Most chips, FPGAs included, can't handle this environment. It usually takes several years of working with a particular chip design before that design can be "space qualified". In the process, the chip becomes quite out of date. As a result, the electrical technology launched into space tends to lack what is on the earth by several years. Dan
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    @Tickstart From my experience you will be asked questions to verify claims you put on your resume. Expect, for example, to be asked HDL syntacsis, implementation of I2C protocol, digital filters, etc. Expect also several people who might be your coworkers will talk with you to get the feel and to test your skills. Everything depends on what is the company doing. Most of US companies don't train employees, they might pay for their classes but that's about all. If you are lucky and the company eager to higher you then they can give you time for training. Once more from my experience companies hire people who can bring something the company doesn't have. Think about it and decide if you have something to offer, otherwise spend time on learning. During the Internet boom one of my friends after reading a few software tutorials managed to be hired as a software developer. Needless to say he didn't last long and his experience was painful since he didn't have developer skills.
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    Hi @Tickstart, Since your question was not directly related one of the Digilent FPGA boards, I have moved it to a different section of the Forum to hopefully produce less confusion for other readers. As for my personal perspective, I'm in a bit of an odd spot since I have a degree in chemical engineering rather than EE/CS/CompE, yet here I am helping answer questions on all of those things, meaning I don't have a lot (i.e. any) formal education with HDL design. But like Dan hinted at, I'd like to make sure that the people to be hired can "engineer" their way through a problem, not just hope that a single approach works for everything. Thanks, JColvin
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    Apparently the problem was in github. Using git config --global url."https://".insteadOf git:// Seems to fix the issue. I had already modified the problematic .bb files by hand in a previous attempt, but then it didnĀ“t work
  5. 1 like
    Hi @kvantumnuly, I heard back from our layout person at Digilent with regards to the traces. Here is what they told me: Thank you, JColvin
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    Hi @Riteshkakkar, Did you get a chance to watch the video that was pointed out in the blog post? It goes through the whole process of setting it up. Thanks, JColvin
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    Hi @Riteshkakkar, To a certain extent, with enough work, you can build almost anything you like on an FPGA, so it is not possible to list all possible projects to be made on a FPGA. Loosely speaking, you could say that the possibilities an FPGA (or a microcontroller/microprocessor for that matter) are endless. Thanks, JColvin
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    @deppenkaiser, your macro to Access the Memory is wrong, if you would use the right macro, then your Offset calculation would work. @sbobrowicz: I found the error in my Offset calculation, thats could be also the reason for my uio issue! :-) I will tell you the results.
  9. 1 like
    Hi @JColvin The FTDI EEPROM reprogramming is only and only needed when the device is not detected/recognized by the software (Adept, WaveForms, Xilinx SDK...). This happens when the content (Digilent ID, SN) was erased by another application like FTProg. Unneeded reprogramming could lead to missprogramming the device, like programming AD as AD2 and we end up with more hassle to solve...
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    Hi @Famartinez76, I have moved your question to a more appropriate section of the Forum. As a confirmation, in your main computer (it looks like you are using Windows), does the AD2 show up as a USB Serial Converter in the Windows Device Manager when you connect it? I personally haven't seen this error before, so what I would try to do is reload the data in the EEPROM since it appears that the AD2 is properly getting power from the host computer. You can do this by pressing Alt+F11 on the Device Manger screen of the WaveForms software and then clicking on the "My device is not listed" button that appears at the top to find your device and re-program it. As Attila recommends latter on in this thread, don't do this if your device is already correctly recognized. If this does not resolve the problem though, I will need to pass you off to @attila who is much more familiar with the WaveForms software. Thanks, JColvin
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    Been meaning to document the manual Linux on Arty without petalinux fully so finally here it is. I attached a PDF file as its easier to do it that way. Any questions ask away. Firstly thanks to Jeff of http://www.fpgadeveloper.com as I used his base design as the start, see above. Ping me oberman.l@gmail.com for files, too large to attach here Linux_on_artA7_manual_build.pdf
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    Hello @BYTEMAN, Taking a look at this thread, you may need to re-generate your BSP sources, or potentially delete it and create a new one. I would also make sure that all of the SDK settings (I'm not certain if you have changed any) are on their default settings. Thanks, JColvin
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    @Tickstart, All good questions. I've avoided most of them by avoiding hiring so far, although I am considering putting my first development team together, and so I'm starting to wonder what questions I'd ask from the other side of the divide--if I chose to do so. To be clear, I've been offered the opportunity to work with a group of unpaid interns, and to lead them through the process of creating an ASIC digital design. This is not something I've done before, and ... I'm not (yet) sure I'm up to the challenge. So, I'm just thinking this over. If I did it, I think I'd be doing a *LOT* of teaching ... That teaching would probably start out with a course on how to use formal methods to prove that a design works, how to test a design in simulation, and much more. That said, here's what I think I might look for in a digital design engineer should I choose to put such a team together: a *proven* Verilog capability. Sorry, VHDL designers--I wouldn't be looking for VHDL in my team. I'd be intending to use open source tools (yosys), and open source ASIC support for VHDL is lacking. By *proven*, I'd be looking for someone who has implemented a non-trivial design on hardware--the more complex the better. I wouldn't look for someone who clicked here and clicked there to build a design, I'd want someone who actually has the ability to design. I wouldn't really care too much about *how* it was done, just enough to know that it *was* done. For example, did you do simulation? Which tool did you use? How did you simulate hardware components? How did you go about finding bugs within your design? What methods did you use? What clock speed did you run at, with what hardware? Did you ever struggle with failing to meet timing? How did you solve that problem? What FPGA board did you implement your design on? How much of the resources on that board did you consume? Did you ever struggle to get that design to fit? If you were able to work on your design some more, what would you want to improve? Bonus points would be if I could examine the design on github. Among other things, I want to use these questions to weed out any designers who used Verilog to write software, or who were just placing the word "Verilog" on their resume without really having any background in using it. I'd also be looking for someone who was *real*: a human with faults who is willing to acknowledge they've made a lot of mistakes that they've then learned from. The last thing I would want on any team would be someone of substandard morality, and so I'd be using this criteria to try to weed that out as well. I'm also going to be asking about any experience using Linux or git. This might include, "How would you build a linux software package from source?", or "What is a git branch, and when would you use one?" In this case, I don't care if the answer is right or wrong, but rather if the individual can answer--again proving that he or she has the ability they say they have. Icing on the cake would be someone with all of the above experience who also had experience with computer science and specifically compilers, who was comfortable working in C++, who had experience with formal methods, digital signal processing, or even just a plain mathematical background. Being able to understand how to "prove" something is important when using formal methods and its a background that comes for free from a mathematician. Finally, given that the opportunity I'd be working with is probably less than entry level, I think I'd be surprised to even get all of this. Of course ... this assumes I accept the position. Either way, these are just the thoughts I had off the top of my head. Dan
  14. 1 like
    See my question here. git config --global url."https://".insteadOf git:// solved my github issues
  15. 1 like
    Hi @Manny The scope and awg lines are not available on the BNC adapter wire end (marked as NC) but only through the BNC connectors. Also notice the AC/DC jumpers for the scope inputs.
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    Hi @zyz You can also find shortcut to the SDK in the Start menu/ All programs/ Digilent/ WaveForms SDK or press the SDK button in the WF application.
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    Hi @BYTEMAN, I'm not certain on the differences between the two interrupt controllers, you will likely need to contact Xilinx to see if they have any additional thoughts or concerns on this. As for the SDK debugging behavior, according to this Xilinx site, the GDB mode is depreciated, so you will likely want to instead use the "Launch on Hardware (System Debugger)" option instead for some better results, as this Xilinx forum thread seems to indicate as well. Thanks, JColvin
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    Hi @BYTEMAN, I verified that on my cmod A7 project i was able to re-program the elf(step 4.1) on the flash without having to re-program the download.bit into flash(step 4.2). I will point this out to out content team as well so they can confirm while updating/fixing the sdk flash tutorial. thank you, Jon
  19. 1 like
    Hi @Manny, Effectively you would use BNC probes to attach to the BNC connectors on the Adapter and essentially treat them like an extension cable. The small black cable on the probes (at least on probes sold by Digilent) will need to be connected to ground since the BNC Adapter board is not set up to be differential. There is a tutorial on using the BNC Adapter board that demonstrates the use of the adapter and probes on our Wiki here: https://reference.digilentinc.com/learn/instrumentation/tutorials/bnc-adapter/start. Let me know if you have any other questions about this. Thanks, JColvin
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    The bit stream that hamster has provided is exactly what you would want to provide when you want to have the AD5 use a pseudo differential input with pin "A0" on the 6x2 header on the Pmod. When using the pseudo differential input though, you will also need to provide a a voltage reference on the pin "ACOM" on the 6x2 header on the Pmod. Because the Analog Devices chip on the Pmod is by default operating in bipolar mode, and with a gain of 1 as we have configured the Pmod, I would recommend using a voltage reference of 2.5V. As per the "Data Output coding" section on page 33 of the reference manual, bipolar mode will actually only convert the analog signal into 23 bits with the 24th bit (the first one in the string of bits in the acting as the sign bit. This sign bit will indicate if the analog signal you are sending the AD5 is above or below the ACOM reference voltage. It is fairly easy to enable other analog input channels by turning on their bits (such as CH1, CH2, etc in the Configurations register on page 27), but as Mike mentioned, the design can get more complicated as we start needing to read from multiple registers like the Data register and the Status register in order to tell us which channel the information in the Data Register applies to. Let me know if you have any more questions. Thanks, JColvin
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    The Pseudo bit is in the Configuration Register (register '010' ), bit 18 (page 27 of the datasheet). The power-on-reset value for the register is 0x000117. We want it set to 0x040117 (well, if we only want to set the Pseudo bit), or 0x040110 if the gain of 1x is desired, as per Mr Colvin's post. To do this, we need to write over the SPI interface. Whenever a new write to the ADC occurs, the first byte goes to the Communications Register (see page 22). These are the bits that need to be sent: 0 - active low write enable for the Communication Register 0 - active low write command 0 - REN(2),- The address of the register to write to 1 - REN(1) - The address of the register to write to 0 - REN(0) - The address of the register to write to 0 - continuous read off. 0 0 - must be 0. This is then followed up with the data that will be written to the Configuration Register ( in this case - 0x040110) So the stream of bits we want to send out are: 0001 0000 0000 0100 0000 0001 0001 0000 In the FPGA design code above,this can be done by setting the initial values of the shift registers: signal cs_shift_reg : std_logic_vector(63 downto 0) := x"FF000000007FFFFF"; signal mosi_shift_reg : std_logic_vector(63 downto 0) := x"0010040110000000"; [code=auto:0] So here what it looks like in simulation, as these registers are written while the design starts up: Just to reiterate, I don't have access to the PMOD, so all of this code has not been tested other than by me eyeballing that the simulation waveforms match what I think they should look like. You will need to do a lot of checking against the datasheet - you will need to read it very closely, and double check everything! Also, my initial understanding was that you only needed to read only one channel. To read many channels the design will get a lot more complex and may need to be structured differently, to include a more complex FSM to switch to different channels. Mike
  22. 1 like
    Hi i1116345, From a quick read of the datasheet, it seems that you need to send a few register writes to switch ADC into continuous sample mode, and then you can just clock the data in every time DRDY is asserted. You can take either the high road (with lots of levels of abstractions in your design) or the often-muddy low road (where you do all the work on paper, and then just make a design that achieves the desired result). The high road most likely involves a soft CPU, with a SPI peripheral interface, and software that talks SPI that will configure the device and retrieve the samples. The low road involves a long shift register to send out the SPI signals needed to configure the eight registers in the device, and then a simple FSM that clocks in the samples when they are available, storing the values into a flip-flops connected to the LEDs. So to me the low road looks to be something like two or three 128-bit shift registers (as it has to program up to eight 8-bit registers), a counter to act as a clock divider, and a small FSM that clocks in the samples . I know which road I would take - but that is just me. Mike