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Showing content with the highest reputation since 06/17/18 in all areas

  1. 1 point

    Show both channels scale

    Using the scope, is it possible to show channel 1 and channel 2 scale on the y-axis at the same time? Right now it only shows one at a time, and I have to click between the two. For saving screenshots it would be nice to have both shown at the same time.
  2. 1 point

    WF32 with PMod TC1: quatization noise

    Its fixed, I was too agressive on trimming and averaging (mean)
  3. 1 point
    @fandrei Not that I am aware of, but feel free to start one up here Update: still working on the push, hopefully it will come soon
  4. 1 point
    Hi @Sridhar Prasath Aruppukottai Ganesan, Can you attach a screen shot of what your block design looks like? For the uartlite you will need to right click on the uartlte out and select make external and then constraint the pins with the xdc. Are you using the zynq processor? thank you, Jon
  5. 1 point
    Hi @Sridhar Prasath Aruppukottai Ganesan, UART0 and UART1 are tied to the ps. If you are needing to connect these two modules to pmod ports through uart communication the i would use the axi uartlite or axi uart 16550. I would not use JE since this is tied directly to the ps and would be more difficult to get working. Is this project going to be baremetal through vivado/sdk or are you going to use embedded linux such as petalinux? thank you, Jon
  6. 1 point
    Hi @Sridhar Prasath Aruppukottai Ganesan, Could you be more specific about where the gps data and gsm/lte data is coming from? Are you going to use the pmod ports to connect to these devices and receive data? How are you planning on sending data to a remote server? thank you, Jon
  7. 1 point

    Nexys Video DMA Audio Demo is broken

    I followed your suggestion and just downloaded Vivado 2016.4. I tested it and it works on that version.
  8. 1 point

    ZYNQ -7020 Development Board OOB code

    Thank you for verifying the project creation script. Yes, I had done what you did. I also ran it without the "./" prepended and got the same results. However, what I did notice was your path to the .tcl file and mine were different in that none of your directories had a space in the name. I had my projects in a folder named Xilinx Projects. I could cd to it using the old DOS trick of putting quotes around the path. Apparently tcl has problems internally when operating on folders with a space in the name. I admitted I am a newb. I made a new directory without a space, extracted the zip to that folder, opened Vivado 2016.4, cd'ed to the project directory and ran the script with the ./ . Now I have a working project to explore. I can't thank you enough. Yes, I have the ZYBO Z7-20. I will look into those threads.
  9. 1 point
    I figured out the problem. The AXI Ethernet Subsystem is not compatible with the Nexys 4 DDR, since the PHY on that board is not a gigabit PHY, so it requires a RMII interface, while the AXI Ethernet Subsystem can only support RGMII or GMII. I purchased a nexys video board, which has a gigabit PHY that supports RGMII and is therefore compatible with the AXI Ethernet subsystem.
  10. 1 point
    Hi @tadius The 12@2A should be fine. Although if you want to use the adjustable power supplies at maximum (+/-9V@1.5A 27W) you will need a higher rate supply. I think you saw the 15V in the revB schematic. This prototype revision was not released for public. Now I removed the reference to this schematic. https://reference.digilentinc.com/reference/instrumentation/electronics-explorer/start
  11. 1 point
    Hello, I've posted the next part in my FPGA graphics series using the Arty + VGA Pmod or Basys 3. It shows you how to make use of double buffering to animate sprites using simple Verilog. https://timetoexplore.net/blog/arty-fpga-vga-verilog-03 Feedback very welcome, Will PS. I'll add the source to GitHub shortly.
  12. 1 point
    Hi @Flux, Thank you for taking the time to share your project! Thanks, JColvin
  13. 1 point
    good 🙂 One more hint: A simulator and the warnings window / timing reports from Vivado are the key tools. If you start with Verilog (as opposed to VHDL), iverilog plus GTKWave can be extremely useful to debug the logic (cursor-up / return / alt-tab / ctrl-R takes me about 1 second. This is the immediate feedback you were looking for). There's nothing special about it, it's just mean and lean and works. Implementing the design in Vivado up to bitstream is important to keep in touch with reality - HDLs were originally implemented for simulation, not synthesis, and a great deal of online information is just misleading for FPGA, telling things that aren't implementable. You won't get rid of many warnings, but understand every single one. Vivado is trying to tell you something you need to at least understand as a concept. Consider it an automated private lesson. The compiler is your friend. All it takes is a lot (and I mean a lot) of time. Hardware debugging is actually fairly limited - essentially it tells me "simulate some more and re-read the warnings..."