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  1. 1 point
    Hi @Devendra Pundir Can you try removing U82 from your PCB and see if that solves the problem? 30pF is a lot of added capacitance for the USB data lines and is likely what's causing the issue. Thanks, Michael
  2. 1 point
    attila

    Analog Discovery 2 stopped working

    Hi @DanielF The auxiliary supply of the AD2 has under/over-voltage protection. The USB 2.0 port voltage should be around 5V. Higher voltages, above 6.5V could damage the device. Defective HUBs or using unregulated/defective supplies for this could output higher voltages killing the USB devices. In the following posts you can find troubleshooting tips:
  3. 1 point
    It is possible to mux PL pins to ZYNQ PS peripherals. You can, for instance use one PS UART connected to the MIO pins as normal and connect a second PS UART to PL IO pins. For a two pin UART interface this pretty easy to do. For an Ethernet interface not so easy. It sounds to me as if what you want to do is leverage your ZYNQ platform into something that let's you experiment with Verilog designs. You can certainly start with the board design flow to experiment with exchanging data between the PS and PL Verilog code. Simply adding GPIO ports that connect to PMODs would be a place to start. Later you can experiment with using BRAM or you own IP. Personally, I find that having Vivado create a toplevel HDL source that I control works best; but I'm pretty comfortable with HDL design. In my case I create my own HDL toplevel design source and instantiate the board design HDL code. This make connecting HDL code to open ports and pins straight-forward. If you can afford it I strongly urge you to consider buying a cheap non-ARM based FPGA development board to learn Verilog development. It's just a lot less complicated. There are a number of options for nice <$100 FPGA boards, though the best one's for the money might not be Xilinx based. Once you figure out how to implement something in HDL that you can interact with using , say a UART, then try an integrate your HDL into the ZYNQ platform. There is HDL code projects on other areas of the Digilent forums to play with to help get started. A UART is the easiest interface for debugging or connecting an HDL design to PC applications. For <$10 a good 3.3V TTL USB UART breakout module or cable is indespensibe. It is also possible to tie off the PS and just use your board as an FPGA platform; this is not something that I'd recommend. In the end you should choose the best strategy for you. Just don't be afraid to ditch a processor based design because it seems daunting. Before you are ready to implement a 6502 soft processor with peripherals in logic you should be comfortable implementing, simulating, and debugging "peripherals" in the HDL of your choice. At least that's the view from where I sit.
  4. 1 point
    Hello, First, As you may think you have to write your own UART vhdl/verilog module, with an RS323 interface. After you make sure that it works correctly, you have to add to your code and axi lite interface. There are two ways for doing that: 1. You add it by your own, and keep your code as a module. 2. Package your module as an custom ip and use the template given by Xilinx. Personally, I will probably go with the second option. And that is because, the template is clearly written and commented. Inside this template there is a state machine that gives you access to a couple of registers.Trough these registers you can pass data from PL to PS side. After you have your own IP, you can add it into a block design and connect it trough the AXI Interconnect. On this stage your IP will have it's own address into the address editor. With that, you can access trough the lite interface each individual register. Best Regards, Bogdan Vanca
  5. 1 point
    asmi

    ARTY-A7-100 MIG Clock & Reset Requirement

    I wonder if there is a single post by @D@n which doesn't include shameless plugs to his projects...😫 Now, directly to OP's questions: Yes you do. This is why "Clocking wizard" IP is being used (it instantiates MCMM internally). No, reference clock (clk_ref_i) is ALWAYS 200 MHz no matter what.It's fed into IDELAYCTRL blocks which control delay elements used inside MIG. You can select it in MIG wizard, but the choice is limited based on your memory's frequency. For DDR3(L) 333 MHz MIG wizard doesn't allow you to select 100 MHz as allowed input frequency due to the way MCMM is used inside MIG, as well some of its' limitations (only single fractional divider per MCMM). Since you always need to feed 200 MHz into MIG no matter what and there is only single clock source on Arty board, you will have no choice but to use MCMM, so you might as well use it to also generate input system clock. sys_rst signal is an active-low asynchronous reset, you can connect it to board's reset signal (again if polarity is right). It isn't required unless your design is supposed to withstand and properly handle system resets. It's used to bring everything to a known initial state so that memory initialization can be performed and functionality is restored if due to some bugs your HW is not working properly. I never actually tried using it, but I think it won't work out-of-box because of clocks needed to be provided - example design assumes they come directly from IO CC pins. But you can modify it to get it to work, and that shouldn't be that difficult. Same goes for status signals tg_compare_error, init_calib_complete - you can connect them to onboard LEDs provided that polarity is right (might need to inverse depending on how LEDs are wired on a board).
  6. 1 point
    zygot

    Advanced topics

    I certainly won't argue against reading the available literature form Xilinx or Intel; tutorials, reference manuals, etc. A problem with diving into "advanced topics" is that it's hard to wrap your mind around everything by trying to absorb complicated information in a vacuum. It certainly doesn't hurt to be familiar with material on timing closure and constraints. Don't just stick with one vendor. I highly advise that you understand how Intel's or maybe even Actel's timing analysis tools work. Getting into trouble, as it were, is pretty easy. Dealing with it is probably easier with a structured approach. So, one idea for a structured approach is to browse the many Application Notes that are available from the vendors. Often they come with design files demonstrating concepts. This might be an easier way to dip your toes into deeper waters without your eyes glazing over. The reality is that simple designs often don't require much attention to timing and placement constraints but complex high clock rate designs often do. Quite a few application demo delve into advanced concepts. The nice things with this path is that you usually get some sort of analysis and explanation of the theory behind ways of dealing with complexity. One easy path to complication is, as has been pointed out above, understanding pipelining to achieve substantially higher data rates for a given design. This will introduce you to timing closure concepts, latency, valid data scope, and other issues quickly, but with specific issues to resolve. First you need to understand the AC switching specifications for your particular device so as to make the project feasible. For real FPGA design situations what takes place beyond the IO pins is critical; but this is no longer FPGA development but digital design. Ideally, one would start with understanding digital design before trying to do FPGA development; but the is no right or wrong path to enlightenment. If you aren't competent at doing high level simulation and writing useful behavioral and RTL testbenches the you aren't ready for the other advanced topics. Well, for now that's my 2 cent contribution. Bon Voyage!
  7. 1 point
    D@n

    Advanced topics

    For CDC, consider these articles on 1) basic CDCs, 2) formally verifying asynchronous designs, and 3) Asynchronous FIFOs. For speed optimizations, you'll need to learn about pipelining. Here's an article on pipeline control. Dan
  8. 1 point
    xc6lx45

    Advanced topics

    one recommendation, but check out whether it works for you: Keshab K. Parhi "VLSI Digital Signal Processing Systems: Design and Implementation" It's a very old (pre-FPGA) book, but it'll be as relevant in 20 years since the theory does not change. You can find a condensed version in the lecture slides. Pick what appears interesting: https://www.win.tue.nl/~wsinmak/Education/2IN35/Parhi/ ------- Reading through the Xilinx documentation might be a good idea. There are those people who read manuals and those who don't. Usually it's easy to tell the difference... I'd skim quickly over parts that don't seem relevant at the moment (which may be 99 %, definitely too much material to read cover-to-cover) and spend time with those parts that seem interesting or immediately relevant. ------------ For a practical example regarding timing, speed optimization, critical path, you can try this simple project: implement a pseudorandom sequence (e.g. 9 or 24 bits) and compare against a same-size number that is an input to the block (not hardcoded, e.g. set by switches). This is a simple AD-converter and you can test with a LED that it works. Then try to run at as high clock speed as you can manage e.g. 300 or 400 MHz. Understand all the warnings, fix those that are relevant (some are not but you should understand why), especially the ones related to inputs ("switches") and outputs ("LED").
  9. 1 point
    BogdanVanca

    Basys 3 HW Target shutdown (Vivado)

    Hi @giamico, This happens when you lose the connection with the Board. Please try on with a different USB cable.
  10. 1 point
    JColvin

    PMODs - Spec 1.2.0

    Hi @andresb, I apologize for the delay. The best way to determine if they are complaint with specification 1.2.0 is by looking at their respect Resource Center (such as the Pmod AD1). On the right-hand side under Electrical, you will see the Specification version that the Pmod is currently compliant with. The Pmod Interface Specification 1.2.0 is available directly here: https://reference.digilentinc.com/_media/reference/pmod/pmod-interface-specification-1_2_0.pdf. Let me know if you have any questions about this. Thanks, JColvin
  11. 1 point
    tom21091

    iic setup failure

    Its sounds to me like a memory issue as well. It looks to me like you are accessing the correct memory location. This isn't a problem with the cache. I think I've had issues with the Smart Connect IP before. Try recreating the block design without the Smart Connect IP. Try running connection automation and unchecking the object (MIG?) that wants to add a SmartConnect IP. -Tommy
  12. 1 point
    Hi @vinodcxlv You have functions to read data from binary and text file, see the examples and Help tab. The Script tool supports JSON if you want to use it, but it does not apply settings from such data.
  13. 1 point
    Hi @Takashi "The Yaka mein", I apologize for the delay. I am not certain why that particular power supply is not included for the Japan export version of the kit that Xilinx makes. Your guess that it could be a certification issue would make sense, though I do not know this for certain since that particular power supply isn't sold directly on our website as per this forum thread here. I will ask and find out if somebody at Digilent happens to know the reason the power supply would be excluded from the Japan export version, though it may be better to reach out to Xilinx as they are the ones who made that choice for their kit. Thanks, JColvin