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  1. 2 likes
    @Shuvo Sarkar What exactly needs to be done depends on what you mean by "region of interest" and "binary mask". I will assume that you are trying to replace some area of what is being displayed on the screen with a rectangular image. A good starting point would be to take the input stream and output it with modifications. The DemoScaleFrame function in video_demo.c does this. The resolution scaling being done by this function also may or may not be desirable for your project. The Bilinear interpolation function implemented on line 473 of the original source is the primary point of interest here. The three variables required to tell what is being written to in the destination frame are the index, i, which can be used to determine the color channel being written to, and the destination coordinate variables xcoDest and ycoDest. A good starting point to be able to see changes being made would be to add extra code to black out a rectangular area of the screen. This can be accomplished by wrapping the destFrame[iDest] statement within an if statement, that either writes a zero to destFrame[iDest] or runs the bilinear interpolation of the source frame, depending on the coordinates of the target pixel in the destination frame. How you store, access, and process the binary mask (overlay image?) is a large topic that I would need more details to provide information on. Let us know if you have more questions. -Arthur
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    Hi @koenraad In Network Analyzer interface to allow frequency above 10MHz under Wavegen options select Frequency Extended. In Wavegen interface you can generate a custom waveform with 2 periods of sine, so the actual frequency will be double of the one you set. Alternatively you have in private message instruction to enable directly setting higher frequencies.
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    Hi @deppenkaiser, Here is a video that shows using multiple cores with the zybo. I believe it would be the same think for the Arty-Z7. Here is a forum thread that discusses using multiple elfs in different cores. cheers, Jon
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    Thanks. Now that's confirmed I've gone ahead and posted my introductory article on using the VGA Pmod: https://timetoexplore.net/blog/arty-fpga-vga-verilog-01 I hope it'll encourage some other people to give it a go.
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    Also, we're planning on coming out with a pure ts / js version of DIP that doesn't require Angular (though we still recommend using Angular/Ionic for large scale applications). If you're interested, I can send you an update here when we publish it within the next few weeks. -Dharsan
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    Okay I know what the problem is. I'll update the documentation thank you for finding this. I've updated my ionic version to 3.19.0 (the latest version). This is what app.module.ts should say: import { BrowserModule } from '@angular/platform-browser'; import { NgModule, ErrorHandler } from '@angular/core'; import { IonicApp, IonicModule, IonicErrorHandler } from 'ionic-angular'; import { MyApp } from './app.component'; import { HelloIonicPage } from '../pages/hello-ionic/hello-ionic'; import { ItemDetailsPage } from '../pages/item-details/item-details'; import { ListPage } from '../pages/list/list'; import { StatusBar } from '@ionic-native/status-bar'; import { SplashScreen } from '@ionic-native/splash-screen'; import { DeviceManagerService } from 'dip-angular2/services'; import { DigilentChartModule } from 'digilent-chart-angular2/modules'; @NgModule({ declarations: [ MyApp, HelloIonicPage, ItemDetailsPage, ListPage ], imports: [ BrowserModule, IonicModule.forRoot(MyApp), DigilentChartModule ], bootstrap: [IonicApp], entryComponents: [ MyApp, HelloIonicPage, ItemDetailsPage, ListPage ], providers: [ StatusBar, SplashScreen, {provide: ErrorHandler, useClass: IonicErrorHandler}, DeviceManagerService ] }) export class AppModule {} Then you can follow the tutorial as normal. Note that DeviceService is just a type and cannot be instantiated and therefore cannot be added to the providers array. Instead we use it in hello-ionic.ts in order to get typing for an instance of the device in the DeviceManagerService. Let me know if you have any more questions, Dharsan
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    Hi, the most Bank voltages (not all) are variable on TE0720, you can select different Bank voltages on TE0701, with Jumper, see: https://wiki.trenz-electronic.de/display/PD/4+x+5+SoM+Integration+Guide https://wiki.trenz-electronic.de/display/PD/TE0701+TRM You must use the value, which is set on the bank with your PMOD IOs. br John
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    Hi Ronik, create external IO, like jpeyron has described. And add loc constrains and IO Standard on XDC. You can Use Vivado Pinout Planner (after Synthese) or write directly into xdc. To get correct pin assignment, you can use schematics or the Trenz Electronic Pinout Excel Sheet. Here are some links: Download Pinout Excel sheet: https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/Pinout Download TE0720 https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/TE0720 https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/TE0720/REV03/Documents Download TE0701 https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/carrier_boards/TE0701 https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/carrier_boards/TE0701/REV06/Documents Trenz Wiki with all resources links, TRMs and other descriptions: https://wiki.trenz-electronic.de/display/PD/TE0720+Resources https://wiki.trenz-electronic.de/display/PD/TE0701+Resources PS: There are two new 2017.2 Reference Designs with Linux Examples for TE0720 are available: https://wiki.trenz-electronic.de/display/PD/TE0720+Reference+Designs br John
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    Hey, We use the cross-origin request header to allow WaveForms Live to talk to the OpenScope hardware. More general info about the cross origin request header can be found here. -Kristoff
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    @Mell, You'll need the level shifter for both your trigger signal as well as the response from the device. Most FPGA's can't handle a 5V input. Dan
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    Hi @spri It looks like you are configuring only DIO-0 line to output pulse. The other unconfigured DIO lines, by default are in high impedance and you are seeing these floating lines randomly toggling. In case you need you can configure the other DIO lines to output the same signal, like: dwf.FDwfDigitalOut***Set(hdwf, c_int(-1), ...) # -1 enable all lines or configure enabled lines or mask the acquisition to see only the DIO-0 line, like: rgpy[i] = 1 & rgwSamples[i]
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    Hi @flexible111, One thought I had just now is that you might be able to write some helper functions to get you larger sized font created. What I am envisioning is since all of your fonts are 16x16, you could essentially break those up into 4 8x8 quadrants and re-write the CharFont0 existing definitions with your new quadrant pieces. Your helper write function could then use the existing print character function and call it 4 separate times along with 4 calls to move the cursor/pointer to the next upper left corner as appropriate for the next section of the quadrant. I haven't done this before, but I think that might be the easiest way to approach this without entirely re-writing the functions. The potential catch here is that the the CharFont0 file doesn't have enough space for all of the possible characters when they are now taking up 4 8x8 pixel areas rather than just one. If you already know what you are printing, you may be able to "erase" the characters you don't plan on printing, or you may be able to just add more lines to the CharFont0 file. I haven't done anything like that before, so I do not know if there any caveats with this. Good luck. Thanks, JColvin
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    Hi @junaidahmad_k@yahoo.com, Here is the MicroBlaze Processor Reference Guide that should have the clock cycle information you are looking for. Here is a forum thread that discusses clock cycles for Microblaze on the Arty board. I believe it also depends on how you set the processor up I.E. Performance Optimized MicroBlaze with Branch Optimizations or Frequency Optimized MicroBlaze with Branch Optimization as described here. cheers, Jon
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    AK72, Did you get your answer on this? I can probably help there if it's still needed. Meanwhile, to the others on this thread, I apologize for piling on an aging forum thread, but I too have had issues with interrupts and using the UIO driver. I have been using the UIO driver to provide various interrupts (from the PL of the Zynq) to the PS. I have a handful of threads that are invoked from my application. For whatever reason, I slip/miss interrupts on occasion (several in a row for that matter). I lack the in-depth understanding of the linux kernel and the UIO driver. Both would probably make troubleshooting a little easier. Still, I blame either the UIO driver or how I am using the driver to poll for interrupts. Is anyone else using multiple interrupts with the UIO driver? Is anyone else having problems missing interrupts? If anyone reading this can help, let me know. I would be more than happy to provide additional information about what I am doing and the problem(s) I am experiencing.
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    Hi @ronik, We do not have board files for non Digilent fpga's. This will change the process to connect the pmod ip. You will still need to add the vivado library to the ip repository. Then you will add the desired ip from the add ip button in the block design. Once the ip is added to the design you will need to right click on the pmod out click "make external". After you are done with building the block design and have created a wrapper you will need to constrain the pins for the pmod in the wrapper using an xdc file. thank you, Jon
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    Hi @Jay Sngh, I have received the Declaration of Conformity's for the Basys 3, the Pmod USBUART, and the Pmod RS232. The other two Pmods (the Pmod LVLSHFT and the Pmod SSR) are exempted based on "subassembly exemption". All of our boards are designed with UL-94V0 rated PCB material and are RoHS Complaint. Let us know if you have any questions. Thank you, JColvin
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    Hi @amkichu, I am glad you were able to get it going. Here and here are forums that talks about using the Ethernet with the Anvyl. I would suggest looking at examples like here. cheers, Jon
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    Hi @gwideman, I am sorry for the inconvenience. We are in the process of updating our tutorial for Vivado installation. The newer versions of Vivado do not require a license for the webpack edition. You can also use the Design edition without a license as long as you are not targeting an fpga that requires the design edition to work with it. thank you, Jon
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    @elodg Thanks for your reply! I tried with Antivirus (Avira) turning off and other networks (Wi-Fi) and doing the same by generating new bsp and project. Fortunately, it is successful and I could open it up with telnet also. I repeat the whole with turning on the antivirus and Wi-Fi, but it gives the below result. Thanks for your support. I guess that the regenerating of bsp and project made it right. Thanks again. If I am not wrong I think I need to modify echo.c for adapting the code for my own applications.
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    Indeed, the project included in the workspace does not work. But if you create a new "lwip echo server" example project in SDK along with a new BSP, that works. Make sure any software firewall is off or allows ping packets.
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    To add to my comments on possible performance problems: Running this masking algorithm in the Zynq PS will likely be inherently slower than running it in the PL. Adding a stage to the output pipeline in hardware is likely going to be a better approach, with the caveat that it would be a significant amount more work. This stage would likely need to be created as a custom IP core that either: 1. Takes in an AXI stream and outputs an AXI stream, probably placed near the AXI stream converter IP in the pipeline (if I am remembering things correctly, I don't have access to Vivado at the moment). There may be a xilinx provided IP that does something like this, but I am unsure. 2. Takes in VGA signals and outputs VGA signals, placed directly before the output port. This approach would require more work in detecting the pixel position and resolution of the data stream, but would avoid the complexity of AXI. For the time being though, it is still worth trying to make the algorithm work in the PS, this is just a hypothetical for if the performance of the PS design is unacceptable. Thanks, Arthur
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    @Shuvo Sarkar Are you selecting the output frame using the serial interface to the demo? I assume that what is currently being displayed on stream is a single captured frame with the masking applied? If this is the case, it is likely possible to modify the demo further so that it runs the "copy, scale, and mask" algorithm repeatedly. By this I basically just mean placing the modified DemoScaleFrame function inside of a while loop. Caveat: I not certain what the performance cost of doing this would look like, so it may be worth looking into how quickly the algorithm runs (perhaps a little outside of the scope of the current discussion). Thanks, Arthur
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    Hi @flexible111, Changing the font size will be far more difficult. Currently the OLEDrgb libraries are using a pre-generated file that defines the 8x8 pixel area for each printable character and the functions printing individual characters all all based off working with that size. With that in mind, there are four options to change the font size available: - Change the pixel pattern file that the Pmod OLEDrgb uses (called CharFont0.h) - Create the custom characters that you need and individually print those custom characters - Individually draw them pixel by pixel - recreate the functions to print each character with a large pixel area Unfortunately, Digilent won't be able be to offer much help in this particular customized endeavor though. Let us know if you have any more questions. Thanks, JColvin
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    Hi @flexible111, I am glad that you were able to get it working. You would have to alter the chrfont0.h here as well as the drivers themselves and how they index the struct in chrfont0. Changing the preset font size would not be an easy task. thank you, Jon
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    Hi @Jay Sngh, There is no license provided with the Basys 3 board. We would suggest using Vivado's design edition which can be downloaded and used on a non-design edition target such as the Basys 3 without a license. If you are concerned with Vivado's size and are not going to use a virtex or kintex fpga you can also uncheck these boxes in the initial download options. cheers, Jon
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    What are you talking about? I opened 10.Anvyl_Ethernet_Demo in XPS 14.7, and upgraded the project to the latest version along with IPs. There are no IPs missing, but there is an error message upon bitstream generation that is answered here: https://www.xilinx.com/support/answers/62380.html Just double-click on axi_ethernetlite_0 and uncheck Include PHY I/O constraints, as described in the AR. Then, the bitstream gets generated successfully. Exporting to SDK works, but BSP needs to be regenerated to upgrade to the latest library version. Then the application compiles as well. I don't have a board at hand, but you can try it yourself using the upgraded project I attached. 10.Anvyl_Ethernet_Demo.zip
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    Hi @MicahK555 Unfortunately the seen ~30mV pk2pk noise on AWG output of EExplorer board is a fact. For such low amplitudes use resistive divider, like output 3V signal divider with 1k/10 Ohm to 30mV. You might also want to increase the current limitation on the power supplies, with the specified 10mA these are in limitation.
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    Last night I measured the speed of RF waves in a generic 10m TV coax using the AD2, a socket and two resistors Why?: I'm trying to build a cheap colinear antenna for receiving 1090MHz plane broadcasts. To do this I need to know the "velocity factor" of a cable. The setup: Connect the AD2 wave output and the input of the first scope channel (the reference channel) to one end of a 330 ohm resistor, Connect the other end of the 330 Ohm resistor, the second scope channel, and one end of the 100 Ohm resistor to the center pin on the socket. Connect the other end of the 100 Ohm resistor plus the AD2's ground connection to the shell/ground connection of the socket. Running the test: Without the cable plugged into the connector, run the Network Analyzer, from 1 MHz to 10 Mhz - it should be a pretty much flat line. Then connect the cable and test again. There will be a 'dip' somewhere 5 or 6 MHz. What is going on: The 330Ohm+100Ohm resistor acts as a signal divider, and has an AC impedance of about 75 ohm, matching that of the Coax cable. Because the cable has an open end, it is acting as an 'open stub' and any signal that is injected into the cable reaches the end of the cable and is reflected. The source and reflected signal interfere with each other, and where the signal is destructively interferes with the source signal the "dip" is seen. The bottom of this dip is when the cable is 1/4th the wavelength of the RF signal - so if the driving signal is at 90 degrees, the reflection is at 270 degrees, making the measured signal much weaker. Results: For a 10m (30 ft?) cable the dip was at 5.634MHz. That makes a full wavelength 40m long. That gives a speed of propagation of 5.634MHz * 40m = 225,360,000 m/second - about 75% the speed of light in a vacuum.
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    Hi @smarano, I reached out to our design engineer and found that access to the VBAT pin on the Cmod A7 is impossible. There’s no way to attach a coin cell to just the VBAT pin because it’s hard tied to the VCC1V8 rail and the trace that connects the FPGA ball to the via that goes straight to the VCC1V8 polygon is underneath the FPGA. Therefore a cut and jump is not possible. We didn’t have space for an auxiliary JTAG connector on the CmodA7, which means that the JTAG signals aren’t routed out to a header. That will make attaching an external program very difficult, if not impossible. thank you, Jon
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    Hi @amkichu, The only thing I have been able to find is Here is the Anvyl Demo Project Suite. I have reached out to my co-works to see if we have an OOB demo that contains all peripheral interfacing. thank you, Jon
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    Could you try using Tera Term instead? I am unfortunately not super familiar with the SDK console, and have had trouble using it in the past.
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    Using posedge on fabric logic can have a few issues. If the fabric-generated clock doesn't come directly from a register -- eg if you have c = ( a == b ) -- then you can generate glitches. It might be that as new values of a,b are being propagated to the logic the condition is met one or more times within a normal cycle. This can generate short pulses which might trigger some registers but not others. This is also true for async set/reset logic. When a fabric generated clock comes from a register or doesn't have glitches, the clock might be ok to use. There are still some issues. First, this design style is more prone to generating a larger number of clocks, which might exaust the clock routing for a given clock region. Second, the clock might will have routing delays that change from build to build as well as over temperature. This means the clock must be treated as asynchronous to other clocks in the design. These are not insurmountable issues -- you can create directed routing constraints (DiRt) to ensure the same routing is used each build. You can ensure safe clock-domain-crossing logic. However, this requires extra effort in design/sim/constraints. This is another issue -- that the fabric clocks appear easier to use. Add to this that they often work fine and they teach novice bad practices. The fabric generated clocks also can have additional jitter, duty-cycle distortion, etc... This generally isn't an issue as these clocks tend to be run at Fmax/10 or lower. For the original post, the synthesis tool generally is allowed to optimize the circuit. It is possible the tools will decide to share adder logic or other logic when it can detect mutual exclusion. The tools might opt to place the majority of the ALU into a DSP48 slice for example.
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    @gcp Yes. BRAM is located within the FPGA fabric (PL), rather than on the PS. Further, most FPGA's have BRAM's within them as well, Dan
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    Hi @Matt Ownby In the Logic Analyzer you can use Bus interpreters with Enable and Clock signal for address/data decoding, and additional lines to visualize further control signals.
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    Hi @techno-rogue I might be wrong but it appears from the picture that the Pmod output is directly connected to 50 Ohms coax cable. The scope is showing about 2V amplitude which is inconsistent with the description of the experiment but consistent with the driving 50 Ohms directly from logic. Note that Zybo traces probably designed to have 60 Ohms impedance. Tail waves on the waveforms indicate impedance mismatch between 50 Ohms load and driving impedance. If I would do such experiment I would interface Pmod using high speed line buffer and measure timing on its output. This is how design should be done and this way we would get realistic measurements. Overall I think this is a good learning experience of electronic design theory in practice. Good luck!
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    @Flux, I have 1080p60 working on my desktop using the Nexys Video, both transmit and receive. The limitation I'm running into so far isn't a video rate bottleneck, but rather a memory bandwidth bottleneck. Dan
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    @techno-rogue I would suggest 1) check your scope measurements capability here 2) try to add a clock buffer at the Pmod output. Xilinx recommends to us such buffers for clocks. In VHDL it is component BUFG port ( I : in STD_LOGIC; O : out STD_LOGIC); end component;
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    For anyone else who is interested, I've got Arty's Ethernet port working in PetaLinux and I've documented the process here: http://www.fpgadeveloper.com/2017/11/petalinux-for-artix-7-arty-base-project.html I've also provided a link to the boot files at the end of the article so that you can try it out yourself. Jeff
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    Dear @techno-rogue It is not clear what is your goal. Do you want to use Zybo as a signal source for some 50 Ohm load or it will interface some kind of digital logic? If the goal is the first one then your experiment can be representitive. However you need to account for the capacitance of the 50 Ohm cable and the bandwidth of the scope you are using. Typically measurements of ns pulse are done using special scope hih impedance probes with very small input capacitance. If your load is some digital logic then the experiment is not representitive because most of 3.3V logic is CMOS and its input is pure capacitance with some loss component. In my experience I was able to drive 40 MHz clock to my custom logic out of Zybo Pmod. I didn't try higher since it was no need. Higher rates can be achived using LVDS but Zybo is not equipped for this. Hope you find it useful.
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    Hi @nattaponj, Here is an article that explains Weighted method for converting RBG to grayscale. Are you asking about why we chose those specific weights or just about the algorithm in general? cheers, Jon
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    Hi @nattaponj, It is a compiler directive. The compiler will take it into account in order to optimize your code. You can "optimize your system and hardware functions using a set of directives and tools within the SDSoC environment." "You can insert pragmas into application source code to control the system mapping and generation flows, providing directives to the system compiler for implementing the accelerators and data motion networks. "(SDSoC User Guide, UG1027). In SDSoC you can use two types of compiler directives: SDSoC directives and HLS directives. Some examples of SDSoC directives: #pragma SDS data data_mover(A:AXIDMA_SIMPLE) -> specify which data mover you want to use to transfer data: FIFO, DMA simple, SG_DMA, etc. #pragma SDS data sys_port(arg:port) -> specify the memory port #pragma SDS data zero_copy -> copy arguments in the called function. Because SDSoC uses HLS(UG902) to compile synthesizeable C/C++ functions into programmable logic you can use HLS directives too. For example #pragma HLS PIPELINE II = 1 "The initiation interval (II) is the number of clock cycles before the function can accept new inputs and is generally the most critical performance metric in any system. In an ideal hardware function, the hardware processes data at the rate of one sample per clock cycle. If the largest data set passed into the hardware is size N (e.g., my_array[N]), the most optimal II is N + 1. This means the hardware function processes N data samples in N clock cycles and can accept new data one clock cycle after all N samples are processed. It is possible to create a hardware function with an II < N, however, this requires greater resources in the PL with typically little benefit. The hardware function will often be ideal as it consumes and produces data at a rate faster than the rest of the system. " Using this directive you specify to HLS compiler to use the pipeline technique in order to obtain an initiation interval = 1. When the HDL is generated it will try to obtain II = 1. If it is not possible it will warning you. All directives are used to optimize the program. You can read more about this in UG1235. Now, in your example you have #pragma AP PIPELINE II = 1 The Sobel filter example from Zybo SDSoC platform was developed by Xilinx in 2011 ( (c) Copyright 2011 Xilinx Inc. ). In that period, HLS used another compiler named APCC which was used to overcome some limitations of standard C compilers. You can read more about this in UG902 HLS 2012.3. I think that APCC is not used anymore. Because the git project was created in Vivado 2015.4, I think it should work. It depends on what Vivado version do you use. If you have building errors you can try to replace #pragma AP PIPELINE II = 1 with #pragma HLS PIPELINE II = 1 and #include "ap_video.h" with #include "hls_video.h" Best regards, Bogdan Deac
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    Hello everyone! we are in process of writing the update, but our workbook has come back from the designer and it's getting prepared for printing! Digilent-OpenScope_Learning_Edition_Workbook.pdf
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    Hi @Allan You need to install Zybo files into Vivado, Here, ( this is for Vivado 2015 and later)... also I made simple project for making blinking LEDs, using Verilog language, but not using IP block.
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    @Allan Your problem could be resolved very quickly if you care to provide details about what have you tried. I suggest go through "Hello World" project and make sure that USB uart is working.
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    Hi @Allan, I'm not certain if you are using the original Zybo or the Zybo Z7-10, but I would recommend following our Getting Started with Vivado IP Integrator which goes through controlling on board LEDs and switches as well as using the UART on a Zynq system. Let us know if you have any questions. Thank you, JColvin
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    Hi @yassin, This can be helpfull for you Petalinux quick guide See you!
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    The interface that your custom IP core will need to implement to connect to the VDMA core is called AXI Stream. This interface is a pretty simple uni-directional FIFO style interface. In your case, your IP core will need to implement one slave AXI stream interface (for the input video stream from memory) and one master AXI stream interface (for the output video to memory). The first place you should go to learn how to implement a custom video IP core is Xilinx's AXI4-Stream Video IP and System Design. That doc will outline a lot of the different things you will need to consider about your design. You may also need to refer to the VDMA IP documentation here. If you need additional information on the AXI stream interface, check out the AXI Reference Guide from Xilinx. Specifically page 94 will have information on the Video "flavor" of AXI stream. To get started, I would recommend that you use the create custom IP wizard in Vivado and check the boxes indicating that you will have an AXI stream master and slave. This will provide you with a good starting template and some control logic for the AXI stream handshaking signals. You can also look at the source for Xilinx's AXI-Stream to Video Out and Video In to AXI-stream IP cores as examples. The source code for those cores should be included with Vivado.
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    That error isn't caused by a version mis-match... but you may run into some problems down the road. You might want to switch to petalinux 2015.4. We have a plan to update the ZYBO petalinux project to 2016.2, but no timeframe yet. I wouldn't recommend waiting for it. Back to the error you are getting, it is probably caused by the fact that your design doesn't have an axi_dynclk core in it, and therefore the system-top.dts file included with the project is trying to modify a device tree node that isn't being created by the tools. I recommend starting with the linux_bd project found in the ZYBO repository on our github, and then making your desired modifications to that project and importing that .hdf. That will ensure that several key aspects of the hardware design we used to generate the ZYBO petalinux project are present in your block diagram. For example, that project also routes an I2C controller over EMIO to the onboard EEPROM so that u-boot can read the globally unique MAC address from it and automatically configure the Ethernet controller to use it. If your design doesn't also route the I2C controller in this fashion, u-boot might fail (as it is configured in our petalinux project), or at the very least, you won't have a globally unique MAC address when you boot into Linux. Edit: If you want to stick with your project as is and try to get it working, then you will just need to tackle these problems as they come up, and we can help with that. To solve this problem, just open up system-top.dts and remove the node that references axi_dynclk_0 and all other nodes that refer to video output (one will be called xilinx_drm). Note your system will not include HDMI output capabilities.