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Showing content with the highest reputation since 02/23/19 in all areas

  1. 2 points
    Hi, there's a lot of new information in your last post. You aren't just "trying" FPGA but have a professional interest in Zynq. Don't let anybody scare you it's "difficult" and go for it, possibly with the cheapest board, no tutorials and low expectations like, blinking LEDs for quite a while. Given the price tag of any industrial training coarse, an FPGA board for self-study is a no-brainer. Maybe save some money to buy your FPGA engineer a coffee once a week, with some questions in mind
  2. 2 points
    True. Zygot believes that making you work for knowledge is kinder than giving you solutions that can be used to mindlessly resolve your problem of the hour.... it's just a different philosophical bent...
  3. 2 points

    Pmod DA3 clocking

    It looks to me like DA3_WriteSpi() was adapted from code for a different device and has vestigial and incorrect code. Reviewing the AD5541A datasheet, several things stand out There is only a single register in the chip so there is no need for the u8 reg parameter. There is no need for a"config byte" to be sent before the data. The transfer is always 16 bits so there is no need to allow for arbitrary length data quoting from the datasheet "Input data is framed by the chip select input, CS. After a high-to-low transition on CS, data is shifted synchronously and latched into the serial input register on the rising edge of the serial clock, SCLK. After 16 data bits have been loaded into the serial input register, a low-to-high transition on CS transfers the contents of the shift register to the DAC register if LDAC is held low". Reviewing the PmodDA3 schematic, the ~LDAC signal is softly pulled to ground with a 10K resistor. So there is no need to explicitly toggle ~LDAC. What all this means is DA3_WriteSpi could be simplified to something like void DA3_WriteSpi(PmodDA3 *InstancePtr, u16 wData) { u8 bytearray[2]; bytearray[0] = ((wData & 0xFF00) >> 8); bytearray[1] = (wData & 0xFF); XSpi_Transfer(&InstancePtr->DA3Spi, bytearray, 0, sizeof(bytearray)); } You would then call it passing in just the instance pointer and the value you want to write to the DAC. u16 dacValue = 1234; DA3_WriteSpi(&myDevice, dacValue); I do not have a PmodDA3 on my bench so I cannot verify the function works, You can give it a try and let us know how it goes.
  4. 2 points

    Pin Mapping for JTAG-SMT3-NC

    Hi @RussGlover, I apologize for the delay; the details you are looking are as follows: TCK - ADBUS0 TDI - ADBUS1 TDO - ADBUS2 TMS - ADBUS3 OEJTAG - ADBUS7 OESRSTN - ACBUS4 Let me know if you have any more questions. Thanks, JColvin
  5. 2 points

    Pmod DA3 clocking

    It seems to me the AXI Quad SPI block is sending address + data. Looking at the .xci file again, I see C_SPI_MEM_ADDR_BITS set to 24 bits. So 24 bits of address and 16 bits of data would yield 40 bits.
  6. 2 points

    Pmod DA3 Pinout

    That is one of the conventions commonly used to indicate an Active Low signal. So in this case, you pull Chip Select low when you want to access the chip. After you have toggled in all the data bits on the DIN line, you pull LDAC low. The Pmod DA3 reference manual has a link to the D/A chip's datasheet. That is the best first place to look for information on the device's function. The required signal timings are on page 5 of the datasheet.
  7. 2 points
    @Ahmed Alfadhel If you installed Vivado then you also installed the Xilinx Document Navigator. If you are serious about developing with FPGA devices you need to know how to find and access the plethora of documents that your vendor provides in order to use their devices properly. Check the box for 7 Series devices to see the list of reference manuals, User's Guides, Datasheets etc. From there you can add all relevant documents to your search and keep up to date. Do the same for ISE or Vivado tools. This is where everyone needs to start their Xilinx FPGA journey. Xilinx makes it easier than other FPGA vendors to obtain knowledge.
  8. 2 points
    The hot plug detect should be on the rx side. The source will see that and will then initiate the DDC conversation.
  9. 1 point

    Pmod DA3 clocking

    I included visualizations of the ~CS, SCLK and DIN lines in the logic analyzer trace I posted Tuesday at 2:51 AM. In the trace, MOSI is the DIN line, Enable is the ~CS line and Clock is the SCLK line. Did the Xilinx SDK report any errors while opening the workspace? Did you program the fpga from the SDK?
  10. 1 point

    FMC Breakout

    Thanks for all your help guys. I chose the XM105.
  11. 1 point

    CMOD a7-35t Schematic

    Hi @mzin92, There is no difference in the schematic on page 4 or 7 between the Cmod A7 15T anf the Cmod A7 35T. We do not publicly provide the BOM. What information are you looking for specifically? best regards, Jon
  12. 1 point

    PMODDA2 on ZedBoard

    Ah thats right, I had to correct that as well. Just change the instance name of the up/down counter to counter. Sorry I forgot about that. up_down_counter counter ( .clk(clk_div), .counter(counter1) );
  13. 1 point

    Pmod DA3 clocking

    I obtained a DA3 and was able to get it working. Here are some pictures of my setup. I am limited by how big the attachments are so I will post again with an archive of the project I used.
  14. 1 point
    Hi @John Evans, I'm personally not able to find the actual part number individually, but there are some details about the microUSB connector on this thread here: Is the connector broken off entirely, or are there some instances where the cable was plugged in upside down so that the tab inside of the connector was simply bent downward slightly? If the latter is the case, you can push the tab back up with a small flathead screwdriver or something similarly sized. Thank you, JColvin
  15. 1 point

    PMODDA2 on ZedBoard

    Hi @mehmetdemirtas89, Another option is to use the add a module function by right clicking on an empty space in the Vivado block design. The Add a module function connects VHDL/Verilog modules to the AXI bus as discussed in this and this forum thread. thank you, Jon
  16. 1 point
    Hi @ezadobrischi, Welcome to the Digilent Forums. Please be more specific on the Photo Diode output. Based on basic Photo Diode output I would: 1) Convert the photo diode receiver current output to voltage and use an ADC to read the voltage signal. 2) The Nexys 4 DDR has and on-board XADC (xilinx analog to digital converter) 7 Series FPGAs and Zynq-7000 SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide. Here is our XADC demo for the Nexys 4 DDR done in Verilog. 3) The voltage input range is 0v to 1v in unipolar mode and -.5v to .5v for bipolar mode for the on-board XADC. 4) If the voltage is not within the 0v -1v then I would either use a level shifter circuit to bring the analog signal into the 0-1v range or use something like the Pmod LVLSHFT. 5) If the voltage is in the 3.3v - 5v range and do not want to use use a level shifter you can use other ADC's like the Pmod AD1. Once you have the signal in the Nexys 4 DDR you can filter the signal. cheers, Jon
  17. 1 point

    PMODDA2 on ZedBoard

    Hello @mehmetdemirtas89, Yes, you can use the PmodDA2 with the zedboard. Note that there is no IP core in Digilent's vivado_library for the DA2. However, on the reference page for the DA2, you can find usage information. You can download the verilog example and the reference component. You will need to retarget the example project to use the zedboard instead of an Artix based board. You will also have to supply a constraints file for the project. Here is the physical setup I tested. (My zedboad's jtag usb connector broke off a while back so I have to use the Xilinx platform cable to program) Here is what the logic analyzer shows while it is running And zoomed so you can see the writes
  18. 1 point
    Hi @hello.parth, I have PM'd you about the proprietary FTDI programming circuit. thank you, Jon
  19. 1 point

    Question about adding Pmod

    Hi Joe, Thank you so much for you help! It works! So I can now continue my final project. Mingfei
  20. 1 point
    Hi @jpswensen, Welcome to the Digilent Forums! I was able to get the example project on the chipKIT Motor Shield Resource Center working. I am using the Arduino IDE version 1.8.1 and the Digilent Core here. In the UC32 reference manual here on page 3 it states "17. J11 – I 2C Dedicated I2C signals. These pins are independent of the settings of jumpers JP6 and JP8. However, if JP6 and JP8 are in the RG3 and RG2 position, the I2C signals will be tied to pins A4 and A5 on J7" JP6 and JP8 need to be jumpered to RG3 and RG2. This ties the I2C signals to pins A4 and A5 on J7. These pins are used in the example demo. cheers, Jon
  21. 1 point
    It seems that something went wrong when preparing first partition with BOOT.BIN and image.ub files. First method : A minimal test that we can do is to prepare only one FAT32 partition and copy BOOT.BIN and image.ub files. Then start the board with this setup. This way it should only start the Linux kernel, however no rootfs. The UART should be initialize. and the green LED should be on. Step 1: format SD card as FAT32 file system Step 2: copy BOOT.BIN and image.ub files to the SD card (then safety remove the SD card) Step 3: insert SD card in zybo-z7-20 and power the board Step 4: The green LED turns on then it means that the UART(via FTDI) is ready. Note: Alternative: The second file attached was z7-20.img.zip which is a snapshot off a 2GB SD card containing both partitions. The image can be written to the micro SD card with `dd` tool on Linux or a similar tool for Windows (writing this image to SD card from windows 10 worked for me using Win32DiskImager). Step 1: extract the z7-20.img.zip Step 1.A : insert micro SD card if not already inserted. Step 2: run Win32DiskImager Step 3: For `Image File` field set the path to z7-20.img file. z7-20.img sha1sum: e08516edb24ff65d32ce7a43a946f0be9b9f0ebe (If you want to check) Step 4: In `Device` field make sure the Drive letter for microSD is selected (If not you risk loosing data from other devices). Step 5: Pres write.(If you are prompted to format partitions please do not. The second partition filesystem is ext4 which is not recognized by the OS) Step 6: After the process ended, safety remove the micro SD. Step 7: Plug the micro SD into the z7-20 board. Power up the board.
  22. 1 point
    You might have a look at Trenz Electronics "Zynqberry". I think they managed to get one of the cameras to work (not sure). What I do remember is that the board has some custom resistor circuitry to additional pins for the required low-speed signaling.
  23. 1 point

    FFT / iFFT / RS - Basys3

    @gummadi Teja, What you are asking for is not the common approach to building FFTs, therefore let me take this moment to invite you to build an FFT that uses the CORDIC algorithm without any multiplies. Let me also share with you what I think you will discover. While CORDIC algorithms do not use multiplies, they aren't necessarily logic efficient by any stretch of the imagination. Worse, CORDICs apply a gain to the incoming signal. Before you think this gain might be easily factored out since it applies to all incoming samples, let me remind you that there are two paths through each butterfly--one that would get the gain and one that would not. That brings you back to needing a multiply again. The FFT algorithm I linked to above does have an option that doesn't require hard multiplies (DSPs). Be aware, though, if you use this option the generator will build your multiplies from shifts and adds and this will cost you a lot of logic resources. Yes, I am aware of an alternative multiplication algorithm that I've come across that is very light on logic resources, but it also requires a delay equal to the number of bits in the multiply. That would slow the FFT processing down to (roughly) one sample every 54 clocks or so. Yes, the algorithm is similar to a shift-add multiplication algorithm, although about 2x less the area. While I've thought of integrating this into my own FFT design, no one has been paying for this upgrade so ... it may take a long while before I get to it. All that said, there's a saying in English that "Beggar's can't be choosers." If you really want a specific type of FFT implementation, you might be stuck with needing to build it yourself. Perhaps if you share more about why you are so interested in such an algorithm, and what engineering problem you are trying to solve, it might be easier to actually recommend a solution to your design problem. So far, you've been asking for an implementation, when I think what you need is a solution. The two are very different. Dan
  24. 1 point
    Thank you all for replying! @elodg Thanks for the tip! I was indeed using the vivado library IP core. From opencores I presume you meant this controller? https://opencores.org/projects/sdcard_mass_storage_controller If so, it does look promising, since it will basically be a direct hardware link to the SD card (if I am reading this correctly), currently it's running on the microBlaze and going through SPI. I just hope that the PmodSD supports the opencores controller. I registered there and hope to download and test the code soon! It appears to be written in verilog, hopefully that wont clash with my vhdl code. @MirceaDabacan Thanks for the explanation! I will search for some low power speakers to use with the AMP2 that I have right now since I couldn't find the max vpp specs of my JBL charge 2+. Your suggestion for the I2S2 is also a very interesting solution and if I do want to hook up a separate amplifier then I will definitely look into that module! @D@n Thanks for the suggestion! Creating a high speed buffer, with a much larger capacity than the RAM that is available on my basys 3 is very interesting! Considering that the data files are about 13 MB worth of samples per track, I could easily load the music from the SD card minute by minute, giving me ample time to continuously buffer during playback. Thanks for the support! Much appreciated! I will post back with my new findings! Jonathan
  25. 1 point
    Hi Jonathan, PmodAmp2 is a class D audio amplifier. Supplied with 3.3V (in conjunction with Basys 3), it generates an output voltage up to 6.6Vpp. The output signal will consist in only 3 levels: -3.3V, 0V, +3.3V. The load circuitry should filter the pulse modulated signal to an audio analog signal. The high input impedance of the speaker amplifier will not allow a high current. The voltage amplitude can eventually damage the speaker amplifier. Please check if this withstands a voltage of +/-3.3V (6.6Vpp). Reducing the “volume” of the digital signal would not help: the amplitude of the pulses will not decrease, just the duty factor… The next question is: how will you generate the signal to drive the Pmod Amp2. I see two possible options: Using an AD convertor Pmod (ex. Pmod DA2). The PmodAmp2 would be cascaded into Pmod DA2. Using a PWM modulator. In both cases, you can adjust the volume by multiplying the digital sample values with a “volume” constant.
  26. 1 point

    Pmod DA3 clocking

    Hi @Ahmed Alfadhel, In section 2 Interfacing with the Pmod on page 1 of the reference manual for the Pmod DA3 here it states the pmod should use spi mode 0. thank you, Jon
  27. 1 point
    Vivado is pretty picky about having the correct folder structure. On my Centos system, the path to the Arty board files and the contents of the folder looks like the following. I have also observed the boards not being offered if the appropriate device family has not been installed. In the Help menu you can launch the "Add Design Tools or Devices" command. At the first dialog, press next to accept the current installation (eg Vivado HL Webpack). The next dialog allows you to select device families. Make sure the 7 Series and Artix-7 family is selected Also note that the Digilent supported version of Vivado is 2018.2 and not 2018.3.
  28. 1 point


    Hi @AndreaD, There is a VISO; you can see it on the Pmod RS485 schematic as well as how it is generated from Vcc in Figure 1 in the Pmod RS485 reference manual. Let me know if you have any questions. Thanks, JColvin
  29. 1 point
    Hi @Brain, On page 4 of the Zybo schematic here it shows the mic_in line is tied directly to the audio codec. The XADC would not be able to access the input from the mic_in line. The XADC can access input from Pmod Port JA as shown on page 10 of the schematic and discussed in section 6.3 Dual Analog/Digital Pmod (XADC Pmod) of the Zybo reference manual. Here is a completed Zybo DMA audio demo made for Vivado 2016.4 that uses the audio codec. Here is a forum thread that discusses using the audio codec on the Zybo. thank you, Jon
  30. 1 point
    Hi @fonak The CC/CV mode was added to WF beta 3.10.3 https://forum.digilentinc.com/topic/8908-waveforms-beta-download/ You can find the schematic of IA Adapter here: https://reference.digilentinc.com/reference/add-ons/impedance-analyzer/start Currently you can make lock-in amplifier like this: Impedance 1. Thanks for reminding. I wanted to add offset compensation for DC, just got distracted with other projects. 2. At the moment you can use a script for history like this: Impedance.run() // use averaging to control the sample rate Impedance.Frequency.Averaging.value = 0.2 plot1.X.AutoScale.checked = false var rg = [] while(true){ if(!Impedance.wait()) break rg.push(Impedance.Traces.Trace.getData("Impedance")[0]) if(rg.length>50) rg = rg.slice(1) // max length plot1.Y1.data = rg plot1.X.Range.value = rg.length plot1.X.Offset.value = -rg.length/2 } Power 1. With AD2 6th device configuration you can use the power supplies as AWG With EExplorer board you can use voltage or current AWG. 2, 3 Ok 4. You can use F5/F6 to start/stop an instrument. 5. The AD/AD2 has no voltage or current readback. On the EExplorer board you can adjust the voltage/current limit and also have voltage/current readback. Protocol Logic 1. You can use script, similar to the previous IA In the Logic analyzer increasing the row height you get analog representation for the bus, interpreted values 2. You have I2C scanner in Protocol/I2C/Custom/examples Other 1. You can export and import data into Scope, Spectrum, Logic Analyzer... 2. Ok. Thank you for your suggestions.
  31. 1 point
    The answer to your question is in two documents: the schematic for your FPGA board and the IO User's Guide. For Series 7 devices this is UG471. Anyone wanting to make their own interfaces must understand the rules [ there are a lot of rules so read the whole manual]. All IO pins are connected to an IO bank. Every IO Bank can be powered with a different Vcco to suit the IOSTANDARD being used. There are rules for mixing IOSTANDARD assignments for any bank. Be aware that some boards, like the Genesys2, have HR and HP banks which further complicate the rules for using IO. As I've pointed out before, many times in fact, the differential "high speed" PMODs are almost useless since all of them are connected to IO Banks powered by Vcco = 3.3V. There are no 3.3V differential IOSTANDARDs supported by Series 7 devices. Spartan 6 and Spartan 3 do support LVDS_33 or LVDS_25 depending on what the Vcco is . For Digilent boards with FMC connectors they use Vadj which allows the user to select from an a wider range of IOSTANDARD to use LVDS directly. None of the Digilent boards with PMODs, that I know of, use Vadj or user selectable Vcco for PMOD IO banks. For LVDS a further complication is that a parallel termination is required and that termination should be as close to the receiving end as possible. HR LVDS supports internal termination. Does this mean that your are completely stuck if your board doesn't directly support the logic that you want to use? No necessarily, but you will have to spend some money getting it right. Xilinx has application notes to help with that. Last thought on the subject. Just getting the IO Vcco and logic right may not be enough to implement an interface. There are rules for clocking that may impact your design. There's a user Guide for clocking. For anyone interested in doing differential interfaces and not able to make their own FMC mezzanine board, Opal Kelly has 2 boards that support the Syzygy specification. They've clearly read the documents and did their homework and have implemented a truly usable POD interface.
  32. 1 point
    Hi @Mukul, Here is a completed and verified Zybo-Z7-10 Getting started with Zynq project done in Vivado 2018.2. 1) Please download and run this project. Does this project work for you? When you started you project did you select the zybo z7-10 board file as shown below. thank you, Jon
  33. 1 point
    Hi @gregsa WF beta v3.10.3 lets you select extended frequency, up to 25MHz for AD. Note that at such high frequencies the signal will be attenuated.
  34. 1 point
    Hi @Ahmed Alfadhel, Glad to hear that the UART is now working and you have the microblaze input at 333 MHz. thank you, Jon
  35. 1 point

    Nexys 3 Pmod Nav Problem

    Hi @NiLo, I have not found any verilog projects with the PmodNAV. I did find a FPGA-Based Real-Time SLAM paper that might be helpful. cheers, Jon
  36. 1 point
    Hi, >> I understand the if the pin is an output, then current should exit from it Most likely, your understanding of the output cell is wrong.The point is the "C" in CMOS, "complementary". Look at the first picture in the link - there are two (MOS) transistors, one to positive supply voltage and one to negative / GND. The pin can source and sink current. This is the magic behind almost all modern digital circuitry. And if anybody wonders what would happen if both switches would open at the same time. Magic smoke appears 🙂
  37. 1 point
    Hi @enriqeat, Presuming you are not using the same physical R1 in both circuits, the short answer is that you can run both circuits at the same time for your particular setup*. If you attempted to have the same physical R1, you will have D2 on all the time and D1 on some of the time, and a short whenever JE2 is set high (so don't set it up like I show in the attached picture). Two independent circuits will work in this situation though. As for why the circuit on the right (VCC going to JE2) works, this is because when JE2 is set as an output logic low (effectively ground with the CMOS logic), there is enough voltage potential from JE6 (VCC) to the grounded JE2 for current to flow through the LED, even though JE2 is technically an output. * As a caveat to consider though, the set-up on the right (with JE2 effectively acting as the "gatekeeper" to whether or not current flows) is not recommended as good hardware practice. The reason for this is because when JE2 is set to output logic high, what you are counting on is that the logic high voltage it provides matches VCC so there is no voltage potential between the two points and consequently no currently flow. If there was some difference in voltage, current would flow and damage one of those points (either the VCC rail or the JE2 output). The reason this works a bit better for your setup is because you have an LED which will not allow current to pass through unless the voltage threshold is met (usually around 0.7V), so with the combination of this and the over-voltage protection on these pins and on the Zybo board (I'm presuming you are using the original Zybo rather than one of the Zybo Z7's, though this should still apply on port JE in either case), you should not have any differences in voltages to be worried about. I can also confirm that I ran both circuits (separate circuits) at the same time without any issue. Let me know if you have any questions. Thanks, JColvin
  38. 1 point

    Simple HDMI pass through with NexysVideo

    Unfortunately, I do not have a NexysVideo board available. I have run the simple hdmi pass thru on both zybo and arty boards. Have you tried using a resolution of 720p yet? I find it useful to start with the lower frequencies first. Most sources and monitors have no trouble working with that.
  39. 1 point
    Hi @amitlwaghmare, 1) What DAC are you using? 2) If possible please attach your block design/wrapper/xdc and SDK code(if applicable) 3) I believe you will need to alter your initialization function to configure each DAC and to use multiple DAC's in this way. 4) Here is an example of the changes needed to be made Expanding the Number of DAC Outputs on the ADuC8xx and ADuC702x Families. thank you, Jon
  40. 1 point
    Hi @Ahmed Alfadhel, The schematic for the Arty-A7 here on the top of page 3 show that the Arduino styled header pin named G is a ground pin. I have attached a screen shot of this as well. thank you, Jon
  41. 1 point

    Board not recognized - please help!

    Hi @ebattaglia42 Please take a look at the: Which board revision do you have? On rev F and earlier the USB EEPROM could be erased by spikes on 12V supply, like due to often connect/disconnects. You can find this on the bottom of the board, under Xilinx/TI logo Do you see at step 6 USB device id 04B4/8613 ? If so, use the reprogramming application sent to you in private message.
  42. 1 point
    and are you using the probe in x10 mode?
  43. 1 point
    are you maybe using a low-speed analog output with 200 ohms series resistor? Check the schematic of the board for a direct output.
  44. 1 point
    Hi @ebattaglia42, What operating system are you currently on? If you are Windows, can you attach a picture of what is shown in the Windows Device Manager and what you see in the WaveForms Device Manager (it should pop up when you initially connect the EE Board). The other thing I would suggest to try would be to use a different USB cable (make sure it's not just for charging only) and/or USB port on your computer as that is another source of error that is easy to check. Thank you, JColvin
  45. 1 point
    So the picture that you post of a (relatively) gigantic scope probe clip resting on a fairly small FPGA device in a BGA package is a way of making a statement. It might also be viewed as a picture that might be making a statement to you. I routinely use an LED to verify that my design is at least being clocked properly. Make a 32-bit counter and connect bit 26 or so to an obuf driving one of the boards LEDs. You can get an approximation of a 1 blink/s LED rate with a little math depending on the clock rate and the chosen counter bit. For me the clock rate of interest isn't the external clock coming into the FPGA but some clock output of an MMCM or PLL that I'm using for my design. If the LED is blinking then I at least know that something is alive in my design. You've got to be careful with those large scope probe grabbers around fine pitch components. I prefer to bring out a few debug versions of particular signals of interest to a PMOD and connect that to a scope probe ( the PMOD has DGND pin(s) ). You still have to exercise some caution with the ground clip on your scope probe as it's easy to short an adjacent pin to ground and ruin your day. It would be very useful if Digilent provided GND test points, or at least holes for test points, in an area of their boards for scope probing. The safest thing might be to stick a pin into the GND receptacle of one PMOD connector and probe on signals in another. Insulation stripped off suitably sized wires can help as well to keep ground clips from accidents. It's really easy to have that ground clip pop off whatever it's connect to and bounce around on exposed parts of your board; nothing good will come of that. I limit scope probing to when it's necessary. There are usually safer ways to evaluate signals in your FPGA design. Lastly, you should understand that its very easy to get a false impression of what a signal looks like, especially with normal scope probe ground clips. Think Heisenberg.
  46. 1 point
    In WF 3.10.2 (windows build) useless restart is corrected: https://forum.digilentinc.com/topic/8908-waveforms-beta-download/
  47. 1 point

    WaveForms beta download

    3.10.6 digilent.waveforms_beta_v3.10.6_64bit.exe Added: - Scope - access to digital channels from custom mathematic channels - digital measurements view Fixes 3.10.5 digilent.waveforms_beta_v3.10.5_64bit.exe digilent.waveforms_beta_3.10.5_amd64.deb digilent.waveforms_beta_3.10.5.x86_64.rpm Added: - Power Supplies for AD2: tracking, slider, min/max - Logic Analyzer: Measurements - Impedance Analyze: DC mode compensation - SDK VB wrapper, C# wrapper updated Fixed: - EExplorer Wavegen AM/FM index precision for sine 3.10.4 digilent.waveforms_beta_v3.10.4_64bit.exe Fixed: - decimal resolution in Export, Data and Event views 3.10.3 digilent.waveforms_beta_v3.10.3_64bit.exe digilent.waveforms_beta_v3.10.3.dmg digilent.waveforms_beta_3.10.3_amd64.deb digilent.waveforms_beta_3.10.3.x86_64.rpm Added: - UART format option (binary, decimal...) - SDK I2C without clock stretching - SDK examples: Digital_I2c_PmodAcl.py, Digital_I2c_PmodGyro.py - Spectrum Analyzer THDN measurement, THDp and THDNp in percentage units - Impedance Analyzer: - constant current, voltage, custom script for amplitude and resistance control - Option to disable mouse drag and wheel operations on plots - Impedance/Network Analyzer: averaging time - Wavegen: extended frequency option Changed: - special values (none, off) moved to end of the preset list 3.10.2 digilent.waveforms_beta_v3.10.2_64bit.exe digilent.waveforms_beta_v3.10.2_32bit.exe digilent.waveforms_beta_v3.10.2.dmg digilent.waveforms_beta_v3.10.2_mavericks.dmg digilent.waveforms_beta_3.10.2_amd64.deb digilent.waveforms_beta_3.10.2_i386.deb digilent.waveforms_beta_3.10.2.x86_64.rpm digilent.waveforms_beta_3.10.2.i686.rpm Added: - Impedance Analyzer - voltage, current and custom plots - edit Meter list - Resistance mode for Meter, Frequency DC option - step mode in Time view - Netowrk Analyzer - step mode in Time and FFT views - amplitude table and custom function Fixed: - Help minor fix - Protocol SPI and I2C Sensor rate improvement - StaticIO button lock 3.8.22 digilent.waveforms_beta_v3.8.22_64bit.exe digilent.waveforms_beta_v3.8.22_32bit.exe Added: - Impedance differential setup, W1-C1P-DUT-C1N-C2-R-GND 3.8.21 digilent.waveforms_beta_v3.8.21_64bit.exe digilent.waveforms_beta_v3.8.21_32bit.exe digilent.waveforms_beta_v3.8.21.dmg digilent.waveforms_beta_3.8.21_amd64.deb digilent.waveforms_beta_3.8.21_i386.deb digilent.waveforms_beta_3.8.21.x86_64.rpm digilent.waveforms_beta_3.8.21.i686.rpm Added: - data property for impedance/network channels. - Impedance.Resistor.reference property - instruments accessible without index in Script tool like Scope. Fixes... 3.8.20 digilent.waveforms_beta_v3.8.20_64bit.exe Added: - Logger function access to other channels value, average, min, max - Script access to Logger channel set data property, getting average, minimum, maximum Fixed: - Logger Show/Maximum - Script Protocol.I2C.Clear() function 3.8.18 digilent.waveforms_beta_v3.8.18_64bit.exe digilent.waveforms_beta_v3.8.18_32bit.exe digilent.waveforms_beta_v3.8.18.dmg Added: - Network Analyzer - logarithmic scale and percentage unit - spectrum measurements: Carrier, THD+N, THD, HD# - FFT view - Averaging option 3.8.17 digilent.waveforms_beta_v3.8.17_64bit.exe digilent.waveforms_beta_v3.8.17_32bit.exe digilent.waveforms_beta_v3.8.17.dmg digilent.waveforms_beta_3.8.17_amd64.deb digilent.waveforms_beta_3.8.17_i386.deb digilent.waveforms_beta_3.8.17.x86_64.rpm digilent.waveforms_beta_3.8.17.i686.rpm Added: - Scope - persistence support for smooth curve and min/max sampling - custom math - current value in custom math function, can be used for averaging - initialization code for integration purposes - examples - unit presets for: ohm, degree, VAC, AAC - Spectrum - Import/Export samples for Traces - trace information option - Range option to adjust all the scope input ranges - Network and Spectrum - Script support for set magnitude property - Step size and steps per decade settings - Network Analyzer - custom plots: THD, HD2, HD3 - Protocol - I2C/Spy glitch filter based on frequency setting - Device options - On Close: Run (keep running), Stop, Shutdown - USB Power: Always ON or Stop with AUX for AD2 - USB Limit: USB current limitation AD1,2 - Audio Output: AD1, 2 - WaveForms SDK FDwfParamSet/Get, FDwfDeviceParamSet/Get - DwfParamOnClose, DwfParamUsbPower, DwfParamLedBrightness, DwfParamAudioOut, DwfParamUsbLimit - Notes toolbar show/hide option - on/off icon for toggle buttons: supply enable, network analyzer reference... - show entire capture button Changed: - renewed mouse wheel, drag and key (left,right,up,down) operation on plots and axis Fixed: - EExplorer output glitch during first device connection - NI VI crash when initializing without device connected - Scope XY plot 3.8.11 digilent.waveforms_v3.8.11_64bit.exe digilent.waveforms_v3.8.11_32bit.exe digilent.waveforms_v3.8.11.dmg digilent.waveforms_3.8.11_amd64.deb digilent.waveforms_3.8.11_i386.deb digilent.waveforms_3.8.11.x86_64.rpm digilent.waveforms_3.8.11.i686.rpm Added: - Digital Discovery: - LED brightness option - Logic Analyzer - ASCII format for: Bus, SPI, I2C, I2S - Format option for I2C - Logic Analyzer and Patterns - Line Color option - Protocol - Format option for SPI and I2C: Hexadecimal, Decimal, Binary, ASCII - Plot Width option in application settings Changed: - drawing quality improvement for thicker lines - color dialog buttons renamed to Close and Reset 3.8.9 digilent.waveforms_v3.8.9_64bit.exe digilent.waveforms_v3.8.9_32bit.exe digilent.waveforms_v3.8.9.dmg digilent.waveforms_3.8.9_amd64.deb digilent.waveforms_3.8.9_i386.deb digilent.waveforms_3.8.9.x86_64.rpm digilent.waveforms_3.8.9.i686.rpm Added: - WF/Settings/Options: Locale with System or English US regional option, export and import options - SDK: FDwfParamSet/Get function - Scope: measurement resolution Fixed: - minor issues 3.8.8 digilent.waveforms_v3.8.8_64bit.exe digilent.waveforms_v3.8.8_32bit.exe digilent.waveforms_v3.8.8.dmg Added: - WF SDK: - examples updated to be Python v3 compatible - FDwfAnalogImpedance functions for impedance/network analysis - Protocol: CAN receiver filter by ID - Impedance: Export information about amplitude and offset Fixed: - WF SDK: FDwfDigitalSpi functions read MISO/RX 3.8.7 digilent.waveforms_v3.8.7_64bit.exe Fixed: - Scope: save/load of coefficients for custom Math channel filter 3.8.6 digilent.waveforms_v3.8.6_64bit.exe digilent.waveforms_3.8.6_amd64.deb Added: - Export: Wavegen and Supplies information added to Scope, Spectrum, Impedance, Network export comments Fixed: - Script Tool.exec timeout - CAN high polarity option in Protocol tool and WF SDK 3.8.5 digilent.waveforms_v3.8.5_64bit.exe Added - Script functions: getSaveFile, getOpenFile, getDirectory - Scope: multiple scales, zero offset - Notes view - Export options: notes, header as comment - Help tab: floating/undock option, find with highlight Fixed: - Impedance Analyzer frequency scale in export 3.7.22 digilent.waveforms_v3.7.22_64bit.exe digilent.waveforms_v3.7.22_32bit.exe digilent.waveforms_v3.7.22.dmg digilent.waveforms_3.7.22_amd64.deb digilent.waveforms_3.7.22_i386.deb digilent.waveforms_3.7.22.x86_64.rpm digilent.waveforms_3.7.22.i686.rpm Added - Scope/Logic View/Logging picture format - Script: - Export function for instruments - access to Protocol/UART/RX using Receiver, Receive and ReceiveArray functions, SendArray Fixed - Scope edge trigger position for all devices, when only one or two samples are above the threshold - other minor fixes 3.7.21 digilent.waveforms_v3.7.21_64bit.exe digilent.waveforms_v3.7.21_32bit.exe digilent.waveforms_3.7.21_amd64.deb digilent.waveforms_3.7.21_i386.deb digilent.waveforms_3.7.21.x86_64.rpm digilent.waveforms_3.7.21.i686.rpm Added - Wavegen dynamic configuration, adjustments without restarting the generator - SDK support for CAN bus TX, RX - more detail in Spectrum, Network and Impedance Analyzer export comments - import data orientation option Fixed - Network Analyzer Meter export and copy - Data Logger quick measurements - other fixes and optimizations 3.7.19 digilent.waveforms_v3.7.19-2_64bit.exe digilent.waveforms_v3.7.19-2_32bit.exe digilent.waveforms_v3.7.19.dmg digilent.waveforms_3.7.19-2_amd64.deb digilent.waveforms_3.7.19-2_i386.deb digilent.waveforms_3.7.19-2.x86_64.rpm digilent.waveforms_3.7.19-2.i686.rpm Added: - Logic I2S Show channel option - SDK functions for UART, SPI, I2C master and UART receiver Changed: - OS-X rollback to FTDI driver 1.2.2 Fixed: - Impedance Analyzer: save/load of views positions - other fixes and optimizations 3.7.15 digilent.waveforms_v3.7.15_64bit.exe digilent.waveforms_v3.7.15_32bit.exe Added: - Logic Analyzer: position (Nth word) option for SPI trigger on value - Impedance: Nyquist plot; settle time, minimum periods options - Wavegen, Network/Impedance Analyzer: external Amplification option - Tabbed/Docking window switching from main window Changed: - lower frequency limit for Scope, AWG, Network, Impedance Fixed: - 10ns delay in Logic Analyzer Sync and Protocol interface - Sound Card device CPU usage 3.7.14 digilent.waveforms_v3.7.14_64bit.exe digilent.waveforms_v3.7.14_32bit.exe Added: - Protocol I2C ACK/NAK last read byte option Changed: - Windows XP, Vista compatible FTDI driver in 32bit installer 3.7.13 digilent.waveforms_v3.7.13_64bit.exe digilent.waveforms_v3.7.13_32bit.exe digilent.waveforms_v3.7.13.dmg digilent.waveforms_3.7.13_amd64.deb digilent.waveforms_3.7.13_i386.deb digilent.waveforms_3.7.13.x86_64.rpm digilent.waveforms_3.7.13.i686.rpm Added: - Sound Card device of the computer can be used as Scope and Wavegen - Scope sampling clock for Electronics Explorer - Logic Analyzer data compression for recording, for Electronics Explorer - Scope and Wavegen support for 4th device configuration of Analog Discovery 1 & 2 - Scope Logging Repeat option - Scope Audio view: Stereo, Tempo options - MacOS option for application menu 3.7.12-2 digilent.waveforms_v3.7.12-2_64bit.exe Fixed: - Analog Discovery 2 configuration file descriptions 3.7.12 digilent.waveforms_v3.7.12_64bit.exe digilent.waveforms_v3.7.12_32bit.exe Added: - Scope sampling clock under time options, for Analog Discovery 1 & 2. The trigger IOs can be used as sample clock with delay and edge options. - Logic Analyzer data compression for recording, for Analog Discovery 1 & 2 Changed: - Windows installer: - embedded prerequisites: Windows Installer, Visual C++ Redistributable 9 32/64bit, 12 64bit - split installer for 32bit and 64bit WF applications, but the included WF runtime for custom applications support both architectures Fixed: - Logic Analyzer UART frame error threshold 3.7.10 digilent.waveforms_v3.7.10.exe Added: - Spectrum Analyzer Markers Fixed: - SDK Electronics Explorer enumeration - Scope Math channel unit presets 3.7.9 digilent.waveforms_v3.7.9.exe Fixing: - Logic Analyzer Event view double click for signals 3.7.8 digilent.waveforms_v3.7.8.exe Changed: - Impedance Analyzer: - view names - solid line for magnitude Fixed: - Impedance Analyzer admittance |Y| value 3.7.7 digilent.waveforms_v3.7.7.exe Added: - Scope and Logic trigger detector for trigger source Fixed: - warning message when connecting to EExplorer - Patterns trigger on Digital Discovery.
  48. 1 point
    Hi again, I have received the board and have tested using the standard 200 ohm series resistors and 33 ohm replacements on a 100 MHz signal. What I did was simply to forward the input 100 MHz clock on the Arty to two output pins, one with the original series resistance on and one with my replacement. This was measured with an 16:1 passive (resistive) probe which presents itself as an load of about 800 ohms (made from an 750 resistor + coax), with a 50 ohm input termination on the scope (the image show 1Meg, this is from another channel). The results, as can be seen in the images, the 200 ohm pin still performs quite okey, though it was very sensitive to anything coming close or touching the board. The 33 ohm signal was rock solid. So I will continue and replace all the I/O resistors to 33 ohm, something a little bigger could probably be used as well but I have a lot of 33 ohm resistors. But is shows that the Arty has no problem, what so ever, with single ended signals up to 100 MHz so far. Another 2 cm of signal path will be added when I add my board, but this should not have any large effect on signal integrity at these speeds. Plus I have looked around the headers for GND points where I will solder extra GND paths, so there won't be a deficiency. @jpeyron Thanks for the signal lengths and the assistance! 200 Ohm: 33 Ohm: Probe:
  49. 1 point

    Differential PMOD Challenge

    I was wondering that myself for the Arty "high speed" PMODs, so I got a rather inexpensive HDMI Transmitter Expansion Module from numato (since digilent doesn't offer any HDMI PMOD modules). It has two 2x6 pin headers but the pin order is not really compatible with the Arty differential pairs nor is the distance between the two headers the same, so I had to use jumper wires (run-of-the-mill, 200mm). I used your Arty 1080p code. With the naive approach (connect and pray) max resolution all I could get was 720x480p (27MHz pixel clock). Anything with a higher pixel clock would simply fail. After giving each pair of wires a few twists though, I was able to get 1280x720p @60Hz (75 MHz). That's 750Mbps per pair, which is quite impressive. I even jiggled the wires and left my phone next to them (called a couple of times too ) but it didn't go out of sync. There could bit bit errors, but there was no obvious picture degradation (not that my eyes are any serious BER test). Couldn't get 1080p though. Maybe if I snip the wires shorter, but it's out of spec anyway and 720p is more than enough to play with. https://goo.gl/photos/7ZNUidDiTGhKtqH29 https://goo.gl/photos/gBiMt3zSNaRVzL4Y6 Zygot's challenge is very interesting by the way (as is the discussion in this thread), unfortunately I only own this Arty at the moment. It would be nice if the people at digilent could do the test with various boards and tell us what the max achievable rate is (pmod documentation is rather lacking in this area). It's still nice to see this kind of performance