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  1. 2 points
    D@n

    Default Power-up Value of Registers

    @Foisal Ahmed, I'm not sure you understand what you are asking. Uninitialized logic values in Xilinx designs are already 1'b1's. This has caused me no end of grief in the past. Simulations treat initial values differently. Most simulations will treat an uninitialized value as an unknown until it is set. This is industry practice. I know Verilator tries to set unconstrained initial values to be random numbers. This is an exception to the industry practice that is done for performance reasons. The discrepancy between Verilator and Xilinx has been the root of much grief--since uninitialized things that work in Verilator don't always work in Xilinx. Depending upon a default initial value for registers within a design, however, is poor practice. The better approach is to force registers that need initial values to whatever initial value they should have. In Verilog, this is done using an 'initial' statement. In VHDL this can be done in the declaration statement, where the register is declared in the first place. Xilinx FPGA's by design will not release your design from its initial state unless all of your registers have their declared initial values. Were you to force all LUTs in a design to be 1'b1 initially, you would break any vendor supplied IP (i.e. DDR3SDRAM core, etc) you might be working with. Can you explain more of what you are trying to accomplish? Perhaps there's a better solution for what you wish to do. Dan
  2. 2 points
    BogdanVanca

    programming guide of zynq

    Hello @Ram, Please check this link : https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-getting-started-with-zynq-server/start "This guide will provide a step by step walk-through of creating a Zynq based hardware design using the Vivado IP Integrator that will build over the Getting Started with Zynqguide by making use of the on-board Ethernet port and GPIOs for the Zybo FPGA board.". You can start from here, and use the same hardware logic but different type of application for uart, spi etc. Best Regards, Bogdan Vanca
  3. 2 points
    jpeyron

    Zedboard Zynq 7000 XADC Header

    Hi @farhanazneen, I used the Analog Discovery 2 which has the 2x15 Flywires: Signal Cable Assembly for the Analog Discovery without issue. Each signal wire is 260mm± 20. thank you, Jon
  4. 2 points
    @hamster I was able to run your AXI Slave interface. It works great! It is now very easy to exchange information between PS and PL, and it even supports execute-in-place (e.g. I can put ARM instructions to register file and run PS CPU directly from it). I have some questions about your AXI Slave design: 1) AXI_a*size has no effect on INCR type of burst transactions, but according to AXI protocol: the increment value depends on the size of the transfer. You set it only for WRAP type, is it correct? Thus, burst size is always 0 for INCR type? 2) Do you know how PS initiates INCR burst type? A kind of memset/memcpy need to be used for that or an incrementing pointer will also work? 3) Where WRAP type is necessary? How to use PS to work in WRAP mode? You may also update your wiki page with following: 0) Create provided VHDL files 1) Create a block-diagram and add PS IP core to it 2) Apply configuration provided by your board's pre-settings; this will set all necessary initialization settings for PS (e.g. clock frequencies, DDR bindings, etc.) 3) Press auto-configure (or how it's called) ==> this will connect PS IP to DDR and to fixed IO 4) Add "External ports" to the diagram (create new AXI_CLK and AXI external ports) and connect them to PS ports 5) Generate VHDL wrapping code for this block diagram 6) Put generated system under axi_test_top by renaming it to axi_test_wrapper (default name is design_#_wrapper in my Vivado version) 7) This will auto-connect block-diagram external ports with axi_test_top 8 ) Add constrains file and rename/uncomment external ports where necessary 9) Generate bitstream 10) File->Export->Hardware and create .hwf file which contains PS configuration 11) Open Xilinx SDK and create a new project: select .hwf file as Hardware BSP for this project 12) Now, Xilinx SDK will auto-generate few .c and .h files which contain necessary PS initialization ==> clocks, IRQs, DDR, etc. 13) Add hello_world.c application to the project @hamster Thank you very much. I've learned a bunch of new things thanks to your help!
  5. 2 points
    @thobie, the bare-metal purchase option for the Zybo was done to enable a lower price point for those who do not require the accessories. For the rest of our customers, adding the Accessory Kit is recommended during the purchase process. You are not the first and the last to complain about version compatibility. It is economically unfeasible for us to update all support projects, IP and support packages provided for free four times per year for each Vivado version. Instead we made a commitment to consider the last Vivado release in each year stable and do a once-a-year update cycle. In that regard, 2017.4 is the version we are upgrading projects to. There is a question whether OOB designs should be updated at all, or kept at the version which generated the binary image shipped with the board. The board presets are not versioned for Vivado (no version-specific releases in our git repo), because these should be forward-compatible with Vivado versions. The critical warning itself related to CK-to-DQS delays being negative appears starting with 2017.4. The negative values are due to CK trace being shorter than any of the four DQS traces. In the early days of Zynq board design negative values where listed as sub-optimal, but not erroneous. Tree topology instead of fly-by was also among the routing recommendations for DDR3 layouts. So the Zybo was designed with this sub-optimal layout due to space constraints. During Write Leveling calibration, 0 is used as an initial value instead of the negative preset delays. After calibration, if the skew is still too low, the clock is inverted. See ug585 pg 316 for more details. All Zybos shipped to customers are functionally tested and pass the DDR3 calibration process. Xilinx recommendations changed in the mean time, both in terms of routing topology and delay values. A trace of this can be found here: https://www.xilinx.com/support/answers/53039.html. The > 0ns requirement was introduced to be in line with non-Zynq MIG-based designs, where negative delays were never permitted. Since these delays are board-dependent, we would need to re-design the board to make the delay positive. This is impossible with the current form-factor. Another option would be modifying the board preset file and forcing a zero value instead of the actual delay. The tools seem to be using zero anyway for calibration. This will have to be thoroughly verified first.
  6. 1 point
    jpeyron

    IP used in Zybo-Z7 MIPI Pcam 5C demo

    Hi @jge64, Looking a little closer the IP Cores we made by Digilent. You can find them in the Vivado library here. Here and here are the PDF's for each IP Cores. thank you, Jon
  7. 1 point
    Hi @Foisal Ahmed, I have not changed the core voltage on a Basys 3. Here is the Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics. Here is a xilinx forum thread that discusses changing the core voltage. thank you, Jon
  8. 1 point
    zygot

    Problem wih Arty S7-50 mapping I/o Pins

    @emarte, I feel your pain. Here's my suggestion for step 1: Look at the Vivado pin report after the configuration file has been generated and check it against the schematic for the Genesys2 as well as the xdc file in your project. If everything doesn't match; fix it. Regardless, reply to this post. No matter how many times I write this ( and it's been a lot of times ) I feel compelled to say it again. Whenever you have a new design that uses IO pins check the pint report against the constraints file and the schematic before configuring hardware. Help stamp out smoking in the FPGA development workplace! ( Yes, I know; you can damage your FPGA device without the dramatic aromatic and visual clues)
  9. 1 point
    attila

    Mechanical drawing of Analog Discovery 2

    Hi @chuerta In case you need it, here you can find the step model as well:
  10. 1 point
    Hi @tcmichals You could use a custom decoder in Logic Analyzer to measure the timing and Script tool to find the min/max. The repetitive captures will have gap between them but you could use Record (Mode) to have measurement on longer continuous sequence. Decoder: c = rgData.length p0 = 1 p1 = 1 v = 0 i0 = 0 for(var i = 0; i < c; i++){ d0 = rgData[i] & 0x01 // DIO 0 d1 = (rgData[i] >> 1) & 0x01 // DIO 1 if(p0 == 0 & d0 == 1){ // DIO 0 rise reset 'v' v = 0 i0 = i } if(p1 == 0 & d1 == 1){ // DIO 1 rise store 'v' for(var j = i0; j < i; j++){ rgValue[j] = v rgFlag[j] = hzRate } } v++ p0 = d0 p1 = d1 } Value to Text: function Value2Text(flag, value){ switch(flag){ case 0: return "X"; default: return 1e6*value/flag; // us, microsecond } }
  11. 1 point
    xc6lx45

    XADC and the FFT

    BTW it should be "20*log10(fftshift(abs(fft(...)))) not 10. If you're dealing with voltage, current, wave quantities, anything that gets converted to physical power by squaring, use 20 log10 =2*10*log10(x) = 10*log10(|x|.^2)
  12. 1 point
    D@n

    XADC and the FFT

    @farhanazneen, I'm not sure how much help I can be if that error message doesn't make sense to you. You'll need to edit and "fix" your CSV file. Relax, it's text. Pull it up in an editor, examine it, then fix it. Dan
  13. 1 point
    jpeyron

    How to read from SD card on ZYBO

    Hi @shahbaz, @Notarobot is correct. I forgot the Zynq processor has the xilffs library for the SD card and that the SDcard is directly connected to the PS. You should not use the Pmod SD IP Core. I have attached some screen shots that should help with getting your project going. I used the Zybo board files. Here is a tutorial on how to install the board files if have not done so already. thank you, Jon
  14. 1 point
    Hello @farhanazneen, Please check this forum thread : There is one project for ZedBoard, and an entire discussion on how to make the pin-out. If you are still having issues, please tag me in here. Thank you. Best Regards, Bogdan Vanca
  15. 1 point
    Notarobot

    How to read from SD card on ZYBO

    Hi shahbaz, If you are Ok using micro SD card adapter embedded in Zybo I would recommend to use it with the driver xsdps provided by Xilinx. Please note that it is connected and intended for use by PS not PL. The driver is located in Vivado library \embeddedsw\XilinxProcessorIPLib\drivers\sdps In Vivado the only thing is needed is enabling SD card in the processing system. Everything else is done in SDK. There you will need to add library xilffs to the BSP. File system and functions are described in here Good luck!
  16. 1 point
    shahbaz

    Can't boot ZYBO from QSPI Flash

    hi @jpeyron Thank you for you concern. I couldn't find because I was choosing wrong board (selecting the part instead) and I missed the step for unchecking the auto update wrapper. found it in destined folder once I selected the right board.
  17. 1 point
    BogdanVanca

    Global variables in SDK

    Hello @Antonio Fasano A global variable is a variable that is declared outside all functions and it can be used in all functions, but into the same c/cpp file. If you want to pass variables between two different files, you need functions. For example you declare the prototype of the function into the main.c file and the body into the echo.c file. In this way you can pass your "int x" variable trough one of the function parameters. I hope I was clearly enough. Best Regards, Bogdan Vanca
  18. 1 point
    JColvin

    Pmod Enc and Raspberry Pi not accurate

    Hi @tpitman, I don't have a nice datasheet to the the shaft encoder to directly link you to, but we just recently (i.e. today) added a 3D step file of the Pmod ENC to it's Resource Center, so hopefully you'll be able to get all of the dimensions you need from there. Let me know if you have any questions about this. Thanks, JColvin
  19. 1 point
    D@n

    Problem in fir compiler 5.0 core

    Just to make certain we are talking about the same thing, I understand "clipping" to be an artifact of an internal overflow within the filter. The output is then mapped to the maximum possible output value. This requires over flow detection, and saturation on overflow to accomplish. You can tell this is happening very easily by looking at a histogram of the data. That histogram will have a disproportionate number of samples at the extreme values of the representation. Hence, for 8'bit math, you'll get too many values at 8'h7f or 8'h80 (or 8'h81--depending on the implementation). This is different from over-driving, where the amplifier is driven outside of its linear region. The effect can look similar, but the over-driving effect is an analog effect, whereas clipping is digital. In this case, you would get a disproportionate number of samples "near" the limits or your representation, but not necessarily at the limits. Both clipped and overdriven audio will sound distorted (if you listen well), but will generally be recognizable. They won't sound "noisy". This is different from the "ticking" effect the poster was struggling with in the post you started responding to, and so would be off topic there. Clipping will only take place if you have overflow protection within your filtering IP core. If you don't put such protection into the core (like me), you'll get another effect characterized by discontinuities in the outgoing data. Unlike other distortions caused by a bug in signaling, clipping is usually really easy to fix. Clipping, or indeed any type of overflow, can be solved by any one of the below approaches. Reduce the amplitude of the input Reduce the magnitude of the filter coefficients, or Add more bits to the data representation within the filter. Any of these solutions should fix a problem with clipping. Dan
  20. 1 point
    jpeyron

    issue with the usb serial com port

    Hi @farhanazneen, Did you follow the Cypress CY7C64225 USB-to-UART Setup Guide for installing the cypress usb drivers? If yes, please try the DigilentFX2Repair.rar. thank you, Jon
  21. 1 point
    Hi @Javier olmos, Here is the resource center for the Nexys 4 DDR. Here is the master XDC. I would suggest to look at this demo as a reference on how to set up the xdc as well as the USB UART bridge. Are you using Verilog or VHDL? Can you attach your HDL code? thank you, Jon
  22. 1 point
    Hello @farhanazneen, Please check page 36 from the fallowing link : https://www.xilinx.com/support/documentation/user_guides/ug480_7Series_XADC.pdf . There you will find an table that contains all the addresses for the status and control registers. Best Regards, Bogdan Vanca
  23. 1 point
    Hi @Zulqar In the Wavegen select Synchronized mode, select to show Channel 2 too, select Play mode in both. Import the file twice, column 1 the 2, select these for Wavegen 1 and 2. Configure the Scope to Record, set trigger Normal on Wavegen1. Start Scope then Wavegen. For custom application see the analog in/out play/record Python examples in WaveForms SDK
  24. 1 point
    mouse123

    sampling filtering

    hi I got my AD2 and started to explore. some silly questions: 1. the sampling rate seems automatically set according to time division selected. why the sampling rate is changed based on the time scale? can it be set by customer at a fixed rate? 2. is there DSP filtering function available, such that I could added a new channel that was low-passed filtered channel of 1+ scope channel? 3. Can the scope graph display real time elapses of signals instead of fixed 8000 samples at fixed time window? how to export to the recorded traces?
  25. 1 point
    lukeswr

    Adept library to use in visual .net c#

    I have an excellent example of interfacing with non-managed libraries using an internal sealed class. I have attached the file. I copied this foot print from another interface class regarding a USB interface. This example is nowhere near complete, but it provides the building block. using System; using System.IO; using System.Runtime.InteropServices; namespace Linear.common.lap.Digilent.Adept2 { /// <summary> /// This class library provides the 64-bit interface to the Digilent Inc. Adept2 dmgr library. /// </summary> internal sealed class StaticDmgr : IDisposable { // ReSharper disable InconsistentNaming /// <summary> /// The following value is passed to DmgrGetTransResult to specify /// wait until the transfer completes. /// </summary> public const UInt32 tmsWaitInfinite = 0xFFFFFFFF; // Handle to our DLL - used with GetProcAddress to load all of our functions private IntPtr hDMGR = IntPtr.Zero; // Declare pointers to each of the functions we are going to use in DMGR.DLL // These are assigned in our constructor and freed in our destructor. private readonly IntPtr pDmgrGetVersion = IntPtr.Zero; private readonly IntPtr pDmgrEnumDevices = IntPtr.Zero; private readonly IntPtr pDmgrGetDvc = IntPtr.Zero; private readonly IntPtr pDmgrIsEnumFinished = IntPtr.Zero; private readonly IntPtr pDmgrStopEnum = IntPtr.Zero; private readonly IntPtr pDmgrFreeDvcEnum = IntPtr.Zero; internal StaticDmgr() { // If DMGR.DLL is NOT loaded already, load it if (hDMGR == IntPtr.Zero) { // Load our DEPP.DLL library hDMGR = LoadLibrary(@"DMGR.DLL"); if (hDMGR == IntPtr.Zero) { // Failed to load our DEPP.DLL library from System32 or the application directory // Try the same directory that this Adept2 DLL is in hDMGR = LoadLibrary(@Path.GetDirectoryName(GetType().Assembly.Location) + "\\DMGR.DLL"); } } if (hDMGR == IntPtr.Zero) throw new ApplicationException("Cannot locate the driver's DMGR.DLL interface library."); // If we have succesfully loaded the library, get the function pointers set up // Set up our function pointers for use through our exported methods pDmgrGetVersion = GetProcAddress(hDMGR, "DmgrGetVersion"); pDmgrEnumDevices = GetProcAddress(hDMGR, "DmgrEnumDevices"); pDmgrGetDvc = GetProcAddress(hDMGR, "DmgrGetDvc"); pDmgrIsEnumFinished = GetProcAddress(hDMGR, "DmgrIsEnumFinished"); pDmgrStopEnum = GetProcAddress(hDMGR, "DmgrStopEnum"); pDmgrFreeDvcEnum = GetProcAddress(hDMGR, "DmgrFreeDvcEnum"); InitializeDelegates(); } private void InitializeDelegates() { if (pDmgrGetVersion == IntPtr.Zero) throw new ApplicationException("Failed to load function DmgrGetVersion."); if (pDmgrEnumDevices == IntPtr.Zero) throw new ApplicationException("Failed to load function DmgrEnumDevices."); if (pDmgrIsEnumFinished == IntPtr.Zero) throw new ApplicationException("Failed to load function DmgrIsEnumFinished."); if (pDmgrStopEnum == IntPtr.Zero) throw new ApplicationException("Failed to load function DmgrStopEnum."); if (pDmgrFreeDvcEnum == IntPtr.Zero) throw new ApplicationException("Failed to load function DmgrFreeDvcEnum."); DmgrGetVersion = (tDmgrGetVersion)Marshal.GetDelegateForFunctionPointer(pDmgrGetVersion, typeof(tDmgrGetVersion)); DmgrEnumDevices = (tDmgrEnumDevices)Marshal.GetDelegateForFunctionPointer(pDmgrEnumDevices, typeof(tDmgrEnumDevices)); DmgrGetDvc = (tDmgrGetDvc)Marshal.GetDelegateForFunctionPointer(pDmgrGetDvc, typeof(tDmgrGetDvc)); DmgrIsEnumFinished = (tDmgrIsEnumFinished)Marshal.GetDelegateForFunctionPointer(pDmgrIsEnumFinished, typeof(tDmgrIsEnumFinished)); DmgrStopEnum = (tDmgrStopEnum)Marshal.GetDelegateForFunctionPointer(pDmgrStopEnum, typeof(tDmgrStopEnum)); DmgrFreeDvcEnum = (tDmgrFreeDvcEnum)Marshal.GetDelegateForFunctionPointer(pDmgrFreeDvcEnum, typeof(tDmgrFreeDvcEnum)); } #region Instantiated Function Delegates internal tDmgrGetVersion DmgrGetVersion; internal tDmgrEnumDevices DmgrEnumDevices; internal tDmgrGetDvc DmgrGetDvc; internal tDmgrIsEnumFinished DmgrIsEnumFinished; internal tDmgrStopEnum DmgrStopEnum; internal tDmgrFreeDvcEnum DmgrFreeDvcEnum; #endregion #region IDisposable Methods /// <summary> /// Destructor for the D2XX class. /// </summary> ~StaticDmgr() { if (hDMGR != IntPtr.Zero) { // FreeLibrary here - we should only do this if we are completely finished FreeLibrary(hDMGR); hDMGR = IntPtr.Zero; } } public void Dispose() { if (hDMGR != IntPtr.Zero) { // FreeLibrary here - we should only do this if we are completely finished FreeLibrary(hDMGR); hDMGR = IntPtr.Zero; } } #endregion #region Marshalling Methods to Unmanaged DMGR /// <summary> /// Built-in Windows API functions to allow us to dynamically load our own DLL. /// Will allow us to use old versions of the DLL that do not have all of these functions available. /// </summary> [DllImport("kernel32.dll")] private static extern IntPtr LoadLibrary(string dllToLoad); [DllImport("kernel32.dll")] private static extern IntPtr GetProcAddress(IntPtr hModule, string procedureName); [DllImport("kernel32.dll")] private static extern bool FreeLibrary(IntPtr hModule); // Definitions for DMGR functions [UnmanagedFunctionPointer(CallingConvention.StdCall)] internal delegate int tDmgrGetVersion(byte[] szVersion); //OPEN & CLOSE functions internal delegate int tDmgrOpen(ref int phif, byte[] szSel); internal delegate int tDmgrOpenEx(ref int phif, byte[] szSel, int dtpTable, int dtpDisc); internal delegate int tDmgrClose(int hif); //ENUMERATION functions internal delegate int tDmgrEnumDevices(ref int pcdvc); //internal delegate int tDmgrEnumDevicesEx(ref int pcdvc, int dtpTable, int dtpDisc, int dinfoSel); //internal delegate int tDmgrStartEnum(ref int pcdvc); internal delegate int tDmgrIsEnumFinished(); internal delegate int tDmgrStopEnum(); //internal delegate int tDmgrGetEnumCount(ref int pcdvc); internal delegate int tDmgrGetDvc(int pcdvc, byte [] dvc); internal delegate int tDmgrFreeDvcEnum(); #endregion } }