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  1. 2 points
    hamster

    RISC-V RV32I CPU/controller

    I've just posted my holiday project to Github - Rudi-RV32I - https://github.com/hamsternz/Rudi-RV32I It is a 32-bit CPU, memory and peripherals for a simple RISC-V microcontroller-sized system for use in an FPGA. A very compact implementation and can use under 750 LUTs and as little as two block RAMs - < 10% of an Artix-7 15T. All instructions can run in a single cycle, at around 50MHz to 75MHz. Actual performance currently depends on the complexity of system bus. It has full support for the RISC-V RV32I instructions, and has supporting files that allow you to use the RISC-V GNU toolchain (i.e. standard GCC C compiler) to compile programs and run them on your FPGA board. Here is an example of the sort of code I'm running on it - a simple echo test:, that counts characters on the GPIO port that I have connected to the LEDs. // These match the address of the peripherals on the system bus. volatile char *serial_tx = (char *)0xE0000000; volatile char *serial_tx_full = (char *)0xE0000004; volatile char *serial_rx = (char *)0xE0000008; volatile char *serial_rx_empty = (char *)0xE000000C; volatile int *gpio_value = (int *)0xE0000010; volatile int *gpio_direction = (int *)0xE0000014; int getchar(void) { // Wait until status is zero while(*serial_rx_empty) { } // Output character return *serial_rx; } int putchar(int c) { // Wait until status is zero while(*serial_tx_full) { } // Output character *serial_tx = c; return c; } int puts(char *s) { int n = 0; while(*s) { putchar(*s); s++; n++; } return n; } int test_program(void) { puts("System restart\r\n"); /* Run a serial port echo */ *gpio_direction = 0xFFFF; while(1) { putchar(getchar()); *gpio_value = *gpio_value + 1; } return 0; } As it doesn't have interrupts it isn't really a general purpose CPU, but somebody might find it useful for command and control of a larger FPGA project (converting button presses or serial data into control signals). It is released under the MIT license, so you can do pretty much whatever you want with it. Oh, all resources are inferred, so it is easily ported to different vendor FPGAs (unlike vendor IP controllers)
  2. 1 point
    I'm quite sure you can use one account (I have done so on several PCs myself with Webpack). Looking at that license file, it says HOSTID=ANY To me, this looks like (but someone correct me if I'm wrong) that the free webpack license isn't even tied to one specific machine.
  3. 1 point
    I will try it to see how it works. Thank you too.
  4. 1 point
    To clarify, the Microblaze clock was set to 100Mhz, and the Axi Quad SPI used the default internal frequency ratio, which I think is 16, so I got a SCLK frequency of around 6 Mhz. But you say that you fixed it, and I want to know which mode did you use and it's working properly with Pmod DA4?
  5. 1 point
    What is the fixed version you are using? The clock was 100Mhz when I used it with Microblaze.
  6. 1 point
    JColvin

    Academic Pricing

    Hi @rober423, Are you still encountering this error? I know one thing that I had to do in the past was disable my ad-block since that was preventing the page from properly loading. Thank you, JColvin
  7. 1 point
    asmi

    Public service announcement: PLL locking

    You can force config logic to wait for PLL/MCMM locks before GSR deassertion and design startup. RTFM: UG472 table 3-7, parameter STARTUP_WAIT. But you've got to be careful with this option as design will never start if one of clocks is not present at startup - typical case being HDMI input, or just about any non-MGT high-speed input for that matter. So it's fine to use it for system clock(s), but it's a definitely "NO" for IO clocks.
  8. 1 point
    JColvin

    Storing Atlys PLB project to SPI/Flash

    Hi @chcollin, Re-reading the tutorial, the bootloader that is provided is intended to reader from the SPI flash via the Xilinx In-System Flash library (as opposed to the default provided by SDK that uses parallel NOR Flash) specifically for the flash on the Spartan-6 LX9 MicroBoard. Based on Table 5-5 (Spartan-6 FPGA Bitstream Length) in the corresponding User Guide, the default bitstream length is much larger for the LX45 device (11,939,296 bits), corresponding to 1.4574 MB. Looking at the flash used on the Atlys (a N25Q128 Numonyx chip which has 64 KByte sectors), this would use the first 23 sectors, leaving 233 sectors (~14,900 KBytes) for the application. It is also possible to compress the bitstream to have it use less resources, though I don't know how much it would get compressed. Extrapolating from the Avnet tutorial, the offset to choose in the blconfig.h file (create boot loader application, step 9) should be 0x170000. With regards to the flash family, I think you would want to choose the 5th one (Spansion) based on the Xilinx documentation for xilisf, since that Spansion option also apparently counts for Micron (and I understand the Numonyx chips are now owned by Micron), though I am uncertain about this since the tutorial I linked you to states that Micron devices have the same control set as STM (option 3). I'm not certain on the XPAR_SPI_FLASH_DEVICE_ID bit; everything that I have found leaves this value unchanged. I'll keep looking and let you know if I find something. Thanks, JColvin
  9. 1 point
    JColvin

    Storing Atlys PLB project to SPI/Flash

    Sweet, I'm glad to hear the design has been exported; I hope the bootloader side of things in SDK works as well.
  10. 1 point
    chcollin

    Storing Atlys PLB project to SPI/Flash

    Update 1 I managed to add xps_spi core to HDMI_DEMO project and export design 😀 As I didn't know how to configure it, I started a new XPS project from scratch using BSB wizard and Atlys_PLB_BSB_Support files to retrieve those needed information. Then, back to HDMI_DEMO project, I configured my new xps_spi core as follows : Added those lines to system.ucf : Net xps_spi_0_SCK_pin LOC=R15 | IOSTANDARD=LVCMOS33; Net xps_spi_0_MISO_pin LOC=R13 | IOSTANDARD=LVCMOS33; Net xps_spi_0_MOSI_pin LOC=T13 | IOSTANDARD=LVCMOS33; Connected xps_spi core ports to those. Finaly, configured xps_spi core as indicated in screenshots. Export was successful. I'll do the SDK part tomorrow. Thanks again @JColvin
  11. 1 point
    zygot

    Vitis

    @JColvin, I really appreciate your help. I suspect that I could have had more success by choosing the 'Hello' Application but why bother? I will pursue a Zedboard Vitis project and if it's interesting will post it. It'll be a tertiary level enterprise though. At this point I've concluded that Vitis and therefore Vivado 2019.2 or later are 'not ready for prime time'. Actually Vivado 2016.2 on WIn7 is my main HDL Xilinx toolset 'main squeeze' and except for a few idiosyncrasies gets the job done. At least I'm familiar with it's quirks. I still can't figure out why implementing a memory viewer in Vivado Simulator is so hard... Quartus has had a hardware memory tool for decades.... ISE ISIM can do it. A lot of my angst has to do with the knowledge that the Win7 box will die someday and I really haven't found a suitable successor yet. IF only Centos 6 were based on a slightly later Kernel it would be one OS to last (almost) forever.
  12. 1 point
    Hi @dos6510 In the WF SDK the CS is controlled by software, so it has a latency of 1-10ms. In the WF app Protocol/I2C/Sensor the instructions in loop are translated to a custom pattern. This constant pattern can be repeated at high rate. This ideal for sensor where the same command is sent out and the received data can be decoded in parallel. See the SDK/samples/py/DigitalOut_CustomBus.py
  13. 1 point
    rfx

    Arty-Z7-20-base-linux Build

    And why dont you add a documentation for the display shield. I think that the spi_ss should be assigned to the default location (J6 SPI Connector). someone who uses the display-shieled can alter his board-files. the change to spi_ss is not documented (well) and took me a day to find out. the J6 connector is the documented SPI interface of the board and with the problem of the interchanged pins it simply does not work.
  14. 1 point
    Ana-Maria Balas

    cmod a7 TRX/MGTs available?

    Yes the transceivers are not routed on Cmod A7, because you would need a high-speed connector, which would increase the cost of the board and this was not the intention for a small board. The only board with Artix 7 is Nexys Video, which has a FMC connector.
  15. 1 point
    Hi @fmilburn, I have asked some engineers more familiar with WaveFormsLive about this. Thanks, JColvin
  16. 1 point
    Hi @chcollin, I don't have EDK available to me to be able to test the Atlys HDMI demo (nor did I directly find answers to the questions you put in quotes), but I was able to locate a reference design for a Spartan 6 chip that creates a MicroBlaze SPI flash bootloader that uses PLB here: https://www.avnet.com/shop/us/products/avnet-engineering-services/aes-s6mb-lx9-g-3074457345628965461?aka_re=1. The Reference Design is called "EDK 12.4 Tutorials Creating a MicroBlzae SPI Flash Bootloader for AES-S6MB-LX9-G". I have attached the pdf tutorial that walks through the process that came with that download for convenience. Let me know if you have any questions about this (or if this was not what you were looking for in your situation). Thanks, JColvin MicroBlaze_SPI_Bootloader_12_4_1.pdf
  17. 1 point
    Hello @JKing, The system boards are from Xilinx, and the adapter board and DAC boards are from Analog Devices, so maybe you would find better responses on the Xilinx forum or Analog Devices, rather from our forum. However, I asked one of our engineers about this issue and here is the response I got: For KC705 case with AD-DAC-FMC-ADP adapter and AD9142A-M5375-EBZ board compatibility between the pins from the DAC board, through the adapter board and up to the FPGA seems OK, for both FMC connectors on the KC705 board. Logical levels: The DAC uses LVDS, on the KC705 board the logical levels LVDS_25 must be set (they are the only ones available from the HR banks, where the FMC connectors are connected). Maximum frequencies / maximum data rates at FPGA banks: in https://www.xilinx.com/support/documentation/data_sheets/ds182_Kintex_7_Data_Sheet.pdf on page 14, in Table 17, data rates for "DDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 14)", in the HR bank, for speed grades -2 (which is on the KC705 board), is 1250 Mb/s : -The DAC can support a maximum of 575MHz on the DCI clock, with the data squared on opposite fronts (I and Q respectively, on opposite fronts of the clock) => 575Mb/s maximum useful data rate required by the DAC. -Since we have to send the data to the DAC in quadrature, the maximum useful FPGA data rate is half of 1250 Mb/s, ie 625 Mb/s. - 575Mb/s <625Mb/s, so it should be OK. For security, you should look for a reference / example design with OSERDES for the respective board, modify it for your DAC and try to compile it with the desired frequencies, to see if the implementation passes. -DATA_WIDTH = 4 to 14 at OSERDES does not affect us, because we actually receive the data of a word in parallel, on different LVDS pairs. -If we were to use DAC in byte mode, then we would need 2 clock cycles to send 16 bits of I and 16 bits of Q. Of the 1250Mb/s that supports FPGA, we would remain with ¼, that is with 312.5 Mb/s, less than 575Mb/s, so I would not reach the maximum DAC rate. Timing analysis: The FPGA must send the data synchronously with each edge of the DCI clock. Fortunately, the DAC has a DLL and a delay line respectively; Depending on the working frequency, one of the two can be used to ease the timing requirements (i.e. to apply a delay between the clock and the data, so that the timing of the DAC is satisfied). You should analyze the rest of cases: KCU105 with AD9142A-M5375-EBZ; KC705 with AD9122-M5375-EBZ; KCU105 with AD9122-M5375-EBZ. Best regards. Ana-Maria Balas
  18. 1 point
    hamster

    CMOD A7 Audio board...

    The last of the parts came in and the new board is up and running. Here's the old and new boards side by side, and spectrum of a 10kHz test tone going from the ADC, through the FPGA and then DAC (top = new board, middle = old board, bottom = no board in the loop. The additional work I did on grounding on the PCB has paid off, with a very good noise floor - better than I can measure with the tools I have to hand.
  19. 1 point
    hamster

    RISC-V RV32I CPU/controller

    I just had a look at the J1b source, and saw something of interest (well, at least to weird old me): 4'b1001: _st0 = st1 >> st0[3:0]; .... 4'b1101: _st0 = st1 << st0[3:0]; A 32-bit shifter takes two and a half levels of 4-input, -2 select MUXs per input bit PER DIRECTION (left or right) and the final selection between the two takes another half a LUT, so about 160 LUTs in total (which agrees with the numbers above) However, if you optionally reverse the order of bits going in, and then also reverse them going out of the shifter, then the same shifter logic can do both left and right shifts. This needs only three and a half levels of LUT6s, and no output MUX is needed. That is somewhere between 96 and 128 LUTs, saving maybe up to 64 LUTs. It's a few more lines of quite ugly code, but might save ~10% of logic and may not hit performance (unless the shifter becomes the critical path...).
  20. 1 point
    attila

    Waveform Feature Requests

    Hi @Mr.Spriggs In the next software version you will have a global option in Protocol tool for data and/or time stamps.
  21. 1 point
    @weilai, The .prj file @JColvin refers to is an XML (i.e. text) file. I was able to use it to create this UCF file. That's going to be the least of your problems. See my answers in the other thread for more of what you'll need to deal with. Dan
  22. 1 point
    This is really something to consider in the long term. X and A have a strong interest to make us use their respective processor offerings. Nothing ever is for free and we may pay the price later when e.g. some third-party vendor (think China) shows up with more competitive FPGA silicon but I'd need a year for migrating my CPU-centric design. For industrial project reality, accepting vendor lock-in may be the smaller evil but if you have the freedom to look ahead strategically (personal competence development is maybe the most obvious reason for doing so, maybe also government funding) there may be wiser options. This is at least what keeps me interested in soft-core CPUs even though its absolute KPIs are abysmally bad.
  23. 1 point
    zygot

    Cmod A7 massive GND noise

    @steddyman Measuring ground noise is not trivial but let's assume that your measurements are correct. You don't provide a lot of details about your prototype. Are you using a custom PCB with headers for plugging in your CMOD? Are you using a lot of the CMOD IO? There were a lot of design choices made for the CMODs that aren't optimal for prototyping, which is odd as this is clearly what the modules are intended for. Having a single GND and Vcc pin is one of those choices that are unfortunate. This doesn't make the modules a bad product but might well limit what kinds of things that you can do with them. Companies that make products that they don't actually use to develop real applications don't always evaluate the correct questions in making design choices.
  24. 1 point
    There is no satisfactory answer because there is no we, and there is no one type of problem to solve. As @xc6lx45has pointed out, in a way, field programmable devices can't compete with non-programmable device in certain areas. Processors, even multi-core ones, have there own limitations and certainly don't come with an infinite variety of external interfaces supporting every possible application. So, typically a product solution is a combination of processor and programmable logic for connecting that processor to the real world. Sometimes programmable logic isn't needed al all. Sometimes a processor isn't needed. Most often a combination is the best choice; and in that case one device with a hard logic processor, like the ARM, make good sense. Occasionally, the case for implementing a soft-processor in logic is compelling, if done correctly, and you can choose your own software development tools. Developing and maintaining software has always been difficult for product manufacturers. Developing and maintaining programmable logic designs are even more difficult as products mature. As you have not doubt observed, the HW/SW co design flow is more complicated than than an all HDL flow. A lot of the reason for this has to do with the vendors releasing tool versions that are not backward compatible with previous tool versions. Some of this is unavoidable, some is not. We all out up with nonsense from vendors that seem to them to be good business. Is there really a good reason why I need to run WinXP in a VM on WIN10 to run an older program? Only because customers who are happy with what they have aren't spending money on new stuff and our society's use of capital requires ever increasing customer spending to sustain itself. As someone trying to hone my FPGA development chops I find that an all HDL flow works best most of the time. But then I'm not so concerned with cost, development hours, power dissipation, thermal budgets, and long term customer support. Sometimes a ZYNQ make the most sense in order to accomplish a task and then I have to put up with the extra headaches involved. If I were making a product then I'd design a platform that makes the most sense from a large variety of considerations. Unfortunately, there are times when vendors foist the FPGA with hard processor platform upon us for reasons that aren't in our best interests. Will programmable logic only devices disappear altogether some day? Perhaps. Might this ever be a good thing? I don't know.
  25. 1 point
    ... some numbers. Yes, apples are not oranges , this is about orders-of-magnitude, not at all a scientific analysis and maybe slightly biased. Take the Zynq 7010. It has 17600 LUTs. Let's count each as 64 bits => 1.1 MBit for the logic functions of my application (if you like, add 2.1 MBit BRAM => 3.2 MBit). Now the ARM processor: While it's probably only a small add-on in terms of silicon area / cost (compare with the equivalent Artix - it's even cheaper - weird world...) it includes 256 kB on-chip memory 512 kB on-chip L2 cache which is 6.1 MBit So we've got already several times the amount of "on-chip floorspace" for the application logic and it'll probably run faster than FPGA logic as it's ASIC technology not reprogrammable logic, typically clocks at 666 MHz (-1) where a non-tuned-/pipelined design on the PL side will probably end up between 100 and 200 MHz. Needless to say, offloading application logic to DRAM or FLASH is trivial where a RTL-only implementation hits the end of the road, somewhat stretchable by buying a bigger chip, maybe partial reconfiguration or biting the bullet and adding a softcore CPU which will be so pathetically slow that the ARM will hop circles around it on one leg. Right, I forgot, the above-mentioned 7010 actually has two of them
  26. 1 point
    Hi, learning a new language well is a major investment => constant cost. Picking an inadequate language / technology / platform is a cost multiplier. Which one hurts more? For a small project the learning effort dominates so you tend to stick with the tools you've got. Try this in a large project and the words "uphill battle" or "deathmarch" will come to life... There's a human component to this question: Say, my local expert has decades of experience with FORTH coding on relay logic - you bet what his recommendation will be, backed by some very quick prototyping within a day or two. And if you have ... >> someone good in verilog or vhdl, ... who is opposed to learning C, you have interesting days ahead... Ultimately, implementing non-critical, sequential functionality in FPGA fabric is a dead end for several reasons. Start with cost - a LUT is much, much more expensive than its functional equivalent in RAM on a processor. Build time is another. The "dead end" may well stretch all the way to success but don't lose sight of it. You will see it clearly when it's right in front of your nose. Now this is highly subjective, but my first guess (knowing nothing about the job, assuming it's not small and not geared towards either side by e.g. performance requirements), I'd predict that implementation on Zynq would take me 3..10x less effort than using HDL only. This may be even worse when requirements change mid-project (again, this is highly subjective but you have considerably more freedom in C to keep things "simple and stupid", use floats where it's not critical, direct access to debug UART, ...). On the other hand, Zynq is a very complex platform and someone needs to act as architect - it may well be that the "someone good in verilog" will get it right first time in a HDL-only design but need architectural iterations on Zynq because the first design round was mainly for learning. Take your pick. Most likely, Zynq is the best choice if you plan medium-/long term, and the (low-volume!) pricing seems quite attractive compared to Artix.
  27. 1 point
    xc6lx45

    hard working FPGA...

    Happy new year
  28. 1 point
    Hello @Zain Zaidi, The JAXC6 and JAXC12 provides 3.3V VCC and are not inputs. The ADC differential input must be with a voltage difference between 0-1V. The input signal for each JXADC channel of the Pmod must be between 0 - 3.3V. So if you connect your XA_N channels to ground, then you must apply to the XA_P channels a voltage between 0-1V. ex : XA1_P= 0.5sin(wt), XA1_N = 0V => XA1_P - XA1_N = 0.5sin(wt) differential input for ADC. XA1_P= 2.5sin(wt), XA1_N = 2.2sin(wt) => XA1_P - XA1_N = 0.3sin(wt) differential input for +ADC. Please read ug480 pages 31-32. If you look into the schematic file of the Basys 3, you will see that the Vp(A12) and Vn(B13) pins are connected to XADCGND.
  29. 1 point
    zygot

    Lowpass Audio Filter

    Don't really have much to add to what @D@nhas mentioned so far. It's been an enjoyable and enlightening read. OCTAVE is a good tool for prototyping and verification. The logic simulator is for RTL and timing verification. For a project like yours I'd start with writing an OCTAVE script that accomplishes what you want to do. The prototype has to be written to represent the algorithm that you intend to implement with digital logic. This means not using keywords that do all of the magic behind the scenes. ( Well, actually a first cut script might do that just to prove the concept..). Before writing the HDL the prototype will reflect your design choices; i.e. data structures and algorithms. Once the prototype is satisfactory you write the HDL implementation. This gets verified with the Vivado Simulator. Be warned that Vivado will be happy to simulate your design using the toplevel entity as the toplevel simulation entity. The result is worthless. You need to write a testbench to exercise your toplevel HDL to test the behaviors that you think need to be tested; that is in simulation your testbench is the toplevel entity.. Testbench code is normally quite different than HDL code meant for synthesis, though it instantiates HDL entities and models written for synthesis. I have written simple behavioral models for external devices as if they were to be synthesized but that another discussion. Your testbench can write output data to a file so that you can compare results to your OCTAVE prototype output. Likely, you are using integer math but often signal processing application use fixed point. Either can suitably be processed with a verification OCTAVE script. If everything has gone right your simulation output, hardware output, and prototype will agree, within reason, with each other. And that's the short course in doing complex programmable logic project for digital, analog or mixed applications. [edit] I forgot to mention that ModelSim or ISIM will let you view std_logic_vectors as analog signals in the waveform viewer if that's appropriate. In theory, I suppose, it would be possible to do all of the steps that I've mentioned in your HDL except for rendering signals, which is a strong part of OCTAVE or SCILAB. Does anyone really want to write their own simulator? I have used the parallel USB interface on my Genesys2, ATLAS, etc. to capture signals from working hardware, using my own C++ application with Digilent Adept API that then writes OCTAVE or SCILAB formatted data files that can then be read into an OCTAVE script for analysis. It's all really quite satisfying.... though if I had the gumption to figure out how to write the rendering part I wouldn't need all of those steps.. perhaps.... [edit1] Yeah, I'm having difficulties letting this go... If anyone from Digilent is reading this thread you should understand that one of the reasons why you've been able to sell me boards is by putting decent PC interfaces on them with useful API libraries for application development. For a number of reasons Ethernet isn't ideal, though I do use a PCIe, FPGA Ethernet PHY equipped board as an alternate route for communications. If all of your boards are going to be ZYNQ based then, unless they have a PCIe or FPGA USB interface directly connected to the logic fabric (USB 3.0 would be nice ) they won't be suitable for my typical development flow.
  30. 1 point
    attila

    Waveform Feature Requests

    Hi @Mr.Spriggs 1. Ok 2. You have timestamp option for SPI/I2C Spy, you can also type in comments in the log fields. Would you need timestamps in other modes too? Could you provide an example for the mentioned numbering? 3. After disconnecting the device you can press Cancel in the device manager. This will leave you with "not connected" warning but the data will remain visible. 4. I will add JTAG interpreter. The OpenOCD support could be done using the WF SDK. Glad to read the positive feedback and thank you for your constructive observations. Merry Christmas
  31. 1 point
    JColvin

    high speed ADC aquisition

    Hi @voltagesurge, I'm not certain when it will be updated (I thought it would've been done yesterday), but I was informed that WaveFormsLive will not be taken down at any point during the update process. I'll let you know when I learn that it becomes updated. Thanks, JColvin
  32. 1 point
    Ana-Maria Balas

    Pmod DA4 with Zedboard

    I'm glad it's working! Have a great day, Ana-Maria
  33. 1 point
    Hi @Lesiastas 1. No, unless we invent time machine You are capturing 5100 samples at 230.4kHz which is 22.135ms. With 744 iterations it takes 16.47sec. The whole process can't be less than this. The data transfer for each capture adds 3-4ms and we end up with ~19sec run time. 2. Instead separate captures you could do continuous capture and data processing.
  34. 1 point
    Hi @cwerner77, I tried to reproduce the problem but unfortunately I could not. You are right though in your assumption, it most likely is a DMA related problem, it expects to receive a certain amount of samples and if the stream is interrupted for some reasons it will stop. If you can record the first time and play back as well then it's most likely not an Audio codec issue. The most likely problem is that the DMA is either in an error state or the IP is no responding to the DMA request. There is a bug in the Demo that if you reprogram the FPGA without resting the board the DMA will hang. Either way I would recommend trying to reset the DMA controller before every playback or record. This would narrow down the search for why it does not work. This can be done with the XAxiDma_Reset() function. I'm also assuming at this point that you did not change anything in the Vivado project or the SDK sources. If you did please let me know, it is unlikely but it might effect the demo. - Ciprian
  35. 1 point
    Hi @Hans Hübner The delay time between trigger and running (or repeats) can be specifies with: dwf.FDwfDigitalOutWaitSet(hdwf, c_double(sec)) The run length can be specified with: dwf.FDwfDigitalOutRunSet(hdwf, c_double(sec)) The number of repeats with: dwf.FDwfDigitalOutRepeatSet(hdwf, c_int(1)) # repeat once
  36. 1 point
    attila

    Running AD2 on Raspberry pi 3 B

    Hi @jody The Analog Discovery is working with Raspberry PI 4 B and many other single board ARM computers. It is not working with Raspberry PI 1, 2, 3 B It looks like there is incompatibility between USB controller and this.
  37. 1 point
    attila

    WaveForms beta download

    3.13.1 digilent.waveforms_beta_v3.13.1_64bit.exe digilent.waveforms_beta_v3.13.1.dmg Added: - Play mode for Digital Discovery in Logic Analyzer - Protocol/UART Save Raw data Fixed: - Pattern Generator preview 3.11.34 digilent.waveforms_beta_v3.11.34_64bit.exe digilent.waveforms_beta_v3.11.34.dmg digilent.waveforms_beta_3.11.34_amd64.deb digilent.waveforms_beta_3.11.34.x86_64.rpm Fixing known bugs. 3.11.33 digilent.waveforms_beta_v3.11.33_64bit.exe digilent.waveforms_beta_v3.11.33.dmg digilent.waveforms_beta_3.11.33_amd64.deb digilent.waveforms_beta_3.11.33.x86_64.rpm Added: - Protocol: - SPI/I2C frequency filter option - SpiFlash (P5Q, M25P16) interpreter option for Spy - Network: - Radian unit for phase plot Fixing known bugs. 3.11.32 digilent.waveforms_beta_v3.11.32_64bit.exe digilent.waveforms_beta_3.11.32_amd64.deb digilent.waveforms_beta_3.11.32.x86_64.rpm Changed: - Protocol: CAN RX re-synchronization for rate tolerance, +/-10% Fixing known bugs. 3.11.31 digilent.waveforms_beta_v3.11.31_64bit.exe digilent.waveforms_beta_v3.11.31.dmg digilent.waveforms_beta_3.11.31_amd64.deb digilent.waveforms_beta_3.11.31.x86_64.rpm Added: - Script: access to windows, like Scope.window.size = [600, 400] Changed: - Logic: - CAN interpreter re-synchronization to increase rate tolerance - CAN trigger ignore substitute remote request bit - Protocol: using Digital Discovery system frequency adjustment Fixes: - Patterns: preview 3.11.30 digilent.waveforms_beta_v3.11.30_64bit.exe digilent.waveforms_beta_v3.11.30.dmg digilent.waveforms_beta_3.11.30_amd64.deb digilent.waveforms_beta_3.11.30.x86_64.rpm Fixing known bugs 3.11.29 digilent.waveforms_beta_v3.11.29_64bit.exe digilent.waveforms_beta_v3.11.29_32bit.exe digilent.waveforms_beta_v3.11.29.dmg digilent.waveforms_beta_3.11.29_amd64.deb digilent.waveforms_beta_3.11.29.x86_64.rpm Fixing known bugs 3.11.28 digilent.waveforms_beta_v3.11.28_64bit.exe digilent.waveforms_beta_3.11.28_amd64.deb digilent.waveforms_beta_3.11.28.x86_64.rpm Added: - Script: - find and replace - clear output button and function - Ctrl+Tab - Save All, Open multiple files 3.11.27 digilent.waveforms_beta_v3.11.27_64bit.exe digilent.waveforms_beta_v3.11.27.dmg digilent.waveforms_beta_3.11.27_amd64.deb digilent.waveforms_beta_3.11.27.x86_64.rpm Fixes and Help update 3.11.26 digilent.waveforms_beta_v3.11.26_64bit.exe digilent.waveforms_beta_v3.11.26.dmg digilent.waveforms_beta_3.11.26_amd64.deb digilent.waveforms_beta_3.11.26.x86_64.rpm Added: - Script: - multiple files for individual scripts or optional include Fixed: - Logic Analyzer: - keep order in Bus signals 3.11.25 digilent.waveforms_beta_v3.11.25_64bit.exe digilent.waveforms_beta_3.11.25_amd64.deb digilent.waveforms_beta_3.11.25.x86_64.rpm Fixed: - Protocol I2C Read with Script 3.11.24 digilent.waveforms_beta_v3.11.24_64bit.exe digilent.waveforms_beta_v3.11.24.dmg digilent.waveforms_beta_3.11.24_amd64.deb digilent.waveforms_beta_3.11.24.x86_64.rpm Added: - Wavegen: - period setting next to frequency Changed: - Protocol: - AVR programmer speed, functions, script access Fixed: - Network Analyzer: - phase averaging 3.11.22 digilent.waveforms_beta_v3.11.22_64bit.exe digilent.waveforms_beta_v3.11.22.dmg (not certified) digilent.waveforms_beta_3.11.22_amd64.deb digilent.waveforms_beta_3.11.22.x86_64.rpm Added: - Logic Analyzer: - SPI interpreter with MOSI/MOSI - HDMI CEC interpreter, trigger on: start, source, destination - Portocol: - AVR programmed: Flash, EEPROM, Fuse, Lock, Calibration - Scope/Logic remembers as default option: Show Attenuation, Acquire Noise, Multiple Scale - Pattern Generator negative delay option Changed: - Pattern Generator: - clock duty round up 3.11.21 digilent.waveforms_beta_v3.11.21_64bit.exe Fixed: - Patterns preview 3.11.20 digilent.waveforms_beta_v3.11.20_64bit.exe Added: - shared workspace list when running multiple applications Fixed: - Digital Discovery trigger position - Patterns preview for pulse - other minor fixes 3.11.19 digilent.waveforms_beta_v3.11.19_64bit.exe Added: - Patterns Delay option for signal/bus Fixed: - Digital Discovery system frequency adjustment 3.11.18 digilent.waveforms_beta_v3.11.18_64bit.exe Fixed: - Supplies for EExplorer and Analog Discovery 1 - Logic Analyzer Inputs for Digital Discovery 3.11.17 digilent.waveforms_beta_v3.11.17_64bit.exe Added: - Spectrum Units: V/vHz, dBm, dBm/vHz, dBm/vMHz - Digital Discovery: - system frequency (Pattern Generator and Logic Analyzer) fine adjustment from Supplies window 3.11.16 digilent.waveforms_beta_v3.11.16_64bit.exe Added: - Spectrum: - Units: dBm, dBmHz, dBmMHz Fixed: - Wavegen: Sync option 3.11.15 digilent.waveforms_beta_v3.11.15_64bit.exe Added: - SDK: - VB/C# ushort and uinteger modes for FDwfDigitalInStatusData/2/Noise/2 - replacing BOOL and BYTE types - manual update - Logic Analyzer: - 100 MHz limit option for Digital Discovery Fixed: - Spectrum: Persistence view axis labels for log scales - SDK: VB/C# wrappers FDwfAnalogInStatusData16 3.11.14 digilent.waveforms_beta_v3.11.14_64bit.exe digilent.waveforms_beta_3.11.14_amd64.deb digilent.waveforms_beta_3.11.14.x86_64.rpm Added: - Script access to Logic Analyzer measurements - System Monitor in Supplies window for AD1, AD2, DD Fixed: - SDK DwfParamOnClose continue running after re-open 3.11.13 digilent.waveforms_beta_v3.11.13_64bit.exe Added: - Network/Impedance Analyzer usage with constant frequency, start=stop - quick measure, cursors, horizontal axis as percentage 3.11.12 digilent.waveforms_beta_v3.11.12_64bit.exe digilent.waveforms_beta_3.11.12_amd64.deb digilent.waveforms_beta_3.11.12.x86_64.rpm Added: - Import data from file option for Spectrum, Network and Impedance Analyzer - trace toolbar width setting for Impedance Analyzer - AnalogOutIn_PlayRecord.py example playing mono and recording to stereo WAV file - FDwfAnalogImpedanceStatusInput phase normalization Fixed: - Analog Discovery 2 USB power monitor false 1A readings - wrong default reference for dBV in Spectrum Analyzer 3.11.11 digilent.waveforms_beta_v3.11.11_64bit.exe Added: - Logic Analyzer Bus interpreter: - either Clock edge option - sampling delay relative to edge - Events view lists sample for each edge when Clock signal is selected 3.11.10 digilent.waveforms_beta_v3.11.10_64bit.exe Added: - Scope scale for XYZ and Spectrogram 3D views - Export EPS image format - support for multiple transfers in Protocol/I2C/Sensor loop function 3.11.9 digilent.waveforms_beta_v3.11.9_64bit.exe Added: - Scope Spectrogram 3D surface view, for 64bit Windows 3.11.8 digilent.waveforms_beta_v3.11.8_64bit.exe digilent.waveforms_beta_v3.11.8.dmg digilent.waveforms_beta_3.11.8_amd64.deb digilent.waveforms_beta_3.11.8.x86_64.rpm Added: - horizontal cursors for Scope/FFT, Spectrum and Impedance Analyzer - cursor delta as decade for logarithmic scales - Scope: - simple Math channel operations: RMS, ATan - LockIn amplifier as Math channel - XYZ 3D graph, for 64bit Windows Fixed: - Scope/Audio/Tempo option 3.11.7 digilent.waveforms_beta_v3.11.7_64bit.exe digilent.waveforms_beta_v3.11.7.dmg digilent.waveforms_beta_3.11.7_amd64.deb digilent.waveforms_beta_3.11.7.x86_64.rpm minor fixes and improvements 3.11.6 digilent.waveforms_beta_v3.11.6_64bit.exe digilent.waveforms_beta_v3.11.6.dmg digilent.waveforms_beta_3.11.6_amd64.deb digilent.waveforms_beta_3.11.6.x86_64.rpm Added: - Protocol - UART Spy - Max Lines option: log limit to prevent application slowdown - Line Wrap option - tooltips for UI controls listing Script access path - application and script Font options - dark theme support for Script 3.11.5 digilent.waveforms_beta_v3.11.5_64bit.exe Added: - Script open/save text file - application argument: -script myscript.txt/js Fixed: - warnings at low record rates 3.11.4 digilent.waveforms_beta_v3.11.4_64bit.exe Added: - Scope: - set/reset zero offset in each channel option - precision option for measurements Fixed: - Script: access to traces and channels from Instrument.Export - unit conversions V to Ṽ, A to à - I2S 32 bit data 3.11.3 digilent.waveforms_beta_v3.11.3_64bit.exe digilent.waveforms_beta_3.11.3_amd64.deb digilent.waveforms_beta_3.11.3.x86_64.rpm Fixes 3.11.2 digilent.waveforms_beta_v3.11.2_64bit.exe digilent.waveforms_beta_3.11.2_amd64.deb digilent.waveforms_beta_3.11.2.x86_64.rpm Added: - Spectrum, Network and Impedance Analyzer store time data when this view is open Fixed: - runscript argument - loading of docked views geometry 3.11.1 digilent.waveforms_beta_v3.11.1_64bit.exe digilent.waveforms_beta_3.11.1_amd64.deb digilent.waveforms_beta_3.11.1.x86_64.rpm Added: - Scope: out of range warning in measurements - Protocol/UART: - support up to 32bit/word - TX/RX format: text, binary, decimal, hex - Wheel Direction option - Logic Analyzer: option to swap previous/next events - Spectrum Analyzer: allowing higher number of BINs for CZT 3.10.7 digilent.waveforms_beta_v3.10.7_64bit.exe Added: - Spectrum: logarithmic magnitude scale for voltage units - Protocol: datetime stamp for SPI/I2C Spy Fixes 3.10.6 digilent.waveforms_beta_v3.10.6_64bit.exe Added: - Scope - access to digital channels from custom math channels - digital measurements view Fixes 3.10.5 digilent.waveforms_beta_v3.10.5_64bit.exe digilent.waveforms_beta_3.10.5_amd64.deb digilent.waveforms_beta_3.10.5.x86_64.rpm Added: - Power Supplies for AD2: tracking, slider, min/max - Logic Analyzer: Measurements - Impedance Analyze: DC mode compensation - SDK VB wrapper, C# wrapper updated Fixed: - EExplorer Wavegen AM/FM index precision for sine 3.10.4 digilent.waveforms_beta_v3.10.4_64bit.exe Fixed: - decimal resolution in Export, Data and Event views 3.10.3 digilent.waveforms_beta_v3.10.3_64bit.exe digilent.waveforms_beta_v3.10.3.dmg digilent.waveforms_beta_3.10.3_amd64.deb digilent.waveforms_beta_3.10.3.x86_64.rpm Added: - UART format option (binary, decimal...) - SDK I2C without clock stretching - SDK examples: Digital_I2c_PmodAcl.py, Digital_I2c_PmodGyro.py - Spectrum Analyzer THDN measurement, THDp and THDNp in percentage units - Impedance Analyzer: - constant current, voltage, custom script for amplitude and resistance control - Option to disable mouse drag and wheel operations on plots - Impedance/Network Analyzer: averaging time - Wavegen: extended frequency option Changed: - special values (none, off) moved to end of the preset list 3.10.2 digilent.waveforms_beta_v3.10.2_64bit.exe digilent.waveforms_beta_v3.10.2_32bit.exe digilent.waveforms_beta_v3.10.2.dmg digilent.waveforms_beta_v3.10.2_mavericks.dmg digilent.waveforms_beta_3.10.2_amd64.deb digilent.waveforms_beta_3.10.2_i386.deb digilent.waveforms_beta_3.10.2.x86_64.rpm digilent.waveforms_beta_3.10.2.i686.rpm Added: - Impedance Analyzer - voltage, current and custom plots - edit Meter list - Resistance mode for Meter, Frequency DC option - step mode in Time view - Network Analyzer - step mode in Time and FFT views - amplitude table and custom function Fixed: - Help minor fix - Protocol SPI and I2C Sensor rate improvement - StaticIO button lock 3.8.22 digilent.waveforms_beta_v3.8.22_64bit.exe digilent.waveforms_beta_v3.8.22_32bit.exe Added: - Impedance differential setup, W1-C1P-DUT-C1N-C2-R-GND 3.8.21 digilent.waveforms_beta_v3.8.21_64bit.exe digilent.waveforms_beta_v3.8.21_32bit.exe digilent.waveforms_beta_v3.8.21.dmg digilent.waveforms_beta_3.8.21_amd64.deb digilent.waveforms_beta_3.8.21_i386.deb digilent.waveforms_beta_3.8.21.x86_64.rpm digilent.waveforms_beta_3.8.21.i686.rpm Added: - data property for impedance/network channels. - Impedance.Resistor.reference property - instruments accessible without index in Script tool like Scope. Fixes... 3.8.20 digilent.waveforms_beta_v3.8.20_64bit.exe Added: - Logger function access to other channels value, average, min, max - Script access to Logger channel set data property, getting average, minimum, maximum Fixed: - Logger Show/Maximum - Script Protocol.I2C.Clear() function 3.8.18 digilent.waveforms_beta_v3.8.18_64bit.exe digilent.waveforms_beta_v3.8.18_32bit.exe digilent.waveforms_beta_v3.8.18.dmg Added: - Network Analyzer - logarithmic scale and percentage unit - spectrum measurements: Carrier, THD+N, THD, HD# - FFT view - Averaging option 3.8.17 digilent.waveforms_beta_v3.8.17_64bit.exe digilent.waveforms_beta_v3.8.17_32bit.exe digilent.waveforms_beta_v3.8.17.dmg digilent.waveforms_beta_3.8.17_amd64.deb digilent.waveforms_beta_3.8.17_i386.deb digilent.waveforms_beta_3.8.17.x86_64.rpm digilent.waveforms_beta_3.8.17.i686.rpm Added: - Scope - persistence support for smooth curve and min/max sampling - custom math - current value in custom math function, can be used for averaging - initialization code for integration purposes - examples - unit presets for: ohm, degree, VAC, AAC - Spectrum - Import/Export samples for Traces - trace information option - Range option to adjust all the scope input ranges - Network and Spectrum - Script support for set magnitude property - Step size and steps per decade settings - Network Analyzer - custom plots: THD, HD2, HD3 - Protocol - I2C/Spy glitch filter based on frequency setting - Device options - On Close: Run (keep running), Stop, Shutdown - USB Power: Always ON or Stop with AUX for AD2 - USB Limit: USB current limitation AD1,2 - Audio Output: AD1, 2 - WaveForms SDK FDwfParamSet/Get, FDwfDeviceParamSet/Get - DwfParamOnClose, DwfParamUsbPower, DwfParamLedBrightness, DwfParamAudioOut, DwfParamUsbLimit - Notes toolbar show/hide option - on/off icon for toggle buttons: supply enable, network analyzer reference... - show entire capture button Changed: - renewed mouse wheel, drag and key (left,right,up,down) operation on plots and axis Fixed: - EExplorer output glitch during first device connection - NI VI crash when initializing without device connected - Scope XY plot 3.8.11 digilent.waveforms_v3.8.11_64bit.exe digilent.waveforms_v3.8.11_32bit.exe digilent.waveforms_v3.8.11.dmg digilent.waveforms_3.8.11_amd64.deb digilent.waveforms_3.8.11_i386.deb digilent.waveforms_3.8.11.x86_64.rpm digilent.waveforms_3.8.11.i686.rpm Added: - Digital Discovery: - LED brightness option - Logic Analyzer - ASCII format for: Bus, SPI, I2C, I2S - Format option for I2C - Logic Analyzer and Patterns - Line Color option - Protocol - Format option for SPI and I2C: Hexadecimal, Decimal, Binary, ASCII - Plot Width option in application settings Changed: - drawing quality improvement for thicker lines - color dialog buttons renamed to Close and Reset 3.8.9 digilent.waveforms_v3.8.9_64bit.exe digilent.waveforms_v3.8.9_32bit.exe digilent.waveforms_v3.8.9.dmg digilent.waveforms_3.8.9_amd64.deb digilent.waveforms_3.8.9_i386.deb digilent.waveforms_3.8.9.x86_64.rpm digilent.waveforms_3.8.9.i686.rpm Added: - WF/Settings/Options: Locale with System or English US regional option, export and import options - SDK: FDwfParamSet/Get function - Scope: measurement resolution Fixed: - minor issues 3.8.8 digilent.waveforms_v3.8.8_64bit.exe digilent.waveforms_v3.8.8_32bit.exe digilent.waveforms_v3.8.8.dmg Added: - WF SDK: - examples updated to be Python v3 compatible - FDwfAnalogImpedance functions for impedance/network analysis - Protocol: CAN receiver filter by ID - Impedance: Export information about amplitude and offset Fixed: - WF SDK: FDwfDigitalSpi functions read MISO/RX 3.8.7 digilent.waveforms_v3.8.7_64bit.exe Fixed: - Scope: save/load of coefficients for custom Math channel filter 3.8.6 digilent.waveforms_v3.8.6_64bit.exe digilent.waveforms_3.8.6_amd64.deb Added: - Export: Wavegen and Supplies information added to Scope, Spectrum, Impedance, Network export comments Fixed: - Script Tool.exec timeout - CAN high polarity option in Protocol tool and WF SDK 3.8.5 digilent.waveforms_v3.8.5_64bit.exe Added - Script functions: getSaveFile, getOpenFile, getDirectory - Scope: multiple scales, zero offset - Notes view - Export options: notes, header as comment - Help tab: floating/undock option, find with highlight Fixed: - Impedance Analyzer frequency scale in export 3.7.22 digilent.waveforms_v3.7.22_64bit.exe digilent.waveforms_v3.7.22_32bit.exe digilent.waveforms_v3.7.22.dmg digilent.waveforms_3.7.22_amd64.deb digilent.waveforms_3.7.22_i386.deb digilent.waveforms_3.7.22.x86_64.rpm digilent.waveforms_3.7.22.i686.rpm Added - Scope/Logic View/Logging picture format - Script: - Export function for instruments - access to Protocol/UART/RX using Receiver, Receive and ReceiveArray functions, SendArray Fixed - Scope edge trigger position for all devices, when only one or two samples are above the threshold - other minor fixes 3.7.21 digilent.waveforms_v3.7.21_64bit.exe digilent.waveforms_v3.7.21_32bit.exe digilent.waveforms_3.7.21_amd64.deb digilent.waveforms_3.7.21_i386.deb digilent.waveforms_3.7.21.x86_64.rpm digilent.waveforms_3.7.21.i686.rpm Added - Wavegen dynamic configuration, adjustments without restarting the generator - SDK support for CAN bus TX, RX - more detail in Spectrum, Network and Impedance Analyzer export comments - import data orientation option Fixed - Network Analyzer Meter export and copy - Data Logger quick measurements - other fixes and optimizations 3.7.19 digilent.waveforms_v3.7.19-2_64bit.exe digilent.waveforms_v3.7.19-2_32bit.exe digilent.waveforms_v3.7.19.dmg digilent.waveforms_3.7.19-2_amd64.deb digilent.waveforms_3.7.19-2_i386.deb digilent.waveforms_3.7.19-2.x86_64.rpm digilent.waveforms_3.7.19-2.i686.rpm Added: - Logic I2S Show channel option - SDK functions for UART, SPI, I2C master and UART receiver Changed: - OS-X rollback to FTDI driver 1.2.2 Fixed: - Impedance Analyzer: save/load of views positions - other fixes and optimizations 3.7.15 digilent.waveforms_v3.7.15_64bit.exe digilent.waveforms_v3.7.15_32bit.exe Added: - Logic Analyzer: position (Nth word) option for SPI trigger on value - Impedance: Nyquist plot; settle time, minimum periods options - Wavegen, Network/Impedance Analyzer: external Amplification option - Tabbed/Docking window switching from main window Changed: - lower frequency limit for Scope, AWG, Network, Impedance Fixed: - 10ns delay in Logic Analyzer Sync and Protocol interface - Sound Card device CPU usage 3.7.14 digilent.waveforms_v3.7.14_64bit.exe digilent.waveforms_v3.7.14_32bit.exe Added: - Protocol I2C ACK/NAK last read byte option Changed: - Windows XP, Vista compatible FTDI driver in 32bit installer 3.7.13 digilent.waveforms_v3.7.13_64bit.exe digilent.waveforms_v3.7.13_32bit.exe digilent.waveforms_v3.7.13.dmg digilent.waveforms_3.7.13_amd64.deb digilent.waveforms_3.7.13_i386.deb digilent.waveforms_3.7.13.x86_64.rpm digilent.waveforms_3.7.13.i686.rpm Added: - Sound Card device of the computer can be used as Scope and Wavegen - Scope sampling clock for Electronics Explorer - Logic Analyzer data compression for recording, for Electronics Explorer - Scope and Wavegen support for 4th device configuration of Analog Discovery 1 & 2 - Scope Logging Repeat option - Scope Audio view: Stereo, Tempo options - MacOS option for application menu 3.7.12-2 digilent.waveforms_v3.7.12-2_64bit.exe Fixed: - Analog Discovery 2 configuration file descriptions 3.7.12 digilent.waveforms_v3.7.12_64bit.exe digilent.waveforms_v3.7.12_32bit.exe Added: - Scope sampling clock under time options, for Analog Discovery 1 & 2. The trigger IOs can be used as sample clock with delay and edge options. - Logic Analyzer data compression for recording, for Analog Discovery 1 & 2 Changed: - Windows installer: - embedded prerequisites: Windows Installer, Visual C++ Redistributable 9 32/64bit, 12 64bit - split installer for 32bit and 64bit WF applications, but the included WF runtime for custom applications support both architectures Fixed: - Logic Analyzer UART frame error threshold 3.7.10 digilent.waveforms_v3.7.10.exe Added: - Spectrum Analyzer Markers Fixed: - SDK Electronics Explorer enumeration - Scope Math channel unit presets 3.7.9 digilent.waveforms_v3.7.9.exe Fixing: - Logic Analyzer Event view double click for signals 3.7.8 digilent.waveforms_v3.7.8.exe Changed: - Impedance Analyzer: - view names - solid line for magnitude Fixed: - Impedance Analyzer admittance |Y| value 3.7.7 digilent.waveforms_v3.7.7.exe Added: - Scope and Logic trigger detector for trigger source Fixed: - warning message when connecting to EExplorer - Patterns trigger on Digital Discovery.