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Showing content with the highest reputation since 05/21/18 in all areas

  1. 2 points
    mohammadhgh

    Zybo z7-20 Zynq Presets

    Hi @Mahesh, As @jpeyron said in the post marked as accepted solution, the Zynq processing system will be configured with the board presets when you first add the Zynq processing system IP core to the block design and run the block automation task from the green message that appears! Just remember to keep the Apply Board Preset option checked as shown in he picture. So this means if you are using the pre-built block design from the example project, a possible solution can be to remove the existing Zynq processing system block and adding a new one!
  2. 1 point
    mohammadhgh

    OpenCL on Zybo

    Hello everyone, I am trying to do some projects on Zybo Z7-20 board with Xilinx SDSoC tool. I added the platform files for the board to the SDSoC and now I am able to compile and run C/C++ codes on the board. However when creating a new project, the OpenCL option is not still available. Is there any way to fix this and compile and run OpenCL code on Zybo board? Thanks
  3. 1 point
    Hi @Michael The syntax highlighter color can't be changed but you could set the text field background color to black by adding the following to the style sheet: QPlainTextEdit{background-color:black;} But with this the blue numbers won't be visible.. Using a bit of red for background looks like this: QPlainTextEdit{background-color:#770000;} With the following you can set the text coloring to black on white: QPlainTextEdit{background-color:white;color:black;}
  4. 1 point
    I was able to get both of the methods I tried yesterday working this morning. Here is a short summary of my solution: 1) Created the block design using the ZYNQ PS with UART_1 enabled and an AXI UARTLite stream connected (see bd.png) 2) Modify the ZYNQ PS to send UART_1 to EMIO pins (see psconfig.png) 3) Modified the xdc file to route the 4 UART signals to the JC PMOD on the Zybo Z7. I also added a switch to turn on an LED for easier debugging (see xdc.png) 4) Set up a FSBL and HelloWorld application projects in SDK (see sdk.png) 5) Redirected stdin/stdout in the BSP settings. I had the FSBL project write out of UART_1 and the HelloWorld project write out the AXI UART and both worked! (see bsp.png) Next up I will be recreating this project on my custom PCB to see where the FSBL fails now that I finally have a UART configured! Thanks for the help again @jpeyron, the forum you linked ended up showing me how to correctly redirect the stdin/stdout ports for the UART
  5. 1 point
    Abhinav Airan

    Pmod GPS not working

    I am using a pmod GPS with a zybo z7-10 board. However, even after running the sample code for the GPS, nothing is being printed on the serial monitor. I'm not entirely sure whether I have connected the pmod right, since there are 6 pins on the GPS but 12 pins on the pmod port. Nowhere has anyone mentioned whether one should connect the pmod GPS on the top six pins or the bottom six pins. Am I doing something wrong here or is there some other problem? I have also attached a picture of my block diagram for reference.
  6. 1 point
    jpeyron

    Pmod GPS not working

    Hi @Abhinav Airan, What version of vivado are you using? Can you attach your project? Are you leaving J2 floating as discussed in the reference manual? thank you, Jon
  7. 1 point
    That platform does not support QEMU. It may be added in a future update. Sorry for the inconvenience.
  8. 1 point
    sbobrowicz

    PYNQ vs ZYBO Z7

    The Zybo Z7-20 will be better for video projects due to the following reasons: 1) Double the DDR bandwidth 2)Double the DDR capacity (mostly relevant for Linux video apps) 3)Fixed HDMI backpowering issue. A monitor attached to the pynq board has to be disconnected every time the board is power cycled because it will back power the Pynq through the HDMI port. This has been fixed in the Zybo Z7. 4) This might not be relevant, but the Zybo Z7 has a Pcam connector for attaching an image sensor directly to the Zynq, which tends to allow for lower latency camera input compared to an HDMI camera 5) This is only relevant if you are planning to use SDSoC and/or reVISION, but Zybo Z7-20 has the best reVISION support of all Digilent boards.
  9. 1 point
    How should the FSM should handle 8 7 0 1 1 8 8 8 7 0 1 7 8 7 0 0 0 1 7? 87011 is not 87017. 8887017 contains 87017. But if 8701 was seen before, the 87017 seen occurs after 8887. 8700017 conatins 870 and 17, but has two extra 0's. I don't think any FSM model allows async inputs that modify state. I've always found that Mealy is the FSM that devs want to write -- even when they write Moore/Mendevev FSMs. Mealy provides next-state/next-value logic -- often avoiding code duplication. But it uses more lines of code so it is rarely used. For this context, VHDL and Verilog are basically the same. This problem doesn't make use of any Verilog/VHDL specific features and both languages handle the general logic design in very similar ways. In terms of using the CE on DFFs vs the CE on BUFGCE, just make sure you constrain the CE signal to the BUFGCE. The CE signal does have a setup/hold similar to a FF and shouldn't be changing close to a clock edge that affects logic. Because designs can have thousands of different CE signals for DFF control sets, but normally only 32 BUFGCE's, the CE feature of the BUFGCE is less used.
  10. 1 point
    I have solved this issue in userspace, below is the code, if someone wants that to work: #include <stdio.h> #include <stdlib.h> #include <fcntl.h> //this system call resets USB OTG char resetCfCard() { int fd; fd = open("sys/bus/usb/devices/usb1/authorized", O_WRONLY); if(fd < 0) { printf("ERROR:\tGPIO Export Failed\n\r"); return 0; } write(fd,"0",1); write(fd,"1",1); close(fd); printf("CF restarted\n\r"); return 1; } //my CF card was of Fat type so this search works char checkCfCard() { FILE *fp; char path[1035]; char cfName[5]; char returnVar; /* Open the command for reading. */ fp = popen("fdisk -l | grep FAT16", "r"); if (fp == NULL) { printf("Failed to run command\n" ); returnVar = 0; } if(fgets(path, sizeof(path)-1, fp) != NULL) { printf("CF Card Present\n"); cfName[0]=path[5]; cfName[1]=path[6]; cfName[2]=path[7]; cfName[3]=path[8]; printf("%s\n", cfName); returnVar = 1; } else { printf("No CF Card\n"); resetCfCard(); returnVar = 0; } /* close */ pclose(fp); return returnVar; } int main( int argc, char *argv[] ) { char inputBytes[10]; int option; printf("Enter 1 to hot swap\n"); while(1) { if(fgets(inputBytes, 10, stdin)) { option = strtol(inputBytes, NULL, 10); if(option==1) { checkCfCard(); } } } return 0; }
  11. 1 point
    Hi @JColvin, I recovered my nexys 3. Thank you. Pablo
  12. 1 point
    theAsker

    Program code on PetaLinux

    Hello! I was able to fix the problem. I only had to add an interrupt to the bloc diagram and also to the device driver. But now I have a now problem. The voltages I read are not correct. And I don't know why. In the attachment you can see my code for testing. Is someone having a plan, why I am having this effect? My driver is here: &xadc_wiz_0 { interrupts = <0 53 4>; interrupt-parent = <0x1>; clocks = <&clkc 15>; xlnx,channels { #address-cells = <1>; #size-cells = <0>; channelJA4@7 { reg = <7>; }; channelJA1@15 { reg = <15>; }; }; }; My constraints are: set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { Vaux14_0_v_p }]; #IO_L21P_T3_DQS_AD14P_35 Sch=JA1_R_p #set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L22P_T3_AD7P_35 Sch=JA2_R_P #set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L24P_T3_AD15P_35 Sch=JA3_R_P set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { Vaux6_0_v_p }]; #IO_L20P_T3_AD6P_35 Sch=JA4_R_P set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { Vaux14_0_v_n }]; #IO_L21N_T3_DQS_AD14N_35 Sch=JA1_R_N #set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L22N_T3_AD7N_35 Sch=JA2_R_N #set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L24N_T3_AD15N_35 Sch=JA3_R_N set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { Vaux6_0_v_n }]; #IO_L20N_T3_AD6N_35 Sch=JA4_R_N The configuration of the XADC is: AXI4Lite, channel_sequencer, AXI4 Stream Interface is false, Timing Mode is continuous, DCLK Frequency is 100MHz, Sequencer Mode is continuous, channel averaging ist none and enable external mux is also false. xadcread.cpp
  13. 1 point
    @jygcm, One of the common beginner mistakes is to create a clock using the logic of the board instead. Since the PLL's won't support a 1Hz clock, this is the only way to make a 1Hz clock. It's also severely flawed. Don't do it. In this case, you have to switch from your 1Hz clock counter to a much faster clock to get your seven segment display working. This will create a "clock domain crossing" (CDC) that you may find difficult to deal with properly. The problem with unmitigated CDC's is that the logic on the other side might not act properly. Worse, it will often act properly in simulation, but then fail in hardware. This will leave you scratching your head and wondering what went wrong. My recommendation for beginners is that they only ever use the system clock. To do this, you'll often want to create a clock enable signal that will be true for one clock per second--such enable signals are only ever one clock wide or this won't work. Inside your clocked logic, you should then have something like: process(clk) begin if (rising_edge(clk)) then if (i_ce) then ----- this is the enable signal --- --- Your logic would go here --- end if; end if; end process; I discuss generating such enable signals in this post from some time ago. Dan P.S. I only just learned VHDL in the last two weeks or so, after having used Verilog for years.
  14. 1 point
    I am working on the Zybo Z7-10 board. My goal is to determine the position and orientation of the FPGA in space at any given instance. For that, I am using a PmodACL2 and PmodGYRO. Now, I need to integrate the accelerations and angular velocities. How do I measure the time at which the Pmods are giving me the data?
  15. 1 point
    Abhinav Airan

    Pmod GPS not working

    @jpeyron, now I removed the if condition for printing in the example code and also printed the gps ping. This is what I'm getting (the data was taken on the terrace of a building) :
  16. 1 point
    Notarobot

    Protocol Development

    xc6Ix45 You are absolutely correct, I should have noticed that you are proposing direct connection. Sorry for bringing unrelated issue.
  17. 1 point
    Abhinav Airan

    Pmod GPS not working

    @jpeyron I have set the baud rate to 115200 and I have installed the board files. I am using Windows 10. I tried printing the ping separately, but it gave a value of -1. Here's the code that I used to do this:
  18. 1 point
    Hi @blacklight, The Arty A7 does not have the HDMI connections to facilitate 2 HDMI inputs and 1 HDMI output. I would suggest the Nexys Video since it has and HDMI in and an HDMI out. The other reason would be that it has an FMC which you can use to facilitate more HDMI inputs such as the FMC-HDMI. thank you, Jon
  19. 1 point
    jpeyron

    SDSoC - couple of questions

    Hi @theUltimateSource, Download the reVISION-Zybo-Z7-20-2017.4-2.zip from here. Once you have unzipped the folder the live io can be found in the samples folder(zybo_z7_20\samples). thank you, Jon
  20. 1 point
    hamster

    Theory of pipelining/paralellism

    I think it is best to view it as a car assembly line. The quickest way to assemble a car is for each team to do their step one after each other - a car will take the combined time of all operations, but you are only building one car at a time. Fine if you a build a single Mclaren F1 race car. The quickest way to assemble lots of cars is a production line. Each team does their step, and then the car moves on to the next team for the next process. Making the first car takes (number of steps) * (length of longest step). But once you have your first car you get another car every (length of longest step). But what if mounting a motor takes five minutes, and the next longest operation takes only three minutes? You can only make one car every five minutes, and the rest of the teams are idle for at least 40% of the time. The solution might be to split mounting the engine into two steps, each taking up to three minutes. Then you can make a car every three minutes. In FPGA-speak, this is pipelining to get the highest clock speed. Big gains are easy at first, but then it gets harder and harder to get any faster, as more parts of the design become critical to the timing of the overall pipeline. The other solution might be to combine pairs of the three minute steps so no step takes longer than 5 minutes. That way you only need half the resources, yet can still produce a car every five minutes... this is the "once you meet your FPGA's timing constraints, then re-balancing the pipeline can save you resources" strategy.
  21. 1 point
    jpeyron

    Theory of pipelining/paralellism

    Hi @Tickstart, It sounds like you are getting the idea of how a basic pipeline works. Here is a good link for explaining risc pipelines. thank you, Jon
  22. 1 point
    Hi @tsakitsan, I found out we have an engineer familiar with LIFA, but that they are out of the office at the moment. I am waiting to hear back from them about your post. thank you, Jon
  23. 1 point
    Side note, to use gpioutil, first run "gpioutil -d" in order to get the needed uio number of the axi GPIO attached to the switches. Then use the following to read switch 0: gpioutil <uio#> 0 2 -i 0
  24. 1 point
    attila

    Analog Discovery 2 vs Raspberry Pi 3

    Hi @Wojtek I have updated the PRi B2 a few months ago and tried different boot/kernel options mentioned on other forums... but nothing helped.
  25. 1 point
    attila

    Analog Discovery 2 vs Raspberry Pi 3

    FTDI USBs like AD, AD2, DD are not working with RPI model B (1,2,3) data packets/bytes are randomly lost. The EExplorer with different USB controller is working fine on these. All devices are working with other embeddeds: Zed, Zybo, BeagleBone… According reports AD is working with the original RPI model A and probably Zero because it has similar chipset/USB. The problem seems to be with FTDI or RPI B USB, library or hardware. You can find such comments regarding RPI problems with other devices too. Unfortunately we couldn't remediate this problem.