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Showing content with the highest reputation since 07/09/19 in Posts

  1. 1 point
    attila

    Scope custom math channel limitations?

    Hi @P. Fiery For such purpose you have the recently added "Initialization" script: For max you can have:
  2. 1 point
    Hi @rigochox, Here is a tutorial on how to add a custom command in LINX. best regards, Jon
  3. 1 point
    jpeyron

    Scope custom math channel limitations?

    Hi @P. Fiery, Welcome to the Digilent Forums! I have moved your thread to a section where more experienced AD2/Waveforms engineers look. best regards, Jon
  4. 1 point
    Hello @jpeyron, I have successfully uploaded this bitstream into the Cmod-A7! :) Writing a simple tutorial now for reference! :)
  5. 1 point
    I want to automate the network analyzer function in waveforms using script. I want to run the network analyzer every 5 minutes for 10 times (with the same settings) on the same RLC circuit and save the results (frequency, gain and phase) to a file. Is there a way to write a script to automate this? thanks rob
  6. 1 point
    jpeyron

    UCF to XDC

    Hi @PoojaN, Thank you for letting us know the the Schmitt_trigger property doesn't work with the 7-series FPGA's best regards, Jon
  7. 1 point
    Hi @john_joe, Glad to hear that you were able to use @hamster's GitHub example. best regards, Jon
  8. 1 point
    Hi @Lesiastas WaveForms application trigger options are similar to the following SDK settings: None = FDwfDigitalInTriggerSourceSet(hdwf, trigsrcNone) Auto = FDwfDigitalInTriggerSourceSet(hdwf, other than trigsrcNone) FDwfDigitalInTriggerAutoTimeoutSet(hdwf, not zero) Normal = FDwfDigitalInTriggerSourceSet(hdwf, other than trigsrcNone) FDwfDigitalInTriggerAutoTimeoutSet(hdwf, zero)
  9. 1 point
    Foudam

    Supply problem in Analog discovery II

    Thanks, I figured out the problem..
  10. 1 point
    Hi @john_joe, Please configure the attached is a Nexys Video Vivado 2017.4 pass through bit file. Does this work for you? Here is the project that generated the bit file. best regards, Jon hdmi_pass_top.bit
  11. 1 point
    jpeyron

    Program Cora Z7 Quad-SPI flash memory

    Hi @eflyzhao, Looking at the Cora Z7 reference manual, Digilent store page and schematic I am not seeing a qspi flash IC on the Cora Z7. Please attach a link to where you are referencing this quote. To boot a project on power up you will need to use the SD. Here is an older tutorial for the Zedboard that is still relevant for the process of making a BOOT.BIN and adding it to the SD card. best regards, Jon
  12. 1 point
    The PICkit 3 (or PKOB on Pro MX7) can only be used, in general, with MPLAB and MPLAB X. The Pro MX7 has a number of options: MPIDE UECIDE (https://www.uecide.org) PlatformIO (https://platformio.org) Arduino IDE with either: the Digilent Core (https://reference.digilentinc.com/learn/software/tutorials/digilent-core-install/start) the chipKIT Core (https://chipkit.net/wiki/index.php?title=ChipKIT_core)
  13. 1 point
    JColvin

    HELP! General questions about OpenLogger

    Hi @CNg33, 1) No, the OpenLogger does not support triggers to start sampling process on an analog input. 2) The OpenLogger doesn't have readable data logging to the SD card at this point in time, though I think 3) No, I do not think there is a way to increase the bandwidth on the OpenLogger since that would require a hardware change and have been informed that even if you multiplexed the ADC channels the bandwidth would not improve. The drop-off after 50 kHz will be quite sharp as it was designed similarly to the OpenScope MZ which also has a sharp roll-off after its 2MHz bandwidth at -3dB as shown on page 45 of the Microchip Masters presentation for the OpenScope MZ here. I haven't done math to figure out what the bandwidth would be at 100 kHz for an OpenLogger, though I do know it's a 2-pole filter that is used on each analog input. Thanks, JColvin
  14. 1 point
    Hi @CNg33, There is not a way to generate a pulse wave on WaveFormsLive; the current waveform options are a sine, triangle, ramp up, square waves, and DC output, with the ability to change the frequency, amplitude, and DC offset as appropriate. As mentioned on this thread, the math function button is not operating correctly; I tried the smaller buffer size that was recommended to me but to no avail. I will let you know when I hear an update on this. Thanks, JColvin
  15. 1 point
    Hi @Foisal Ahmed, We are very sorry for the inconvenience. The PDF version of our reference manual for the basys 3 wasn't updated with the additional information on the WIKI version of the reference manual. This will be fix shortly. The WIKI version of the reference manual here states : "Some Basys 3s have been loaded with a Flash device from Spansion (part number S25FL032), while others have been loaded with a Macronix device (part number MX25L3233FMI-08G). The part loaded on any particular board can be determined by checking the part number and manufacturer logo printed on the Flash IC itself, as seen in the images below." If MX25L3233FMI is not an option in Vivado 2015.1 i would suggest to install a newer version of Vivado. I would suggest Vivado 2017.4 or higher. best regards, Jon
  16. 1 point
    Hello @jpeyron, thanks for the responses. I'll try that the next day as I'm away from the desktop now and will report whether it works or not. 😀
  17. 1 point
    joaquinbvw

    Cora Z7-10 High-Speed Pmods

    Hi zygot, thank you for your response, I appreciate it very much! You're right, just using LVDS is not enough, I was just trying to see if there were maximum speed tests on that interface. At the end I'm planning to use JESD204B for this application, since that interface was design for this type of requirements. The Cora z7 board is just for testing, in the future we will be building our own board for the acquisition system we want to implement. I'm new to this JESD204B protocol/interface but I know that it has a lot of advantages and a lot of Analog Devices high speed ADCs use it, that's why I want to use that. There are some problems using the Cora z7 that I found, it seems that the traces that goes to the PMOD connectors are designed for LVDS, so it is a different impedance matching. I guess if I adapt it well on the other side the JESD204B could be used (it seems that they use CML interfaces for the data lines in this JESD204B protocol). And also you're right on the clock issue, I didn't see if any of the PMOD pins goes to any clock pin, I will have to check this also. We will be doing some tests in the next days, I will post our results here so you can see it and maybe help me with some questions. Thank you again. Cheers, Joaquín
  18. 1 point
    In the Project Settings for the project in which you create your FIFO from the IP Wizard you can select VHDL or Verilog. In ISE there is a separate Core Generator file that does this for your IP. I have a few tips: You definitely need to use Verilog to simulate MIG code You should avoid the AXI interface and just select the Native FIFO interface. This will be much easier to hook up to the Xillybus code. I've done a number of KC705 Xillybus project though without using the DDR for storage. Start off by building the Xillybus project. After you think that you understand how his design works try creating a custom interface to provide some positive feedback on how well you do. After you are comfortable with the Xillybus then try an add the MIG DDR interface. There will be a lot of clocks involved and timing closure will start becoming tricky. If you try and jump to a final project it likely will take longer than if you progress through integrating interfaces in an orderly step by step manner. Having a verilog model for the DDR memory certainly helps with simulation. After creating a MIG DDR interface it is not as simple as hooking up some FIFOs and reading data. You will need to create your own state machines to interact with your code and the DDR interface FIFOs to perform external read and write operations. Regardless of any experience you might have developing FPGA DDR designs with other vendors devices and tools I suggest that you read through all of the relevant Xilinx literature. This includes IP documentation, Vivado simulation, etc. Jumping off a cliff into a pool is a lot safer if you know what's waiting for you once you hit the water....
  19. 1 point
    Bogdan50

    WaveForms Live Math Function Not Working

    Don't know why but the Math Function at the lower left of graph does not work and just locks up the browser. Tried 3 browsers: Firefox Developer, Chrom and Edge. All on Windows 10. It works though when I select a Simulated device. I guess I am doing something wrong. Does it work with the captured data?
  20. 1 point
    Hi @john_joe, Typically having both the RGB2DVI and the Clocking wizard set to PLL causes a Unroutable Placement error in vivado. If vivado allows you to have both the clocking wizard and the RGB2DVI set to PLL then your project should be fine. Does the pass though work with this project? best regards, Jon
  21. 1 point
    JColvin

    Pmod wifi

    Hi @kavya@iiitn, You need to keep your router set to DHCP; this should be the recommend settings of your router as per it's manual here, rather than a static IP; the example project we provide with our Pmod WiFi determines and sets up the IP address and the connectivity for you; you only need to provide the SSID and password to the WiFi -- this is described in this post here. Additionally, in your earlier post showing your router and Zedboard, it looked like you both 1V0 and 2V5 selected with jumpers on the VADJ select in the bottom right corner of the board near the 5 push buttons. This will cause conflicting voltages on the Zedboard and likely damage it, particularly on the FMC. I would also not recommend showing all of your router settings (I removed the picture) as that can provide all of the details a hacker needs to access your internet. Thanks, JColvin
  22. 1 point
    Hi @Lesiastas You could change the declaration in the wrapper to UInt16: <DllImport("dwf.dll", EntryPoint:="FDwfDigitalInStatusData", CallingConvention:=CallingConvention.Cdecl)> Function FDwfDigitalInStatusData(ByVal hdwf As Integer, <MarshalAs(UnmanagedType.LPArray)> rgData() As UInt16, ByVal countOfDataBytes As Integer) As Integer End Function And use as: Dim samples = 1000 Dim rgwData(samples) As UInt16 FDwfDigitalInStatusData(hdwf, rgwData, 2 * samples)
  23. 1 point
    Hi @john_joe, Welcome to the Digilent Forums! Does the ILA error cause the generate bitstream to fail? Are you able to get the Nexys Video HDMI project working? best regards, Jon
  24. 1 point
    Hi @Lesiastas, I moved your thread to a section where more experience Waveforms/AD2 engineers look. Also here is a forum thread that should be helpful for you. best regards, Jon
  25. 1 point
    Bianca

    ARTY A7-35 REV E.

    Hi @Djsnzheusj, The XDC for D.0 will work. We made a spin for the power supplies. Nothing in the FPGA configuration was affected by the new PCB spin. Regards, Bianca
  26. 1 point
    Chris Burrows

    Embedded Project Oberon OS

    We have just released v7.0 of Astrobe for RISC5. The initial release supports both the Artix-7 and Spartan-7 FPGA devices as used on the Digilent Arty development boards. New hardware capabilities include Arduino shield-compatible SPI and I2C interfaces and support for up to 32 GPIO pins. See the announcement on the Astrobe forum for links to a full summary of What’s New and information on how to obtain a free copy:
  27. 1 point
    JColvin

    WaveForms Live Math Function Not Working

    Hi @Bogdan50, I have asked our firmware engineer about this; I was also not able to get the math function to work with the OpenLogger. Thanks, JColvin
  28. 1 point
    Hi @PoojaN, Welcome to the digilent Forums! 1) Are you programming the QSPI flash through SDK or through Vivado? 2) Here is the Arty Programming Guide and the How To Store Your SDK Project in SPI Flash that should help depending on what type of project you are using. best regards, Jon
  29. 1 point
    Hi, check your options for bitstream generation. There is a clock frequency setting that determines the time it takes to move the data from flash to FPGA.
  30. 1 point
    Thanks for trying to help me! Unfortunately I'm just a dumb end-user of the openlogger, not a software developer, so most of your advice has gone over my head! Not to say I am not going to try it out - I do have Ubuntu on my computer, so I'll have a crack. I'm hoping @digilent will come to the party and provide openlogger buyers with something that lets us get to our logged data without us having to learn how to handle snakes, or to learn the difference between batch and shell scripts 😁...
  31. 1 point
    Bianca

    I want to blink LED

    Hello hilarikas, I just checked again your files and saw some things that I missed last time I looked. I saw that you tried to assign your clock signal and one led. Unfortunately you confused the XDC file with the UCF file. Both UCF and XDC are contraints files. UCF is used with ISE and XDC is used with Vivado. The main difference between them is the syntax. What you tried to do was writing in the XDC the with the syntax from UCF. It won't work. XDC syntax for the clock: ## Clock Signal #set_property -dict { PACKAGE_PIN AD11 IOSTANDARD LVDS } [get_ports { sysclk_n }]; #IO_L12N_T1_MRCC_33 Sch=sysclk_n #set_property -dict { PACKAGE_PIN AD12 IOSTANDARD LVDS } [get_ports { sysclk_p }]; #IO_L12P_T1_MRCC_33 Sch=sysclk_p UCF syntax for the clock: ## Clock signal #NET "clk" LOC = "E3" | IOSTANDARD = "LVCMOS33"; (taken from Nexys4 UCF) What you tried to do: ##NET "refclk" LOC = "AD11"; Then, you cannot use the Genesys2 clock like this. It's a differential clock and you'll have to use a primitive to instantiate it. As you can see you have a sysclk_n and a sysclk_p. You'll have to use IBUFG primitive. you can find more information in Xilinx documentation. This primitive will allow you to use the clock. The primitive looks like this: IBUFDS_inst : IBUFGDS generic map ( DIFF_TERM => FALSE, -- Differential Termination IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards IOSTANDARD => "DEFAULT") port map ( O => O, -- Buffer output I => I, -- Diff_p buffer input (connect directly to top-level port) IB => IB -- Diff_n buffer input (connect directly to top-level port) ); Where, O is a clock signal you will declare as standard_logic. (Not Port, but Signal) in your case you wanted refclk and I and IB are the two parts of the differential clock. it would look like this: IBUFDS_inst : IBUFGDS generic map ( DIFF_TERM => FALSE, -- Differential Termination IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards IOSTANDARD => "DEFAULT") port map ( O => refclk, -- Buffer output I => sysclk_p, -- Diff_p buffer input (connect directly to top-level port) IB => sysclk_n -- Diff_n buffer input (connect directly to top-level port) ); After this when your code and your XDC are ready synthesize your project. Don't generate bitstream just synthesize then open the synthesized design. You'll have to assign that clock to the design, in order to know that is a clock signal. Attached to this post is a word document with a tutorial on how to assign the clock. At the end of this reload your XDC file. You'll have an option on the top where you have the page open and if all works well you'll see that it will add an extra line on the bottom of your XDC. Mine looks like this: create_clock -period 5.000 -name sysclk_p -waveform {0.000 2.500} [get_ports sysclk_p] After you finished, generate your bitstream and put it on the board. Attached here you'll also find an example of a working code that counts on the leds and the correct uncommented XDC file. Best regads, Bianca Asign Clock.docx LED.vhd Genesys2_H.xdc