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Showing content with the highest reputation since 09/14/20 in Posts

  1. 1 point
    Hi @painterguy1995, I believe (it's been awhile) that the needed drivers either come with the Arduino IDE or are part of the Digilent Core for the Arduino IDE (installation instructions available on our Wiki here: https://reference.digilentinc.com/learn/software/tutorials/digilent-core-install/start). *Edit: I checked and the necessary drivers are included with the Digilent Core. The instructions say to use Arduino 1.6.9, but I have used the same core up through 1.8.12 without any issues or needing to install drivers; Windows . My understanding is that MPIDE has been depreciated and is no longer used. Let me know if you have any questions. Thanks, JColvin
  2. 1 point
    @[email protected], I just got an email from a well known high end FPGA board vendor claiming 200 Gbps Digital IO. Yes this is far fetched but I had to know why a respected vendor would make such a claim. The answer turns out to be OCuLink. No, I was unaware that this is a thing but a google search returns plenty of hits. Some variants of the RfSoC have multiple lanes of transceivers that run at 25 Gbps. Connect 8 of these transceivers to an interface and you have 200 Gbps of something. Calling that something digital IO is beyond misleading. PCIe transceivers aren't like Select IO pins. My PCs have spare 4 lane Gen 3 (8 Gbps) slots. What do you think my chances of using one for GPIO are? BTW, finding OCuLink hits for things that you can connect to your 200 Gbps FPGA board interface is a different proposition. Beware of marketing claims. They can take a kernel of truth and turn it into a fantastical claim... unless you understand the context. The FPGA vendor claims that it can use this interface to connect two boards with a very high speed interface. Now that's believable but practical sustained data rates would likely be no where near 25 GB/s. [edit] It's curious that these beasts have such limited PL logic clocking support given the capability of the PS hard logic and the transceivers.
  3. 1 point
    Hi @Frank.Muenzner 2. I'm working on implementing such recording for the VIs Hope to give you a version with this in a few days.
  4. 1 point
    @xc6lx45, Spoiler Alert! This is one of those ZYNQ beasts with onboard ADC and DAC converters. The issue is essentially a lack of documentation and transparency on the part of Xilinx on how their devices work. My earlier posts to this thread shows that I didn't get it at first either.
  5. 1 point
    A sneaky way out of it is to use n (e.g. n=8 ) generators in parallel, with a phase offset of 1/n sample. This is literally a "polyphase" approach. For high-end fast DA / AD converters you won't be able to operate at the converter's clock rate on an FPGA so it needs to be split on multiple, parallel lanes anyway.
  6. 1 point
    zygot

    SERDES doesn't work as expected

    That's not how TMDS termination works. Read the material that I've suggested. Do not try and connect custom hardware or wires to your board unless you understand supported IOSTANDARD specifications and terminations for your device and bank Vccio. TMDS_33 termination resistors are external. The FPGA IO PULL_UP and PULL_DOWN are not suitable. Again, you need to do your homework before starting any experimentation. You are not likely to find what you are looking for using Xilinx IP. and the board design flow. You will have better fortunes if you learn Verilog or VHDL. The Digilent staff are keen on the board design approach perhaps you will be lucky and one of them will have some suggestions. But really, the appropriate thing to do here is write your own HDL to experiment with IOSERDES.
  7. 1 point
    If this is your first FPGA project you jumped into the deep end of the pool. The UltraScale devices are a lot more complicated than the normal devices used in products normally discussed in the Digilent Forum and the key information tends to be a lot more difficult to tease out. The first thing that you want to do is try to at least build the demo projects that come with your development kit. You might not be able to run them due to odd requirements. This is what I ran into with the ZCU106 TRD. But, with a bit modification of the tcl I did manage to build the demo.
  8. 1 point
    Hi, it sounds very unlikely. Now it does happen that boards fail (which is very rarely related to the FPGA itself, but more often unreliable USB cables, connectors, failing voltage regulators, PCB microcracks and, did I mention, unreliable USB cables) but usually, the problem is somewhere else. The FPGA GPIO circuitry is very robust. Unless there is an external power source involved outside the bank voltage range, I doubt you'd manage to damage it even if you tried. I guess we all know those panic moments, like "oh no I've bricked / toasted the board" and then you have a coffee, reboot the PC and everything is well again.
  9. 1 point
    Hi @S.Kamath, Yes, you can use our guide here, https://reference.digilentinc.com/learn/programmable-logic/tutorials/2020.1/getting-started-with-ipi, for using the Zynq processor to control an LED on a Zynq based board such as the Cora Z7-07S. Let me know if you have any questions. Thanks, JColvin
  10. 1 point
    Shun

    Using script with Wavegen Modulation on AD2

    Awesome, thanks Attila! It's exactly what I wanted to do!
  11. 1 point
    attila

    Using script with Wavegen Modulation on AD2

    Hi @Shun
  12. 1 point
    Kier

    SPI Decode In Logic Analyzer Is Incomplete

    Hi @attila Thank you very much for the quick, proactive support. The beta fixed the problem! Kier.