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  1. 2 points
    JColvin

    Read from MicroSD in HDL, Write on PC

    Hi @dcc, I'm not certain how you are verifying that the HDL is writing to and then reading back from the SD card in a normal formatting style, but in general FAT32 is a widely used format for SD cards that has existing material for it. I am uncertain why you are using a special tool to write to the SD card though; from what I can tell the tool is Windows compatible, so why not just use the Notepad program which comes with Windows and save a .txt file with the data you are interested in reading to the SD card or just using Windows Explorer (the file manager) to move the file of interest onto the SD card? If you do have a header in your file, you will need to take account for that, though I do not know what you mean by "random file" in this case. Thanks, JColvin
  2. 2 points
    SeanS

    Genesys 2 DDR Constraints

    Hi JColvin, I am definitely not using ISE. I think JPeyron had it correctly. I didn't have my board.Repopaths variable set and so the project wasn't finding the board files. Once I set this variable as suggested, the pin mapping and IO types were auto populated as expected. Kudos, Sean
  3. 2 points
    @jpeyron @D@n I fixed the bug in my SPI Flash controller design. Now I can read from Flash memory.
  4. 2 points
    Hi @Blake, I was struggling with the same problem. In Adam's project is mistake which result is an FMC-HDMI module is not recognizable by other devices. The reason for that is not sending EDID at all. The cause of this situation is wrong initialized EDID map. In Adams example EDID is initialized by: but the correct way is: the body of iic_write2 is from LK example: By the way, in LucasKandle example initialization is done in same way as in Adam's example so is the reason why it not worked in your case. I hope it will helps. If you want I will post my working code for a ZedBoard with FMC-HDMI when I clean it because at the moment is kind of messy.
  5. 1 point
    Hi @Ciprian, After some time, I managed to solve this issue. In fact, It was a problem in the hardware and device tree configuration. I discovered it when probing with another example project named Zybo-hdmi-out (https://github.com/Digilent/Zybo-hdmi-out). However, as this project is for a previous version of Vivado, I tested with Vivado 2017.4. Surprisingly, it worked fine but with another pixel-format in the device tree. The Zybo-base-linux project which I used, has a pixel format in DRM device tree configuration set to "rgb888", however, for the Zybo-hdmi-out, it displayed correctly with pixel-format "xrgb8888". If I use other pixel formats, no output is displayed in both cases. Going deep into the configuration of both projects, I discovered that there are some differences in the VDMA and Subset converter settings, which changed to the configuration in Zybo-hdmi-out, solves the problem of colors and rendering, considering also a pixel format in the devicetree equal to "xrgb8888". I attached the images of both configurations. In addition to this, I managed to update the design for the Vivado version I use (2018.2) with no more differences that a change in the AXI memory interconnect replaced by the AXI Smart connect in the newer version, which is added automatically when using Vivado autoconnect tool for the VDMA block. Hope this information could help others which run in the same issue. Thanks for your help. Luighi Vitón
  6. 1 point
    if you can bring it up once in Vivado HW manager (maybe with the help of an external +5 V supply), you might be able to erase the flash. If not, you may be able to prevent loading the bitstream from flash e.g. by pulling INIT_B low (R32 is on the bottom of the board, its label slightly below the CE mark). See https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf "INIT_B can externally be held Low during power-up to stall the power-on configuration sequence at the end of the initialization process. When a High is detected at the INIT_B input after the initialization process, the FPGA proceeds with the remainder of the configuration sequence dictated by the M[2:0] pin settings.""
  7. 1 point
    well, by default your signal is between 0 V and Vref. The opamp circuit has a gain of 2 (range 0.. 2 VRef) but subtracts a constant VRef (range now -VRef..Vref). It'll just shift the waveform on the scope, and double its AC magnitude.
  8. 1 point
    Let me offer a suggestion to all newbies, regardless of how smart you are, before trying to do FPGA development. Read all of the user guides for the FPGA device resources that you are likely to be using. These will include the SelectIO, Clocking, CLB , and memory guides at a minimum. [edit] also read the AC switching part of the device data sheet. Like it or not what you are doing in FPGA development is digital design and you need to have a sense of how design decisions affect timing. Read the Vivado user guides for design entry, constraints, simulation, timing closure, and debugging. Understand that even though various Zynq devices are based on certain FPGA families the documentation tends to be unique for these devices. You will be overwhelmed with all of the 'basic' information. Spend a week or so running though all of the basic documentation, spending more time on specific topics each read-through. The object isn't to memorize or understand everything but to get a general feel for how Xilinx presents its information. You can also learn stuff that you will miss in specific IP documentation by using the simulation, but only if you are careful to read all of the simulator messages. This is complicated stuff and the tools, even when they behave as described in the reference material is even more complicated. The purpose of doing this is to get a general feel for how the devices work and specific use limitations and how the tools work. It will take a year or so before you start becoming competent at it if you are a normal human.
  9. 1 point
    @askhunter Tip if you want to notify someone that you are responding to a post type @and the first few letters of their username. A selection of usernames will appear in a popup window to choose from. If you just type @ and the whole name you won't get the desired result. I confess that I'm not an expert on using the features of this site but I did figure out this one. As to understanding all of the Xilinx documentation what yo are doing is correct. Speed-read though a document to get a general sense of what's being presented and don't worry about the things that you don't grasp. Just being familiar with what information is where will help with a specific question later. The DSP48E is a very complicated piece of hardware. You only understand how complicated by trying to instantiate it as a UNISIM component to implement a particular algorithm. I've done this and it take time. You understand by doing; one step at a time. In your case I'm assuming that you are starting with someone else's code and trying to modify it. This approach takes a difficult task and turns it into an extremely difficult task. [edit] Vivado uses the multipliers in a seamless way when you specify a multiply in your HDL code. It takes care of a lot of little details, such as that the multipliers are signed 18-bit. There are a LOT of options with the DSP48E blocks. Once you start making decisions for Vivado, by say, using the use_dsp attribute in your code you are taking on responsibility for more of those details... so you had better understand how the DSP48E blocks work. Trust me, even after you have figured out all of the necessary behaviors of the DSP48E blocks it doesn't get easier as you will have to contend with routing issues that might dramatically reduce your data rates. This is a general rule for using FPGA device resources. You can use the IP wizards to help construct a component that's useful for your needs or do it yourself in HDL code and assume the responsibility for getting all of the details and constraints right.
  10. 1 point
    @askhunter I suggest that you read UG479 to see what the DSP48E blocks do. Then read UG901 to see what the use_dsp attributes do. Reading the recipe doesn't always help improve the cooking but it never hurts. A long time ago having signed multipliers in hardware was a big deal for FPGA developers. For the past decade or so these have become integrated into more complicated and useful 'DSP' blocks. The DSP nomenclature is a holdover from the days, long before IEEE floating point hardware was available, when having a fast multiplier in hardware meant that you could do some fun stuff in a micro-controller that you couldn't do with software routines. These days the lines are blurry. Most FPGA devices have some really fast hardware features, block ram and DSP blocks ( depending on how they are used ) being the most useful for grinding out mathematical algorithms. By the way, the DSP blocks can be useful for more than multiply-add operations.
  11. 1 point
    D@n

    Read from MicroSD in HDL, Write on PC

    @dcc, This is really the backwards way to get something like this going. You should be proving your design in simulation before jumping into a design on hardware. Let me offer you an alternative. Here is a Verilog driver for talking to an SD card using SPI. If you have already chosen to use the AXI bus, you can find an AXI-lite to WB bridge here that will allow you to talk to this core. Even if you already have a driver you like, this documentation for this one describes how to set up the SD card to where you can talk to it, and provides examples of how to read and write sectors. Even better, there's a piece of C++ code which can be used as a simulator with Verilator. (Not sure if this would work with MicroBlaze or not.) You can then use Linux tools, such as mkfatfs and such, to create a file with a FAT format that you can use as a "simulated" SD card. When the simulation isn't running, you can mount the card on your system and check out/modify the files, and so know that things will work (based upon your experience with simulation) once you finally switch to hardware. Indeed, if you are willing to accept the risks, you could even interact with your SD card from the simulation environment itself. If you want an example of a set up that would control the SD card interface from a ZipCPU, you can check out the ZBasic repository which has such a simulation integrated into it. Indeed, there's even an sdtest.c program that can be used for that purpose. As for reading and comprehending the FAT filesystem, there's a FATFS repository that is supposedly good for use with embedded software. I haven't tried it, so I can't comment upon it that much. Alternatively, if you can control how the file system is laid out, you should be able to place a file of (nearly) arbitrary length a couple of sectors into the FS, and force the file to be use contiguous sectors. If you do that, then you've dealt with the most complicated parts about reading from the SD card. Just my two cents, and some thoughts and ideas along the way. Dan
  12. 1 point
    JColvin

    OpenLogger ADC resolution + exporting

    Hi @sgrobler, Our design engineer who designed the OpenLogger did an end-to-end analysis to determine the end number of bits of the OpenLogger. This is what they ended up doing in a summarized fashion: <start> They sampled 3 AAA battery inputs to the SD card at 250 kS/s and set the OpenLogger sample rate to 125 kS/s and then took 4096 samples; they then took the raw data stored on the SD card and converted it to a CSV file and exported the data for processing. Their Agilent scope read the battery pack at 4.61538 V and as they later found from FFT results the OpenLogger read 4.616605445 V, leading to a 0.001226445 V or ~1.2mV difference, which is presuming the Agilent is perfect (which it is not), but it was nice to see that the values worked out so closely. They calculated the RMS value of the full 4096 samples in both the time domain and using Parseval's theorem in the frequency domain as well, both of which came up with the same RMS value of 4616.606689 mV, which is very close to the DC battery voltage of 4616 mV. Because RMS is the same as DC voltage, this gives the previously mentioned DC value of 4.616605445 V. They can then remove the DC component from the total RMS value to find the remaining energy (the total noise, including analog, sampling, and quantization noise) of the OpenLogger from end-to-end. With the input range of +/- 10V input, this produces an RMS noise of 1.5mV. At the ADC input, there is a 3V reference and the analog input front end attenuates the input by a factor of 0.1392, so the 1.5mV noise on the OpenLogger is 0.2088mV at the ADC. With the 16 bits (65536 LSBs) over 3V, 0.0002088V translates to ~4.56 LSBs of noise. The ENOB is a power of 2, so log(4.56)/log(2) results in 2.189 bits, giving us a final ENOB of 16 - 2.189 = ~13.8 bits. Note though that this ENOB of 13.8 bits is based on system noise and not dynamic range, so for non-DC inputs (which will likely be measured at some point) the end number of bits is not easily determined. The datasheet for the ADC used in the OpenLogger (link) shows that the ADC itself gives an ENOB of about 14.5 bits at DC voltage (so the 13.8 bits is within that range), but at high frequencies, this of course rolls off to lower ENOB at higher frequency inputs. Thus, they cannot fully predict what the compound ENOB would be over the dynamic range, but they suspect it all mixes together and is 1 or 1.5 bits lower than the ADC ENOB response. </end> Let me know if you have questions or would like to see the non-abbreviated version of his analysis. Thanks, JColvin
  13. 1 point
    bogdan.deac

    OpenCV and Pcam5-c

    Hi @Esti.A, If you clone the repo you obtain the "source code" for the platform and you have to generate the platform by yourself. This is a time consuming and complicated task and is not recommended if you do not understand SDSoC very well. I advise you to download the last SDSoC platform release from here. You will obtain a zip file that contains the SDSoC platform already build. After that, you can follow these steps to create your first project.
  14. 1 point
    FPGAMaster

    CMOD A7 Schematic missing stuff

    Thank you Jon... I got the PM and will follow up as you suggested.
  15. 1 point
    Hi, I think a UART is the least effort. Parsing ASCII hex data in a state machine is easy and intuitive to debug, at the price of 50 % throughput. If you like, you can have a look at my busbridge3 project here, goes up to 30 MBit/second. The example RTL includes very simple bus logic with a few registers, so it's fairly easy to connect an own design. Note, it's not meant for AXI, microblaze or the like as it occupies the USB end of the JTAG port. In theory, it should work on any Artix & FTDI board as it doesn't any LOC-constrained pins.
  16. 1 point
    bogdan.deac

    OpenCV and Pcam5-c

    Hi @Esti.A, SDx, which includes SDSoC (Software Defined System on Chip), is a development environment that allows you to develop a computer vision application, in your case, using C/C++ and OpenCV library. The target of SDx-built applications are Xilinx systems on chip (SoC) (Zynq-7000 or Zynq Ultrascale+). Xilinx SoC architecture has two main components: ARM processor (single or multi core) named Processing System (PS) and FPGA, named Programmable Logic (PL). Using SDx to build an application for SoC allows you to choose which functions from your algorithm are executed in PS and which ones are executed in PL. SDx will generate all data movers and dependencies that you need to move data between PS, DDR memory and PL. The PL is suitable for operations that can be easily executed in parallel. So if you are going to choose a median filter function to be executed in PL, instead of PS, you will obtain a better throughput from your system. As you said, you can use OpenCV to develop your application. You have to take into account that OpenCV library was developed with CPU architecture in mind. So the library was designed to obtain the best performance on some specific CPU architectures (x86-64, ARM, etc.). If you are trying to accelerate an OpenCV function in PL using SDx you will obtain a poor performance. To overcome this issue, Xilinx has developed xfopencv, which is a subset if OpenCV library functions. The functionalities of xfopecv functions and OpenCV functions are the same but the xfopencv functions are implemented having FPGA architecture in mind. xfopencv was developed in C/C++ following some coding guideline. When you are building a project, the C/C++ code is given as input to Xilinx HLS (High Level Synthesis) tool that will convert it to HDL (Hardware Description Language) that will be synthetized for FPGA. The above mentioned coding guideline provides information about how to write C/C++ code that will be implemented efficiently in FPGA. To have a better understanding on xfopencv consult this documentation. So SDx helps you to obtain a better performance by offloading PS and by taking advantage of parallel execution capabilities of PL. Have a look on SDSoC documentation. For more details check this. An SoC is a complex system composed by a Zynq (ARM + FPGA), DDR memory and many types of peripherals. Above those, one can run a Linux distribution (usually Petalinux, from Xilinx) and above the Linux distribution, the user application will run. The user application may access the DDR memory and different types of peripherals (PCam in your case). Also, it may accelerate some functions in FPGA to obtain a better performance. To simplify the development pipeline Xilinx provides an abstract way to interact with, named SDSoC platform. SDSoC platform has two components: Software Component and Hardware Component that describes the system from the hardware to the operating system. Your application will interact with this platform. You are not supposed to know all details about this platform. This was the idea, to abstract things. Usually, the SDSoC platforms are provided by the SoC development boards providers, like Digilent. All you have to do is to download the last SDSoC platform release from github. You have to use SDx 2017.4. You don't have to build your own SDSoC platform. This is a complex task. You can follow these steps in order to build your first project that will use PCam and Zybo Z7 board. The interaction between PCam and the user application is done in the following way: there is an IP in FPGA that acquires live video stream from the camera, the video stream is written into DDR memory. This pipeline is abstracted by the SDSoC platform. The user application can access the video frames by Video4Linux (V4L2). The Live I/O for PCam demo shows you how to do this. I suggest you to read the proposed documentation to obtain a basic knowledge needed for SDSoC projects development. Best regards, Bogdan D.
  17. 1 point
    jpeyron

    Vivado free for Artix-7?

    Hi @TerryS, Thank you for posting how you got to the legacy content. I will pass this on to our content team. We will still have this content accessible since there are a wide array of people that use different versions of vivado. The legacy content is accurate for earlier versions of Vivado/SDK. best regards, Jon
  18. 1 point
    jpeyron

    Arty A7 USB mechanical USB problem

    Hi @acm45, I reached out to one of our design engineers about this thread. They responded that: "there are no series resistors between the D+ and D- pins of the connector and the those pins on the FT2232HQ. I think it would be very difficult to solder the D+ and D- wires directly to pins of the USB controller. My suggestion is to purchase an external JTAG programmer/debugger (JTAG-HS2) and attach it to header J8." best regards, Jon
  19. 1 point
    Hi @learni07, Can you please check the baud rate from Tera-Term? For this, click on Setup->Serial port and check Baud Rate down-menu. It has to be 115200. Best Regards, Bogdan Vanca
  20. 1 point
    jpeyron

    OpenCV and Pcam5-c

    Hi @Esti.A, I would suggest using the version of Vivado/SDK/Petalinux that the project was made in and for. If you are typing to update an existing project to an newer version there are alot of potential issues that could occur. We do not have a tutorial on how to do this. I would suggest looking through the xilinx petalinux documentation like the petalinux wiki. Here is a forum thread that might be helpful as well. best regards, Jon
  21. 1 point
    jpeyron

    Cora Z7 Basic IO example problem

    Hi @Lost_In_Space, Welcome to the Digilent Forums! Please download Adept 2. 1) Can Adept 2 recognize the Cora Z7? Please attach screen shots of the Adept 2 text when the Cora Z7 is connected. 2) Are you using Linux? Windows? 3) Is the Mode Jumper JP2 set to JTAG? 4) How are you powering the Cora Z7? USB or external power source? best regards, Jon
  22. 1 point
    Hi @Phil_D It can be done like this: const NAVG = 10 Spectrum.run() var sum = [] for(var acq = 1; acq <= NAVG && Spectrum.wait(); acq++){ var hz = Spectrum.Channel1.dataRate // WF v3.11.2 { // padding in Trace 5 var rg = Spectrum.Channel1.data // channel 1 time domain data var c = rg.length var t = rg[c-1] // last sample for(var i = 0; i < c; i++) rg.push(t) // 2x padding Spectrum.Trace5.setSamples(rg, hz) } { // averaging in Trace 6 var rg = Spectrum.Trace5.magnitude if(acq==1){ sum = rg; Spectrum.Trace6.Clone(Spectrum.Trace5) }else{ rg.forEach(function(v,i){ sum[i] += v;}) // sum sum.forEach(function(v,i){ rg[i] = v/acq;}) // average Spectrum.Trace6.setMagnitude(rg, 0, hz/2) } } } Spectrum.stop()
  23. 1 point
    Hi jon! I have resolved that issue using a case statement to assign the bits instead of using the - operator.Hence I have deleted the post also immediately.where you still able to see it?
  24. 1 point
    Hi @Phil_D I just notice that the -runscript is only working when the instruments are in docking window mode. My bad, runscript is only looking for docked Script window. It will be fixed in the next software version.
  25. 1 point
    Hi @Phil_D There is no zero padding option but it can be done with Script like this: var rg = Spectrum.Channel1.data // channel 1 time domain data var c = rg.length var t = rg[c-1] // last sample for(var i = 0; i < c; i++) rg.push(t) // 2x padding var rghz = Spectrum.Trace1.frequency var hz = 2.0*rghz[rghz.length-1] //var hz = 2.0*Spectrum.Frequency.Stop.value // scope sample rate Spectrum.Trace5.setSamples(rg, hz) Some other suggestions to improve the resolution: 1. For lower frequencies, with 1MHz sampling you can use the Scope to perform a longer recording. This will highly improve the resolution in the FFT view. 2. With AD you can select the second device configuration to have 16k Scope buffer. 3. You can select a higher bandwidth window, like rectangular or cosine. 4. In the latest beta version with CZT algorithm you can select higher number of bins, higher resolution. https://forum.digilentinc.com/topic/8908-waveforms-beta-download/ Here: - T1 is CZT BlackmanHarris 10x BINs, 244Hz resolution - T2 is FFT BlackmanHarris 4k BINs 2.4kHz resolution - T3 is FFT Cosine 4k BINs 2.4kHz resolution
  26. 1 point
    jpeyron

    VGA on Zybo

    Hi @Mukul, Here is a VHDL VGA project that has pixel clock frequencies for multiple resolutions. Here and here are non-digilent VGA tutorials. Here is a listing for different pixel frequencies and resolutions. best regards, Jon
  27. 1 point
    Hey @Phil_D I too had a problem with getting WaveForms to run automatically, and my group didn't find a way to make it work through the suggested code. However, we did have success when we commanded Python to simulate an F5 key press, which is a shortcut in WF to run the script. We used the library "uinput". Here's a sample of the actual command we used. I'm not certain that it's all you need, as I was not the primary Python programmer for this project, but at least it'll give you an idea of what needs to be done for this workaround. The sleep timers are there to give the program time to start and load the workspace. waveform_Call = subprocess.Popen("exec " + waveforms, shell = True) waveform_Call time.sleep(10) device = uinput.Device([ uinput.KEY_FN, uinput.KEY_F5, ]) time.sleep(1) device.emit_combo([ uinput.KEY_FN, uinput.KEY_F5, ])
  28. 1 point
    jpeyron

    Hello world program for zynq linux

    Hi @Ram, I moved your thread to a section where more experience embedded linux engineers look. best regards, Jon
  29. 1 point
    jpeyron

    ZYBO HDMI IN project

    Hi @birca123, I got the same errors when I loaded the applications. Looking at the last line says that the "BSP Project P/HDMI_IN_bsp has been successfully migrated" is a good thing. I was able to program the FPGA, run the application and the project to worked. I have updated the above linked HDMI project with my sdk portion done as well. I have also attached my SDK log so you can compare it to what you have. best regards, Jon SDK_LOG_HDMI_IN.txt
  30. 1 point
    jpeyron

    ZYBO HDMI IN project

    Hi @birca123, I would suggest to start with a fresh sdk portion of the project. To do this close SDK and delete the hdmi-in.sdk folder in the \Zybo-hdmi-in\proj folder. Then in vivado click file->export -> export hardware including the bitstream. Then launch SDK from Vivado by clicking in file and selecting launch SDK. Once in SDK and the HW platform is loaded click in file and import HDMI_IN and HDMI_IN_bsp from Zybo-hdmi-in\sdk. Once you have the HDMI_IN and HDMI_IN_bsp into your SDK project then program the FPGA Next open a serial terminal emulator like tera term and connect to the Zybo's com port. Set the baud rate to 115200 everything else should be left at default settings. Now connect the Zybo to the HDMI and VGA device. then in SDK right click on HDMI_IN and select run as->launch on hardware(system debugger). Do you see the serial terminal menu? Is there an image on the VGA device?
  31. 1 point
    thanks for the response. Greatly appreciated. I figured out what I had done wrong....I didn't select the Board properly. I had filtered/searched for the Basys3 board and when that was the only one on the screen I "thought" that was all I needed to do to select it. I pressed next......and that caused my problem. I finally realized I had to click in one of the fields for the selected/filtered board, which turns the whole line blue...and THAT selected the proper board. I figured it out by looking at the Project Part # (within the project) and realized it was NOT the Basys3 board. Stupid mistake. Thanks again for responding...and so quickly!
  32. 1 point
    JColvin

    Read out .log file from OpenLogger

    Hi @Peggy, I spoke with some of the firmware folks for WFL and OpenLogger and learned that they haven't yet implemented the parsing of the header into the Digilent agent yet. I did receive a picture that showed the structure of the header file, which I have attached below. Thanks, JColvin
  33. 1 point
    I see, thanks jpeyron
  34. 1 point
    jpeyron

    OpenCV and Pcam5-c

    Hi @Esti.A, We have a reVISION project here for the Zybo-Z7-20 that uses SDSoC and the OpenCV that should be useful for your project. best regards, Jon
  35. 1 point
    Esti.A

    IP used in Zybo-Z7 MIPI Pcam 5C demo

    I achieved everything to work properlly. Thanks @jpeyron. Kind regards Esti
  36. 1 point
    If you want to set both pins at the same time, rather than in two separate statements, you could also do this: LATGSET = (1 << 15) | (1 << 6); // or 0b1000000001000000 These parts have registers that can do an atomic set/clear/invert, so that you don't have to do a read/modify/write of the register.
  37. 1 point
    Well geees. In typical fashion as soon as I expose my ignorance, I answer my own question. What I should have been using is the "Latch". This works like I had expected assigning a port would have. LATGbits.LATG6 = 1; LATGbits.LATG15 = 1;
  38. 1 point
    Hi, >> We are forced to work in assembly with picoblaze. you might have a look at the ZPU softcore CPU with GCC. The CPU is just a few hundred lines of code but most of its functionality is in software in the crt.o library in RAM. I understand it's quite well tested and has been used in commercial products. Not surprisingly, using an FPGA to implement a processor that then kinda emulates itself in software (aka RISC :) ) is maybe not the most efficient use of silicon - I'm sure it has many strong points but speed is not among them... Unfortunately, the broken-ness of Xilinx' DATA2MEM utility (to update the bitstream with a new .elf file) spoils the fun, at least when I tried in ISE14.7 (segfaults). When it works, the compile/build cycle takes only a second or two. Long-term, porting the processor to a new platform would be straightforward, or even fully transparent if using inferred, device-independent memory. This would also work for a bootloader that is hardcoded into default content in inferred RAM. I might consider this myself as a barebone "hackable" CPU platform strictly for educational purposes.
  39. 1 point
    bogdan.deac

    Inter core communication

    As far as I know the NN training phase takes long time and needs many resources. For this reason it is not recommended to train NN on FPGAs. On the other hand, FPGA is strong in inference. I advise you to use GPU and a learning framework, like Caffe, for the training phase. Fortunately, Xilinx released recently a new development kit for NN named Deep Neural Network Development Kit (DNNDK). Here you have the user guide and the DNNDK extension for SDSoC. Have a look on the Xilinx documentation and forum posts to get familiar with all concepts. Let us know if you have any questions.
  40. 1 point
    zygot

    How do I select the right FPGA board?

    I really don't know where to put this so I decided to ask myself a question and then propose an answer. Perhaps there needs to be a new home for basic assistance for users. A frequent question for beginners and even experienced people resolves around how to select an FPGA development board. The answer depends on what you want to do with it. The analysis can be anywhere from simple to complex. But there are three issues to resolve that will simplify the process of making a selection. Three questions that only you can answer are: What do you want to do with the hardware ? What is your budget ? What is your experience level ? For our context I'll be ignoring a 4th question, which might be the real driver for your interest. That question is: "What are your goals?". If you are just curious then that's different than if you want to add marketable skills to your resume. Also, you might perceive knowing how to develop with a particular device, such as Zynq, as an over-arching motivation. My view is that the Zynq is a great solution for a number of problems for a competent FPGA developer but except for running Ubuntu almost anything that I can do in software can be done with logic resources in an FPGA. On the theory that goals tend to change with experience and knowledge I'm going to proceed without answering that question. So let's group some possible answers to the responses to the previously listed questions and provide a bit of guidance. Case 1: 1) $0 OR 2) either "I don't know" or "I just want to learn how to use an FPGA". OR 3) None If you don't have a specific hardware project requiring an FPGA you don't need to spend anything to learn or develop FPGA applications and I suggest that you don't. Just get the latest version of Vivado or ISE. You can do everything except spend time debugging hardware with nothing more than Vivado or ISE. If you have no experience with VHDL or Verilog then I strongly suggest buying a used textbook but this is not a requirement. Xilinx provides information about how to use its devices and tools but assumes that you know enough about an HDL to accomplish synthesis or simulation for a project. Learning an HDL in the context of a directed or group setting is easier than teaching yourself, but not necessary. FPGA devices are complex and the tools are complex and no one is going to spend a Saturday afternoon reading the Xilinx literature and being a competent FPGA developer by Sunday. Understand that FPGA development is really just digital logic development. So if you come from a software background you might have to re-wire your brain a bit to grasp the basic concepts. Learn the basic concepts, how to be fluent in an HDL for both synthesis and simulation and how to know how to simulate effectively. You simply can't do competent FPGA development unless you know how to write a testbench in your HDL and perform effective simulation. You don't need to read the vendor manuals for the resources in any particular FPGA device but having an understanding of what and FPGA is certainly can't hurt. Case 2: 1) "not much" AND 2) "Nothing in particular but simple logic designs" AND 3) I'm competent using an HDL, simulator tools, and Vivado or ISE If these are your answers then the advice for case 1 might still be valid. It's true that most of us need some form of positive feedback to motivate us to do hard work. An FPGA development board might just do the trick. So my advice is simple. Spend the least amount possible. There are decent boards with a JTAG programming and minimal interface resources available such as the CMOD or DE0-NANO for < $100. Aside from the motivation factor you still don't need hardware to accomplish even complicated designs so why spend money until you know what to spend you money on? If you are determined to spend your allowance then start off with the least expensive and least expensive to replace board. The buttons, LEDs and switches can all be simulated. For basic HDL designs you can use global clock buffers and not worry about anything except pin location constraints. Case 3: 1) "not much" AND 2) "I want to use and FPGA to build a variety of hardware prototypes that don't require using advanced FPGA IO features" AND 3) "I'm competent using an HDL, simulator tools, and Vivado or ISE plus I'm reasonably competent designing with digital, analog or mixed-signal devices." For this case there are a number of inexpensive modules that offer 30 or more GPIO and basic functionally, but more importantly have the IO on headers that are easy to connect to a PCB of your own design that performs a specific function. In this case the FPGA development board is more of a component and might be dedicated to one prototype. There are a number of inexpensive modules from Digilent, Terasic and other vendors that might be ideal. You can make some pretty useful things with one of these modules and PCB vendors offering free layout and design tools like ExpressPCB. Here are some specific considerations in making a choice: What kind of documentation is provided? What kind of customer support is available? What kinds of demo projects are available and can I actually build them with my tool version Now of course merely understanding the manuals for clocking, IO, and other resources of a particular device isn't sufficient. You need to be able to make use of the device datasheet, especially the AC specifications. To give you an idea here is a table of useful switching specifications for a number of Digilent boards that I own ( the CMOD-A7 is an Artix-1 device ). Nexys Video Genesys2 ATLAS Artix(-1) Kintex(-2) Spartan6(LX-3) DS181 DS182 DS162 ----------- ----------- -------------- Fmax_bufg 464 710 400 Fmax_bufh 464 710 - Fmax_bufr 315 540 - Fmax_bufio 600 800 - Fmax_bufio2 - - 525 Fmax_buffpll - - 1050 Fmax_buffgmux - - 400 PLL_Finmax 800 933 525 PLL_Finmin 19 19 19 PLL_Foutmax 800 933 1050 PLL_Finmain 6.25 6.25 3.125 PLL_vcomax 1600 1866 1050 MMCM_Finmax 800 933 - MMCM_Finmin 10 10 - MMCM_Foutmax 800 933 - MMCM_Finmain 4.69 4.69 - Fmax_bram_xxx 297-388** 427-544** 280 Fmax_fifo 388* 544* - Fmax_dsp48e 177-464** 249-650** - Fmax_dsp48a - - 333** All values in MHz - not applicable * non-ECC mode ** depends on modes used [Update] Interesting SERDES performance specifications: Kintex-2 Artix-1 SDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 - 8 HR 710 600 Mb/s HP 710 - Mb/s DDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 14) HR 1250 950 Mb/s HP 1400 - Mb/s SDR LVDS receiver (SFI-4.1)(1) HR 710 600 Mb/s HP 710 - Mb/s DDR LVDS receiver (SPI-4.2)(1) HR 1250 950 Mb/s For Spartan6-3 (Network) SDR LVDS transmitter or receiver (using IOB SDR register) 400 Mb/s DDR LVDS transmitter or receiver (using IOB ODDR2/IDDR2 register) 800 Mb/s SDR LVDS transmitter (using OSERDES2; DATA WIDTH = 2 to 8 1050 Mb/s DDR LVDS transmitter (using OSERDES2; DATA WIDTH = 2 to 8 1050 Mb/s SDR LVDS receiver (using ISERDES2; DATA WIDTH = 2 to 8 1050 Mb/s DDR LVDS receiver (using ISERDES2; DATA WIDTH = 2 to 8 1050 Mb/s You also need to understand thermal management. Some of these boards don't have much copper mass and do have a lot of heat dissipating components in a very small area. It is likely that you will have issues trying to push these modules to the extreme limits for an application even with their limited power supply resources. If what you need is for some custom logic and <100 MHz switching and a few are output pins then you aren't likely to have problems, assuming that you properly terminate your IO signals. Since you are competent doing digital and analog design you know the differences between a .1" header and and HSMC or FMC connector as far as signal integrity characteristics are concerned. You also understand from the FPGA vendor's literature the termination requirements for all supported logic standards and clocking limitations. Case 5: 1) "Less than $2000" AND 2) "I want to experiment with using advanced IO resources" AND 3) "I'm competent using an HDL, simulator tools, and Vivado or ISE plus I'm reasonably competent designing with digital, analog or mixed-signal devices." In order to get experience using the advanced IO features or transceivers available in current generation FPGA devices you need a board that is designed to allow you to use these features. I bought a Genesys2 primarily because the way that they implemented mDP allowed me to experiment with multi-lane transceiver designs. The HPC FMC connector was a bonus but you have to do your homework if you plan on using a mezzanine board and the FMC connector. In particular, there are a lot of "FMC" mezzanine cards that aren't necessarily suitable for the Genesys2 FMC implementation or are even particularly VITA-57 compliant. Usually, this has to do with clocking and IO bank pin assignments. If you want to use a particular FPGA carrier board with a particular FMC type mezzanine card you have to trace through all of the pin assignments to make sure of compatibility. This is particularly true for differential LVDS IOSERDIES2 applications. In general it's easier to find an HSMC mezzanine card FPGA carrier board combination but you still have to do your homework as there are differences between differential signal pairs routed as differential pairs and differential signal pairs simply having matched trace lengths. If you have a bus of differential signals trace length matching across pairs is important. I've used the Nexys Video and Genesys2 boards for a number of projects using the FMC mezzanine cards with complete success. I've not been able to use either of those boards to connect every FMC card that I wanted to use. It is unlikely that you will find an FMC mezzanine card designed to work with an Intel based FPGA board that can be used on a Xilinx based FPGA board. It all has to do with pin assignments. This isn't a deficiency of the FMC implementation of the Digilent boards are even of the mezzanine boards, just an incompatibility for particular FPGA device pin locations and signal assignments. If you only get one takeaway from this thread this is it... just because it's on an FMC or HSMC connector doesn't mean you can use it with your FMC or HSMC equipped FPGA board. Digilent's current crop of FPGA boards provides either low speed PMOD connectors (<10 MHz) which are ease to connect to a custom PCB or high density FMC connectors which are expensive and difficult to connect to a custom PCB. No one knows what the so called high-speed PMODs were designed to do, but they aren't suitable for advanced IO experimentation. If you want to experiment with transceivers you need to read the Xilinx transceiver user manual and know the difference between GTP, GTH and GTY transceiver implementations and maybe those from other vendors. Before choosing a general purpose board to explore advances IO I suggest: Have a thorough understanding of advanced constraints beyond location and IOSTANDARD. There are user manuals for this. Have competence in timing closure methodologies. Read the manuals. Thoroughly understand the Series7 IO, clocking, and transceiver users' manuals Pore over the board documentation, especially the schematics, for boards on your short list. A lot of FPGA board vendors will make you do the work to figure out which banks specific IO pins are assigned to. Make sure that the support includes applicable demo projects that you can build them targettin that particular board with your version of Vivado easily. Figure out what IP if any you need to do something useful with your advanced IO plans. Case 6: 1) "The minimal to accomplish the project" AND 2) "I have a very specific project to complete using specific advanced IO resources" AND 3) "I'm competent using an HDL, simulator tools, and Vivado or ISE plus I'm reasonably competent designing with digital, analog or mixed-signal devices." For this case the analysis gets complicated. If you want need to do video or Ethernet based communication there might be a board that fits your specific needs for a particular project. The general rule is that buying hardware that isn't designed to accomplish a particular purpose is rarely a good investment. 10G Ethernet is a different animal than Gigabit Ethernet. 12G SDI video is a different animal than HDMI video. You need to verify that either the board can do what you want to do or provides the IO in a form that let's you add a mezzanine card to it to do the job. Neither of these investigations is necessarily straightforward or easy. So by now you probably realize that each of the cases that I posit involve building an ever increasing level of competence and body of expertise. So everything that applies to the previous cases applies here except that you now have to select all of the boards that will allow you to complete your project. If you need to have a temporoary or time-restricted license to complete your project then what good will that be next year? Clearly I haven't addressed all of the possible scenarios for the three questions put forth in the beginning but hopefully I've presented the basic ideas for a wide range of people willing to take the time to read it. One case that I didn't address is where you want to do something using one of the many PMODs available for purchase and want to create an HDL solution to accomplish something. Again, the cheapest board available with the most standard PMODs will likely be what you want. Make sure that you understand what will be provided for you and what you needs to do for yourself. This is a small universe but one in which a lot of people will happily spend there lives. A lot of what's been presented is 'common sense', whatever that is. If you've never ridden a bike but saw the Tour de France and want to dip your toe into competitive racing the first thing to do is not spend 100's of dollars on shoes, helmets, clothes and $10K on a road bike that's just over your wildest budget ( you know because you're going to grow into it...). If, once you know what you're doing, you decide that you want to do mountain trail racing none of that gear will be useful. Also learning how to ride in the company of a local bike club will be much more productive and fun than spending weeks on the couch reading books on technical riding concepts. I hope that this provides some things to consider for the many of you not having the experience with a lot of FPGA development boards and projects. I apologize for the rough formatting....
  41. 1 point
    jpeyron

    IP used in Zybo-Z7 MIPI Pcam 5C demo

    Hi @Esti.A, Can you be more specific? The Vivado library branch here has the updated MIPI_D_PHY_RX and MIPI_CSI_2_RX. These IP Cores were updated by the creator of these IP cores and should work are described in this forum thread here. Here is a forum thread that discusses some of the difference between Digilent's MIPI_D_PHY_RX and MIPI_CSI_2_RX IP Cores and those that are available for purchase. best regards, Jon
  42. 1 point
    Hi @Luighi Vitón, I'm not sure it's a HDMI issue, have you tried to use X11 over SSH do you get the same result? -Ciprian
  43. 1 point
    gummadi Teja

    FFT / iFFT / RS - Basys3

    thank u sir i complete my code for fft using cordic algorithm..
  44. 1 point
    Hi @askhunter, The top.vhd is already added to the project. If you are wanting this file to be underneath the design_1 then you should right click on the design_1 and select add sources. Then add the vhdl files you would like to add to the design. It might be easier to start with a fresh project. best regards, Jon
  45. 1 point
    jpeyron

    Arty A7 vs Nexys A7

    Hi @Phil, The Arty-A7-100T comes with with a built in USB JTAG/UART (J10) programming circuit.You will not need an additional JTAG programmer like the JTAG-HS2 to configure the Arty-A7-100T. Here is the Arty A7 resource center. Under Additional Resources there is a tutorial called getting started with microblaze servers that goes through making an ethernet echo server with the Ethernet lite IP Core (no cost). best regards, Jon
  46. 1 point
    CVu

    Nexys 2 - transistor part number

    Transistor has been replaced, board is back up and running. Thanks!
  47. 1 point
    CVu

    Nexys 2 - transistor part number

    Thank you very much Jon. Much appreciated.
  48. 1 point
    jpeyron

    Nexys 2 - transistor part number

    Hi @CVu, Welcome to the Digilent Forums! Q1 information is below: NTS2101P Single P-Channel Power Mosfet 1.4A, 8VSOT-323 (SC-70) best regards, Jon
  49. 1 point
    zygot

    NexysDDR4 example projects

    OS file permissions are a two-edged sword. It can prevent users from changing stuff that shouldn't be changed but it can prevent users from doing their work unintendedly This is a user issue. You will have to learn how to change file permissions as a computer user to the extent that your privileges allow. Depending on the OS and how security is set up this can be a pain, especially when transferring files form one OS or computer to another one. If you have an IT department they should be able to help resolve issues. If you are the IT department then you need to learn how to set up and use your OS safely and securely.
  50. 1 point
    Hi @Nithin Yes. See the AnalogIO_DigitalDiscovery.py how to adjust the IO voltage, enable VIO output, set pull-up/downs, slew rate, drives The DigitalIO functions can be used the same way controlling DIO[24:31] The DigitalOut functions are the same but you have 32k custom bit/line for DIO[24:31] The DigitalIn by default samples DIN[0:23]&DIO[24:31]. To sample DIO lines first DIO[24:39]&DIN[0:15] set FDwfDigitalInInputOrderSet(hdwf, true). This way if you sample 16 bits you will get DIO[24:39]. The base frequency is 800MHz (FDwfDigitalInInternalClockInfo), like use FDwfDigitalInDividerSet(hdwf, 8 ) for 100MHz